Copper CMP at Advanced Nodes (7 nm and Below): ELK Dielectrics, Cobalt Liners & Slurry Innovations

1. How Advanced Nodes Redefine Cu CMP Requirements

At 28 nm and above, copper CMP is fundamentally a controlled removal problem: remove copper fast, stop accurately, minimize dishing and erosion. The slurry formulation and process parameters have known, well-characterized design windows, and the primary challenge is maintaining statistical process control within those windows across millions of wafers.

Below 7 nm, this shifts to a constraints-first problem: the hard limits imposed by material fragility, dimensional tolerances, and new device architectures are so tight that the entire slurry formulation and process architecture must be rebuilt around them. The table below summarizes how the key process constraints evolve across nodes:

The trajectory is clear: each successive node generation compresses the process window, tightens every tolerance, and introduces new materials that require fundamental reformulation. This is why advanced-node copper CMP slurry development is a continuous R&D investment rather than a one-time qualification effort.

2. Ultra-Low-k Dielectric Fragility: The Pressure Constraint

The dielectric constant of the ILD material surrounding copper interconnects must decrease with each node generation to limit capacitive coupling between adjacent metal lines — the dominant contributor to RC delay and power consumption in dense multilevel interconnects. This requirement drives the industry toward progressively more porous organosilicate glass (OSG) and SiCOH dielectric films:

• 45 nm node: dense CVD SiO₂/fluorosilicate glass (FSG), k ≈ 3.5–4.0, elastic modulus ≈ 70 GPa
• 22 nm node: porous OSG, k ≈ 2.7–3.0, elastic modulus ≈ 10–20 GPa
• 7 nm node: ultra-porous OSG (ELK), k ≈ 2.3–2.5, elastic modulus ≈ 5–10 GPa
• 3 nm class (2026): air-gap assisted ELK, effective k ≈ 2.0–2.2, structural modulus of remaining solid phase ≈ 3–7 GPa

The mechanical consequence of this porosity-driven dielectric constant reduction is severe: the elastic modulus of ELK films at 7 nm is 7–14× lower than conventional SiO₂, making the dielectric stack dramatically more susceptible to fracture, delamination, and plastic deformation under CMP contact stress.

The critical failure mode under excessive CMP pressure in ELK stacks is cohesive fracture within the porous ELK layer itself, or adhesive delamination at the ELK/etch-stop interface. The etch stop (typically dense SiCN or SiN) has a Young’s modulus 5–10× higher than the ELK it caps, creating a mechanical impedance mismatch at the interface that concentrates stress under shear loading. The critical polishing pressure for delamination onset is approximately 1.5 psi at 7 nm and decreases to below 0.7 psi at 3 nm-class ELK stacks.

Chemical Compensation for Reduced Mechanical Input

Reducing polishing pressure below 1 psi severely limits the mechanical contribution to copper removal rate in the Preston equation. To maintain economically viable throughput, the chemical contribution must be enhanced: higher H₂O₂ concentration (3–5 wt% vs. 2–3 wt% at conventional nodes), lower BTA loading (to reduce the passivation film’s mechanical resistance), and more reactive complexing agents that accelerate Cu ion removal from the polishing interface. JEEZ’s CuELK series achieves 180–250 nm/min at 0.7 psi by targeting these chemical levers, accepting a tighter BTA-induced dishing window as the process cost.

3. Cobalt Liner Integration: Corrosion & Galvanic Challenges

Cobalt (Co) has emerged as the leading replacement for Ta/TaN in BEOL liner applications at 7 nm and below, driven by its ability to be deposited by CVD/ALD at thicknesses below 2 nm (physically impossible for PVD Ta/TaN films due to island growth), its lower bulk resistivity for very thin film geometries (<5 nm), and its compatibility with selective deposition processes that allow bottom-up liner deposition only in the feature interior.

However, cobalt introduces three specific challenges for copper CMP slurry:

Challenge 1: Co Electrochemical Susceptibility

Cobalt’s standard electrode potential (E° = −0.28 V vs. SHE) is less noble than copper (+0.34 V). In an oxidizing, slightly acidic CMP environment, cobalt is thermodynamically driven toward dissolution as Co²⁺. Unlike tantalum, which forms a dense, passivating Ta₂O₅ native oxide that kinetically suppresses this thermodynamic driving force, cobalt’s native oxide (CoO, Co₃O₄) is less dense and less protective in the CMP pH/oxidizer environment. This means cobalt actively corrodes in standard Step 1 copper CMP slurry conditions — a problem that becomes visible as liner thinning, pitting at the via/trench intersection, and via resistance increase.

Challenge 2: Cu/Co Galvanic Couple

When copper and cobalt are simultaneously exposed to the slurry electrolyte during Step 2 polishing — as occurs during barrier clearing — they form a galvanic couple. The potential difference (Cu at +0.34 V vs. Co at −0.28 V = 0.62 V difference) drives cobalt anodic dissolution: cobalt acts as the sacrificial anode, copper is cathodically protected. At the geometry scale of advanced-node interconnects, where the Co liner may be only 1–2 nm thick, even modest galvanic current densities can dissolve the liner completely in the time required to clear barrier at Step 2 polishing conditions.

Challenge 3: BTA’s Limited Co Inhibition

BTA forms a stable passivation film on copper through the Cu(I)-BTA coordination complex mechanism. On cobalt, BTA’s N-coordination chemistry is less effective: Co²⁺ forms weaker complexes with BTA’s triazole nitrogen atoms than Cu⁺, and the resulting Co-BTA film is thinner, less coherent, and more permeable to the oxidizer. A Co-specific corrosion inhibitor — with higher affinity for Co surface sites — is required in Step 2 slurries used with Co liner processes.

JEEZ’s CuS-Co series addresses all three challenges through: near-neutral pH (6.5–7.5) to moderate Co corrosion kinetics; reduced H₂O₂ concentration (0.5–1 wt% rather than 2–4 wt%); and a proprietary dual-inhibitor system providing both Cu(I)-BTA passivation and Co-specific surface protection simultaneously.

4. Ruthenium Liner: Inverted Galvanic Pair & Process Implications

Ruthenium (Ru, E° ≈ +0.45 V vs. SHE for Ru²⁺/Ru) has also attracted significant interest as a liner/barrier material due to its very low bulk resistivity (7.1 µΩ·cm), excellent compatibility with selective CVD processes, and superior electromigration resistance compared to cobalt at equivalent thickness. Several leading-edge foundries are qualifying Ru-liner processes for their most advanced nodes as of mid-2026.

The galvanic situation with Ru is the opposite of cobalt: ruthenium is slightly more noble than copper (E° Ru ≈ +0.45 V vs. Cu at +0.34 V). This inverts the galvanic couple: at the Cu/Ru interface, copper is the anode and is preferentially dissolved — potentially accelerating copper dishing at the trench edge where copper contacts the Ru liner. This manifests as edge dishing — anomalously deep copper recess at the line edges compared to the line center — and can increase effective line resistance above what would be predicted from the average dishing value alone.

Mitigating Cu/Ru galvanic dishing requires: tight control of the Cu:Ru removal rate ratio in Step 2 (targeting a ratio close to 1:1 during the copper residual clearing phase before Ru is exposed), careful optimization of pH and oxidizer to minimize the electrochemical potential difference at the Cu/Ru interface, and possibly Ru-targeted passivation additives that slow Ru removal relative to Cu during the period when both are exposed simultaneously.

5. Narrow Trench Challenges at Sub-10 nm Geometries

At metal half-pitch below 10 nm — now achievable with EUV lithography and pattern complementation at the 3 nm class — copper CMP faces dimensional challenges that have no analog at earlier nodes.

Dishing Tolerance of ±1 nm

A copper line with a 10 nm × 20 nm cross-section (width × height) that dishes by 2 nm loses 10% of its conducting cross-section. With a target line resistance increase budget of <5%, the allowable dishing is ±1 nm — of the same order as the slurry’s static etch rate per 30 seconds of over-polish time. This means every second of over-polish beyond endpoint has a measurable impact on electrical performance. Endpoint must be controlled to better than ±3 seconds at typical Step 2 removal rates, requiring eddy-current sensing with sub-nm resolution or friction-based endpoint with very high signal-to-noise ratio.

Abrasive Exclusion from Sub-15 nm Features

Abrasive particles with D50 of 80–150 nm cannot physically enter via features with diameters below 15 nm. This geometric exclusion means that the CMP mechanism inside narrow vias is purely chemical — oxidizer and complexing agent must diffuse into the feature and remove copper without any mechanical abrasive assistance. The implications are that the chemical SER becomes the rate-limiting factor for via clearance, and that BTA loading must be minimized (to allow some chemical dissolution inside the vias) while being sufficient to protect the recessed line copper below the via. This SER vs. dishing balance is more delicate at sub-15 nm than at any previous technology generation.

Surface Roughness at Ra <0.3 nm

At 3 nm-class nodes, the surface roughness of the polished copper must be below 0.3 nm Ra to ensure uniform barrier deposition coverage and consistent copper seed layer growth on the next interconnect level. Achieving Ra <0.3 nm requires: very narrow abrasive particle size distribution (D99/D50 < 2.5), pad asperity height RMS below 1 µm (achieved through aggressive in-situ conditioning), and a Step 3 buff with sub-30 nm abrasive or abrasive-free colloidal chemistry.

6. Hybrid Bonding Cu Pad CMP: Controlled Recess Engineering

Hybrid bonding — direct copper-to-copper and dielectric-to-dielectric bonding between stacked dies or wafers — is the enabling technology for 3D chip stacking architectures deployed in AI accelerators, HBM memory, and advanced logic-on-logic packaging. As of 2026, hybrid bonding is in production at multiple leading advanced packaging facilities worldwide.

Hybrid bonding requires a completely different CMP application than BEOL interconnect planarization. The copper bonding pads must be polished to:

• Nanometer-scale planarity across the full 300 mm wafer (WIWNU <0.5 nm for the copper recess depth).
• A controlled copper recess of −1 to −3 nm relative to the surrounding SiO₂ dielectric surface — intentional and precisely targeted, not a defect to be minimized.
• Surface roughness below 0.5 nm Ra on both the copper and dielectric surfaces to ensure intimate bonding contact across the entire pad area during thermocompression bonding.

The controlled recess requirement is unique: for hybrid bonding, a specific amount of dishing is the target, not zero. The recess allows the dielectric surfaces to bond first under thermocompression (providing alignment stability), then the recessed copper expands under the bonding temperature to fill the gap and form the metal-to-metal electrical connection. Too little recess (<0.5 nm): copper contacts first during bonding, preventing dielectric surface contact and degrading bond strength. Too much recess (>5 nm): copper cannot fully close the gap at bonding temperature, leaving an open circuit or a high-resistance interface.

JEEZ’s CuHB slurry series achieves reproducible copper recess in the 1–3 nm range with wafer-level standard deviation below 0.5 nm through precision control of BTA concentration (governing SER) and polishing time (down to ±1-second accuracy with in-situ endpoint feedback). The formulation uses sub-30 nm colloidal silica abrasive to achieve the Ra <0.3 nm surface quality required for reliable bonding yield.

7. Backside Power Delivery & GAA NSFET Cu CMP

Two architectural innovations at the 2 nm class and beyond are creating new copper CMP application requirements beyond traditional BEOL interconnect:

Backside Power Delivery Network (BSPDN)

Traditional logic chips route power (VDD/VSS) through the front-side metal stack, competing with signal routing for wiring resources and contributing to IR drop. Backside power delivery (BSPDN) moves power rails to the back surface of the silicon wafer, freeing the front-side BEOL for signal wires exclusively. This requires new copper CMP processes on the wafer backside — where the mechanical environment, thermal budget, and contamination constraints differ significantly from front-side BEOL.

Backside copper CMP must be performed after wafer thinning (to <50 µm), on a bonded carrier wafer, with strict temperature limits (typically <200°C total thermal budget) to protect completed front-side circuits. The CMP chemistry must be free of metal ion contamination that could diffuse through the thinned silicon to the transistor active regions. JEEZ’s CuB and CuS formulations meet backside CMP metal purity requirements (<10 ppb Fe, Al, Na, K) by standard specification.

GAA Nanosheet (NSFET) Metal Gate CMP

Gate-all-around (GAA) nanosheet transistors — the standard transistor architecture at 2 nm class and below — use a different contact and power via metallization scheme than FinFET generations, introducing new copper CMP touch points in the front-end-of-line (FEOL) contact level. The specific CMP requirements depend on the integration scheme but share the common challenges of high-aspect-ratio feature filling, extreme planarity requirements (WIWNU <1 nm), and compatibility with high-k/metal gate stack chemistry.

8. Slurry Innovation Trends in 2026

The advanced-node challenges described above are driving an acceleration in copper CMP slurry innovation across the industry. The leading development directions as of July 2026 include:

• Sub-20 nm engineered colloidal silica with narrow PSD (D99/D50 < 2.2) for minimal scratch risk on ELK and for geometric access to sub-15 nm via features.
• Dual-metal inhibitor systems providing simultaneous Cu and Co/Ru passivation — replacing BTA-only formulations in all advanced-node Step 2 applications where Co or Ru liners are present.
• BTA-free azole and MBI-based formulations gaining production qualification status as environmental compliance programs broaden to include all persistent organic compounds, not only PFAS.
• AI-assisted formulation optimization using density functional theory (DFT) and molecular dynamics simulations to predict inhibitor adsorption geometry, passivation film stability, and removal selectivity before physical synthesis — reducing formulation cycle times by 40–60%.
• In-line real-time slurry monitoring with particle count, pH, oxidizer concentration, and BTA content measured continuously at the POU dispense arm, feeding APC loops that adjust slurry delivery in real time to maintain target chemistry within ±2% of nominal.
• Precision recess control slurries for hybrid bonding achieving <0.5 nm wafer-level σ on copper recess depth — enabling the tightly controlled bonding geometry that 3D integration yield requires.

At Jizhi Electronic Technology Co., Ltd. (JEEZ), all six innovation directions are active development programs in our R&D pipeline, with CuELK, CuS-Co, CuHB, and CuG product lines already in customer evaluation or production qualification as of mid-2026.

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