Polishing Templates for Compound Semiconductor Wafers: GaAs, InP & Sapphire
III-V compound semiconductors and sapphire demand polishing templates that silicon engineers rarely encounter: softer pads to protect fracture-prone crystals, chemically resistant carrier plates for bromine and acid slurries, and careful EER design for materials that chip rather than yield. This guide covers each substrate in full.
Why Compound Semiconductors Need Different Templates Than Silicon
Silicon wafer polishing is the reference process against which all other semiconductor polishing is measured — it runs at moderate pressures with alkaline slurries on a substrate that, while brittle, has enough fracture toughness to tolerate normal process variability without catastrophic yield loss. The polishing templates designed for silicon reflect these forgiving conditions: medium-hardness backing pads, FR-4 or G-10 carrier plates at alkaline pH, and process pressures that leave considerable margin before fracture risk becomes significant.
Compound semiconductors — GaAs, InP, and related III-V materials — and oxide substrates like sapphire do not share these forgiving properties. Each presents a distinct combination of challenges that requires deliberate template engineering rather than adaptation of the silicon template specification. Understanding polishing template fundamentals is the starting point, but the substrate-specific details covered in this article are what prevent the breakage rates, contamination failures, and edge exclusion problems that occur when silicon-derived template assumptions are applied to compound semiconductor processing.
Fracture Risk: The Primary Design Constraint for III-V Substrates
The single most important property distinguishing III-V compound semiconductor substrates from silicon for polishing template design is fracture toughness — the material’s resistance to crack propagation once a stress concentration (such as an edge chip or surface scratch) initiates a crack.
GaAs fracture toughness is approximately half that of silicon; InP is even lower, at roughly one-third. This means that stress concentrations which a silicon wafer tolerates without consequence — from carrier head pressure non-uniformity, from retaining ring contact, from an edge chip during loading — can propagate to full wafer fracture in GaAs or InP. Sapphire, by contrast, has higher fracture toughness than silicon, but its extreme hardness (Mohs 9.0) and near-chemical inertness create different challenges: very slow polishing rates, acidic slurry requirements, and long polishing cycles that stress template chemical compatibility.
The fracture risk from thermal stress is an additional, often overlooked factor for III-V substrates. GaAs has a coefficient of thermal expansion (CTE) of 5.73 × 10⁻⁶/°C — more than twice silicon’s 2.6 × 10⁻⁶/°C. When a GaAs wafer is bonded to a wax mount block using conventional wax mounting procedures at 70–85°C, the differential CTE between the wafer and the polishing block creates biaxial thermal stress during the cooling cycle that routinely causes wafer cracking in the 50–200 µm thickness range. This is the primary reason waxless polishing templates are not merely preferred but effectively mandatory for production GaAs and InP polishing. The full waxless vs. wax comparison, including the CTE mismatch quantification, is in our waxless vs. wax mounting guide.
GaAs Polishing Templates
Gallium Arsenide (GaAs) — Template Engineering Guide
The GaAs Polishing Challenge
GaAs combines low fracture toughness with well-defined {110} cleavage planes that run parallel to the flat or notch on the wafer. Any stress concentration that exceeds the cleavage plane’s fracture toughness threshold — whether from mechanical contact at the wafer edge, from differential thermal expansion, or from polishing pad pressure non-uniformity — propagates instantly along the cleavage plane, splitting the wafer rather than creating a localized chip. This makes GaAs polishing less forgiving of edge stress than any other common semiconductor substrate.
The chemical challenge compounds the mechanical one. GaAs contains gallium and arsenic — both of which oxidize in aqueous environments. Standard alkaline silica slurries produce a Ga₂O₃/As₂O₃ surface oxide that is not efficiently removed by silica abrasives, leading to unacceptably slow removal rates and surface contamination. Effective GaAs polishing requires bromine-based chemistry that dissolves the surface oxide chemically as it forms, maintaining a reactive surface for mechanical removal. This bromine chemistry is corrosive to FR-4 and G-10 carrier plate materials.
Template Specification for GaAs
Carrier plate material: G-10 minimum, CXT preferred. Bromine-methanol slurry at pH 4–7 is marginal for G-10 (20–40% longer life than FR-4, but still limited at high cycle counts) and incompatible with FR-4. For production runs above 50 cycles per lot, CXT-grade is the recommended carrier plate material for GaAs polishing. G-10 is acceptable for low-volume R&D use where template replacement frequency is not a cost constraint.
Backing pad hardness: Shore A 30–50 (soft). This is the most important GaAs-specific template parameter. Soft pads serve two purposes: they average out carrier head pressure non-uniformities that would otherwise concentrate stress at the wafer edge, and they reduce the shear force applied to the wafer during lateral loading in the work hole. A medium-hard pad (Shore A 60–70, appropriate for silicon) produces edge pressure concentrations sufficient to initiate cleavage-plane fractures in GaAs at process pressures as low as 2–3 psi. Soft pad specification is non-negotiable for production GaAs polishing.
Work-hole radial clearance: 0.15–0.25 mm. Tighter than the 0.3–0.5 mm standard for silicon. GaAs’s tendency to slide along cleavage planes means that excess lateral freedom in the work hole creates intermittent contact between the wafer edge and the work-hole wall during polishing, which is a crack initiation source. Tighter clearance prevents this contact while the soft backing pad provides the compliance needed for pressure uniformity.
Process pressure: 1–3 psi maximum. GaAs polishing operates at the lower end of the SSP pressure range. Higher pressures increase both the removal rate and the fracture risk in proportion — the marginal yield improvement from higher pressure is rarely worth the breakage rate increase.
InP Polishing Templates
Indium Phosphide (InP) — Template Engineering Guide
InP: The Most Fracture-Sensitive Production Substrate
Indium phosphide has the lowest fracture toughness of any commonly produced semiconductor substrate — 0.32 MPa·m½, approximately 45% of GaAs and less than half of silicon. This extreme brittleness, combined with well-defined {110} cleavage planes, makes InP the substrate where polishing template design decisions have the largest impact on breakage rate. InP wafers are expensive (typically 3–8× the cost of equivalent-diameter GaAs) and are often processed in small lot sizes for telecom and photonic applications, making each breakage event economically significant.
The fracture propagation speed in InP is effectively instantaneous once the fracture toughness threshold is exceeded — there is no plastic deformation or crack arrest mechanism that might limit damage in a more ductile material. This means that template design for InP must be preventive rather than damage-limiting: the template must be engineered to prevent any stress concentration from reaching the fracture initiation threshold, because once initiated, fracture is total.
Template Specification for InP
Carrier plate material: CXT-grade strongly recommended. InP polishing slurries — typically HBr/Br₂-based (pH 5–7) or NaOCl-based alkaline chemistry — are corrosive to both FR-4 and G-10. CXT-grade is the production standard. Because InP lot sizes are typically small (25–100 wafers/lot), the higher template cost per unit is less significant relative to the wafer cost being protected.
Backing pad hardness: Shore A 25–45 (ultra-soft). InP requires the softest backing pads used in any semiconductor polishing application. Even Shore A 50 pads, acceptable for GaAs, can produce sufficient edge pressure concentration to initiate cleavage in InP at 1–2 psi. Shore A 25–40 pads are recommended for production InP polishing. These ultra-soft pads significantly limit pressure uniformity and material removal rate efficiency — a deliberate trade-off that prioritizes breakage prevention over throughput optimization.
Work-hole radial clearance: 0.15–0.20 mm. Tight clearance, as for GaAs, to prevent edge-wall contact. InP wafers typically have slightly less precise incoming diameter control than silicon prime wafers, so the clearance specification must account for OD variation — measure incoming wafer OD from each lot before specifying the work-hole diameter.
Multi-wafer template design consideration. Many InP polishing templates are designed for single-wafer-per-carrier operation rather than the multi-cavity templates common for silicon, because the precise centering of each wafer in its work hole is more critical for InP than for more fracture-resistant substrates. In a multi-cavity template, small differences in work-hole centering between cavities create differential pressure profiles that increase cleavage risk for the off-center wafers.
Sapphire Polishing Templates
Sapphire (Al₂O₃) — Template Engineering Guide
Sapphire: Hard, Chemically Inert, and Anisotropic
Sapphire’s polishing challenges are the inverse of InP’s: where InP is dangerously fragile, sapphire is mechanically robust. The template design concern for sapphire is not breakage prevention but chemical compatibility with acidic diamond slurries, handling of the long polishing cycle times required by sapphire’s extreme hardness, and managing the anisotropic polishing behavior that results from sapphire’s trigonal crystal structure.
Sapphire’s CTE anisotropy — the a-axis and c-axis thermal expansion coefficients differ by approximately 8% — creates internal thermal stress when the wafer is heated or cooled non-uniformly. This anisotropy makes sapphire more susceptible to thermally-induced warping during extended polishing cycles than isotropic substrates. For polishing cycles exceeding 60 minutes, temperature control of the polishing table to ±2°C or better is recommended to prevent thermally-induced TTV excursions from sapphire warping during polishing — a process consideration that affects template selection indirectly through its interaction with the backing pad compliance.
Template Specification for Sapphire
Carrier plate material: G-10 for mild acid slurry; CXT for diamond slurry below pH 5. Sapphire polishing uses diamond abrasive slurries at pH 3–9 depending on the polishing step. For initial coarse polishing with acidic diamond slurry (pH 3–5), CXT-grade is recommended. For final polishing with near-neutral to mildly alkaline silica slurry (pH 7–9), G-10 is adequate. FR-4 should be avoided for any sapphire polishing application using slurry below pH 8.
Backing pad hardness: Shore A 60–75 (medium-hard). Unlike the III-V substrates, sapphire’s high fracture toughness allows the use of medium-hard backing pads without significant breakage risk. Harder pads improve TTV uniformity for sapphire’s long polishing cycles by maintaining more stable work-hole depth control under sustained load. Shore A 65–70 is the most common production specification for 2-inch and 4-inch sapphire LED substrates.
EER for sub-2 mm edge exclusion. Sapphire LED substrate applications — particularly for 4-inch c-plane sapphire used in high-brightness LED production — often require sub-2 mm edge exclusion to maximize LED die count per wafer. EER design for sapphire follows the same principles as silicon, with EER heights in the 60–150 µm range appropriate for sapphire’s process pressures (2–5 psi) and medium-hard backing pads.
Multi-wafer templates for high-volume LED production. Sapphire LED substrate polishing at commercial scale uses multi-cavity templates (typically 3–7 wafers per carrier) to maximize polisher throughput. Multi-cavity sapphire templates require precise work-hole depth uniformity across all cavities (≤5 µm variation between cavities) to prevent wafer-to-wafer TTV variation within a single polishing run. CMM verification of all work-hole depths on each template is required for production qualification.
Shared Design Principles Across All Three Substrates
Despite their different physical properties and polishing chemistry requirements, GaAs, InP, and sapphire polishing templates share three fundamental design principles that differentiate them from silicon polishing templates.
1. Waxless Processing Is the Default, Not Optional
All three substrates benefit from or require waxless polishing templates. For GaAs and InP, waxless processing eliminates the thermal stress during wax bonding and debonding that is a primary source of cleavage-plane fractures in production. For sapphire, waxless processing eliminates the risk of differential thermal expansion stress from sapphire’s CTE anisotropy during the wax cycle. The economic case for waxless processing — lower total cost per wafer, higher throughput, zero organic contamination — is covered in detail in our waxless vs. wax mounting comparison.
2. Chemical Compatibility Must Be Verified Against the Actual Slurry
All three substrates use slurry chemistries that are incompatible with FR-4 and marginal for G-10. Specifying the carrier plate material as “standard FR-4” for any of these substrates is a process engineering error that will produce template failures at predictable cycle counts. The correct specification workflow — state slurry pH range and oxidant components, then select carrier plate material — is covered in our 6-parameter specification guide.
3. First-Article Qualification Must Include Breakage Rate Data
For silicon templates, the primary qualification metrics are TTV, SFQR, and surface quality. For compound semiconductor and sapphire templates, breakage rate per 100 wafers polished is an additional mandatory qualification metric. A template that achieves excellent TTV but produces 2% wafer breakage in qualification is not a production-viable template, regardless of the flatness data. The backing pad Shore A specification and the EER height are the two template parameters most directly controllable to reduce breakage rate, and both must be validated against actual breakage data in qualification.
Slurry Chemistry Compatibility Summary
| Substrate | Slurry Chemistry | pH Range | FR-4 | G-10 | CXT |
|---|---|---|---|---|---|
| GaAs | Bromine-methanol (Br₂/MeOH) | 4–7 | Not suitable | Marginal | Recommended |
| GaAs | NaOCl alkaline oxidant | 9–11 | Marginal | Acceptable | Recommended |
| InP | HBr / Br₂ acidic | 5–7 | Not suitable | Marginal | Recommended |
| InP | NaOCl + citric acid | 7–9 | Marginal | Acceptable | Recommended |
| Sapphire | Diamond abrasive, acidic | 3–6 | Not suitable | Marginal | Recommended |
| Sapphire | Colloidal silica, final polish | 8–10 | Acceptable | Recommended | Recommended |
Side-by-Side Specification Comparison
| Parameter | GaAs | InP | Sapphire | Si (reference) |
|---|---|---|---|---|
| Carrier plate material | CXT / G-10 | CXT | CXT / G-10 | FR-4 / G-10 |
| Backing pad Shore A | 30–50 | 25–45 | 60–75 | 55–75 |
| Process pressure | 1–3 psi | 0.5–2 psi | 2–5 psi | 2–5 psi |
| Work-hole clearance | 0.15–0.25 mm | 0.15–0.20 mm | 0.25–0.40 mm | 0.25–0.50 mm |
| EER height | 40–100 µm | 30–80 µm | 60–150 µm | 50–150 µm |
| Waxless required? | Mandatory | Mandatory | Strongly preferred | Preferred |
| Key failure mode | Cleavage fracture | Cleavage fracture | Chemical compat. | TTV drift |
| Typical cycle life | 80–150 | 100–180 | 80–160 | 100–200 |
Handling & Loading Best Practices for Fragile Substrates
Template design sets the mechanical boundary conditions for wafer polishing, but in-process handling — how the wafer is loaded into the template, transported to the polisher, and unloaded after polishing — is equally important for fragile III-V substrates. The best-engineered template cannot prevent breakage from handling errors that apply stress concentrations exceeding the wafer’s fracture toughness threshold.
Loading Protocol for GaAs and InP
Wet the backing pad with DI water as for standard waxless loading, but apply additional care to the wafer placement step. Lower the wafer into the work hole vertically rather than sliding it laterally — lateral placement drags the wafer edge across the work-hole wall and is the most common source of edge chips in fragile substrate loading. Use vacuum tweezers rated for the wafer diameter; finger contact with GaAs or InP wafers during loading introduces point-contact stress that can initiate subsurface cracks that become visible only after polishing. Allow 5–10 seconds of gentle pressure after placement to ensure the capillary adhesion is fully established before the assembly is moved.
Release Protocol After Polishing
Release GaAs and InP wafers by allowing the backing pad to partially dry — do not use mechanical release (spatula at the edge) for III-V substrates, as the edge-lift force required is sufficient to initiate cleavage-plane fractures. If the pad is slow to dry, a brief application of low-pressure compressed nitrogen at the wafer edge can accelerate the drying without applying mechanical stress. Once the wafer releases freely, transfer immediately to the post-polish cleaning bath without intermediate dry storage, as GaAs and InP surfaces oxidize rapidly in air and benefit from continuous wet processing.
