Copper CMP (Cu-CMP): Process, Challenges, and Advanced Nodes
A complete technical guide to copper chemical mechanical planarization — covering Damascene integration, two-step Cu CMP architecture, dishing and erosion control, barrier chemistry, and advanced-node scaling challenges through 2 nm.
Why Copper Requires CMP — and Why It Cannot Be Etched
Copper became the dominant interconnect metal in logic chips starting in the late 1990s, replacing aluminum primarily because of its 40% lower electrical resistivity (1.68 µΩ·cm vs. 2.65 µΩ·cm for Al) and significantly better electromigration resistance at the current densities required by shrinking device geometries. Lower resistivity means lower RC delay in long interconnect lines — critical for the operating frequency of advanced processors and DRAM. Better electromigration resistance means longer device lifetime under the high current density stresses that narrow lines experience.
However, copper presents a fundamental processing challenge that aluminum does not: copper cannot be patterned by standard plasma dry etching. Unlike aluminum, which forms volatile chloride byproducts under halogen plasma, copper’s halide compounds are non-volatile at conventional etch temperatures, leaving non-volatile residues that contaminate the etch chamber and cannot be removed from the wafer surface. This is the fundamental reason CMP is not merely useful for copper integration — it is the only viable process for defining copper interconnect geometries in a production environment.
The Damascene Process Architecture
The solution to copper’s etch incompatibility is the Damascene process — named after the ancient Syrian metalworking technique of inlaying metal into carved grooves. Instead of depositing copper on a patterned surface and etching away the unwanted portions, the Damascene process reverses the sequence: the pattern is first etched into the inter-level dielectric (ILD), copper is then deposited to fill the trenches and vias by electrochemical plating (ECP), and CMP is used to remove the copper overburden above the ILD surface, leaving copper only in the recessed features.
Single Damascene vs. Dual Damascene
Single Damascene processes define either the via (vertical connection) or the trench (horizontal wiring) in separate lithography and etch steps, with a CMP step after each fill. Dual Damascene — the dominant approach in HVM for BEOL — defines both the via and the trench in a single patterned dielectric layer and fills both features simultaneously with a single copper ECP step, requiring only one Cu CMP step to complete both connections. Dual Damascene reduces the total number of process steps and CMP operations, lowering cycle time and cost per metal level.
The Barrier/Liner Stack
Before copper is electroplated, the etched trenches and vias are lined with a thin (3–10 nm) barrier/liner stack — typically TaN (diffusion barrier) + Ta (adhesion layer) or, at advanced nodes, TaN + Co or TaN + Ru. The barrier prevents copper from diffusing into the surrounding dielectric (copper is a deep-level trap in silicon and silicon dioxide, causing device failure at concentrations as low as 10¹² atoms/cm³). The barrier must be removed by CMP along with the copper overburden — this is the barrier CMP step.
Two-Step Cu CMP Sequence: Bulk + Barrier
Every production copper Damascene CMP process uses a two-step sequence, each step with a different slurry, pad, and process conditions optimized for its specific objective.
Step 1 — Bulk Copper Removal
Objective: remove the majority of the copper overburden (typically 400–1500 nm) as quickly as possible while maintaining good within-wafer uniformity. Uses a high-rate Cu slurry (H₂O₂ oxidizer, colloidal silica abrasive, pH 3–5, BTA corrosion inhibitor) on a hard IC1000-type pad at moderate pressure (1–3 psi). Endpoint: motor current or optical interferometry detects the approach to the barrier layer. A controlled amount of residual Cu (50–150 nm) is intentionally left to prevent barrier breakthrough during bulk polish.
Step 2 — Barrier/Liner Removal (Barrier CMP)
Objective: remove residual copper, the TaN/Ta barrier, and a controlled amount of the ILD surface to achieve a globally planar interconnect level with minimal dishing and erosion. Uses a barrier-compatible slurry (alumina or low-rate SiO₂ abrasive, controlled Cu:barrier:oxide selectivity, pH 6–9) on a softer pad at lower pressure (0.5–2 psi). Endpoint: optical detection of the transition from barrier to oxide signal confirms barrier clearance across the wafer.
Cu CMP Slurry Chemistry in Depth
The copper CMP slurry formulation is arguably the most sophisticated in the CMP consumables portfolio. It must simultaneously accelerate copper removal, inhibit copper corrosion on features not under polishing pressure, chelate dissolved copper ions to prevent re-deposition, and maintain particle stability across a wide range of temperature and shear conditions in the delivery system.
The Oxidation-Complexation-Abrasion Cycle
Copper CMP proceeds through a continuous three-stage cycle at the wafer-pad interface:
- Oxidation: H₂O₂ in the slurry oxidizes the metallic copper surface to CuO or Cu(OH)₂, forming a softer, more easily abraded passivation layer (3–10 nm thick).
- Complexation: Glycine, citric acid, or other chelating agents in the slurry form soluble Cu-chelate complexes with the oxidized copper layer, preventing the re-deposition of Cu²⁺ ions onto already-polished surfaces.
- Abrasion: Colloidal silica abrasive particles mechanically remove the softened CuO/Cu(OH)₂ layer, exposing fresh metallic copper for the next oxidation cycle.
BTA (benzotriazole) acts as the selectivity-controlling additive: it adsorbs onto copper areas of low surface topography (low contact pressure, recessed areas), forming a protective monolayer that slows the oxidation and removal of copper in recessed features — the primary mechanism for controlling dishing on wide copper lines.
Dishing, Erosion & Pattern-Dependent Effects
The two most yield-critical defect modes in Cu CMP are dishing und erosion. Both are pattern-dependent effects — they are not uniformly distributed across the wafer but are concentrated at specific feature geometries.
Dishing: Wide Line Degradation
Dishing is the formation of a concave depression in wide copper lines (typically >3 µm wide) after CMP, where the copper surface sits below the surrounding dielectric. It is caused by the polishing pad’s mechanical compliance: the pad locally deforms into the copper recess as the copper polishes faster than the surrounding material, creating an ever-deepening bowl shape. Dishing increases with copper line width (wider lines accumulate more dishing), polish time overrun, and slurry formulations with insufficient BTA loading. At advanced nodes, even 5–10 nm of dishing on 100 nm-wide sub-M2 lines is significant — it increases interconnect resistance, degrades RC performance, and causes lithographic reflectivity variations in overlying layers.
Erosion: Dense Pattern Thinning
Erosion occurs in regions of high metal pattern density (e.g., wide memory arrays, power grid regions with dense copper fills) where the effective polishing rate of the composite metal+dielectric surface is faster than in low-density areas. In high-density regions, the dielectric between metal lines is also removed along with the copper, reducing the total layer thickness. This creates a height difference (step height) between the array region and the surrounding field that affects the planarity available for the next lithographic layer and CMP step.
Barrier CMP: Ta/TaN and the Transition to Co and Ru
The barrier CMP step — step 2 of the two-step Cu CMP sequence — faces a more complex material removal challenge than the bulk copper step. At the barrier CMP stage, three materials are being simultaneously polished: residual copper, the TaN/Ta (or Co, Ru) barrier/liner, and the ILD oxide (TEOS or low-k). The slurry must remove all three while maintaining the correct selectivity ratios to prevent over-erosion of any one material.
At the 7 nm node and below, cobalt (Co) and ruthenium (Ru) have largely replaced TaN/Ta as the liner materials due to their lower bulk resistivity at ultra-thin film dimensions (relevant because the liner now constitutes a significant fraction of the total line cross-section at <10 nm half-pitch). Co and Ru have different electrochemical reactivity from Ta, requiring new slurry formulations with inhibitors specific to Co/Ru oxidation kinetics. Co in particular is susceptible to galvanic corrosion in the presence of copper and acidic oxidizing agents — a failure mode that did not exist with Ta-based barriers and required significant slurry chemistry innovation to resolve.
Endpoint Detection for Cu CMP
Copper CMP endpoint detection requires a more sophisticated approach than oxide CMP because the transition from copper to barrier metal represents a change in both optical reflectivity and surface friction — both signals are used simultaneously for maximum reliability.
- Optical endpoint (OEP): Broadband light reflected from the copper surface has high reflectivity (>40%) that drops sharply when the barrier layer (TaN, dark gray, very low reflectivity) is exposed. The OEP system monitors the integral reflected intensity and triggers at the step-change associated with barrier breakthrough. For dual Damascene structures, there may be two optical signals: via clearing followed by trench clearing, depending on the polish rate uniformity.
- Motor current (friction): Copper’s coefficient of friction against the polishing pad is lower than tantalum’s. As barrier breakthrough occurs, the drive current of the polishing platen motor increases measurably. The current signal is particularly reliable for detecting barrier clearance at die positions where the OEP signal may be weaker due to pattern density effects.
Advanced Node Scaling: Co and Ru Lines, Sub-10 nm Challenges
At the 3 nm and 2 nm nodes being ramped in 2026, the copper interconnect architecture itself is under pressure. At line widths below 8 nm, copper grain boundary scattering causes its resistivity to increase dramatically — its bulk resistivity advantage over tungsten and even aluminum disappears. This has driven the industry to evaluate cobalt and ruthenium as bulk conductor materials (not just liners) for the lower metal levels (M0–M2) where line widths are smallest.
Co and Ru bulk conductor CMP presents entirely new process challenges: these metals have lower ductility than copper and different passivation chemistry, requiring new slurry formulations, lower polishing pressures to prevent delamination at the metal-dielectric interface, and new endpoint detection calibrations. JEEZ is actively developing Co/Ru-compatible slurry solutions for next-generation BEOL architectures. For detailed discussion of all advanced node CMP challenges, see our article: CMP in Advanced Nodes: Challenges at 7 nm and Beyond.
Cu CMP Performance Comparison: By Node Generation
| Node | Min. Cu Line Width | Barrier Metal | Cu MRR Target | Dishing Spec | Key Challenge |
|---|---|---|---|---|---|
| 28 nm | ~40 nm | TaN/Ta | 400–800 nm/min | <15 nm | Within-wafer uniformity |
| 16/14 nm | ~25 nm | TaN/Ta | 300–600 nm/min | <10 nm | Low-k compatibility, dishing |
| 10/7 nm | ~15 nm | TaN/Co or TaN/Ru | 200–400 nm/min | <5 nm | Co/Ru inhibitor chemistry, EUV-grade clean |
| 5/3 nm | ~10 nm | Ru | 150–300 nm/min | <3 nm | GAA integration, ULK delamination |
| 2 nm (2026+) | <8 nm | Ru / Co (bulk) | 100–200 nm/min | <2 nm | Resistivity at thin film, EUV overlay |
Häufig gestellte Fragen
Two-step Cu CMP exists because the optimal process conditions for bulk copper removal (high pressure, high MRR, Cu-selective slurry) are incompatible with the requirements of the barrier removal step (low pressure, controlled Cu/barrier/oxide selectivity). Using a single step with a compromise recipe would result in either excessive dishing (if optimized for rate) or incomplete barrier removal (if optimized for dishing control). The two-step architecture assigns each objective to a purpose-optimized step, delivering better performance than any single-step compromise.
The Damascene process is a subtractive patterning technique where the dielectric insulator is patterned first (by lithography and plasma etch), copper is deposited to fill the etched features by electrochemical plating, and CMP removes the excess copper above the dielectric surface. It is used for copper interconnects because copper cannot be patterned by conventional plasma etching — copper halide etch byproducts are non-volatile and contaminate process equipment. The Damascene process sidesteps this limitation by never requiring copper etching at all; the copper is defined purely by the shape of the dielectric trench it fills.
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