Shallow Trench Isolation (STI) CMP: Process and Optimization
A complete technical guide to STI CMP — covering the role of STI in FEOL device isolation, CMP process sequence, high-selectivity ceria slurry, nitride stop-layer control, dishing prevention, and advanced node scaling.
The Role of Shallow Trench Isolation in Semiconductor Manufacturing
Shallow Trench Isolation (STI) is the dominant technology for electrically isolating adjacent transistors from one another on a silicon wafer. Without isolation, the electric field from one transistor would extend into neighboring devices, causing parasitic current leakage, latch-up, and device crosstalk that would make reliable circuit operation impossible. STI achieves this isolation by physically surrounding each active transistor area with deep trenches filled with silicon dioxide insulator, creating an impenetrable electrical barrier between devices.
STI replaced the earlier LOCOS (Local Oxidation of Silicon) isolation technique starting at the 250 nm node, driven by three advantages: STI creates a more planar surface (critical for CMP compatibility), consumes less lateral silicon real estate (enabling higher transistor packing density), and avoids the “bird’s beak” encroachment artifact of LOCOS that caused active area reduction and threshold voltage variability. Since its introduction, STI has scaled seamlessly from 250 nm to the 2 nm node in 2026, with process modifications at each generation to accommodate shrinking trench dimensions and new transistor architectures.
STI Process Flow and CMP Integration
The STI process is one of the earliest steps in the FEOL fabrication sequence, performed on a bare or lightly processed silicon wafer before any transistor gate structures are formed. Understanding the full process flow is essential for understanding the specific requirements it places on the CMP step.
Pad Oxide and Nitride Deposition
A thin pad oxide layer (5–10 nm thermal SiO₂) is grown on the silicon wafer surface, followed by deposition of a silicon nitride (Si₃N₄) layer by LPCVD (50–100 nm). This Si₃N₄/SiO₂ stack serves as the CMP polish stop layer — the CMP process must remove oxide down to this nitride surface without consuming it, so the nitride must have a dramatically lower removal rate than the oxide being polished.
Active Area Patterning and Trench Etch
Photolithography defines the active area pattern (the transistor body regions that must be protected) in the nitride layer. A reactive ion etch (RIE) step opens trenches in the silicon substrate, typically 200–400 nm deep and 50–200 nm wide at advanced nodes. The nitride acts as a hard mask, protecting the active areas from the etch.
Liner Oxidation and Oxide Fill
A brief thermal oxidation step grows a thin liner oxide (3–5 nm) on the trench sidewalls to passivate silicon damage from the etch and reduce interface state density. The trench is then filled with high-density plasma CVD (HDP-CVD) or sub-atmospheric TEOS oxide, which deposits conformally to fill the trench without voids. The deposited oxide is substantially thicker than the trench depth, leaving a significant oxide overburden (200–600 nm) above the nitride surface that must be removed by CMP.
STI CMP — Oxide Planarization to Nitride Stop
The CMP step removes the oxide overburden and achieves global planarity across the wafer, stopping precisely on the Si₃N₄ layer. This is the most critical and technically challenging step of the STI process. The polish must remove 200–600 nm of oxide selectively over the nitride, with uniformity sufficient to achieve a globally planar surface across an entire 300 mm wafer that may contain a mix of dense and sparse active area patterns.
Nitride Strip and Post-STI Clean
After CMP, the Si₃N₄ polish stop layer is selectively removed by wet phosphoric acid (H₃PO₄) etching, leaving the oxide-filled trenches elevated slightly above the silicon active areas — the classic “recessed oxide” STI profile. Post-CMP cleaning removes residual ceria particles and CMP byproducts before the next FEOL process step.
High-Selectivity Ceria Slurry for STI CMP
The CMP slurry is the critical enabler of successful STI CMP. STI CMP imposes the most stringent selectivity requirement of any CMP application — the slurry must remove SiO₂ at a rate 100–500× faster than it removes Si₃N₄. This requirement eliminates conventional colloidal silica-based oxide slurries, which achieve SiO₂:Si₃N₄ selectivity of only 4:1 to 10:1 — far insufficient to stop reliably on the nitride surface across a full 300 mm wafer with 200–600 nm of oxide to be removed.
Why Ceria Achieves High Selectivity
Cerium dioxide (CeO₂) abrasive achieves high oxide-to-nitride selectivity through a fundamentally different removal mechanism than silica abrasives. Ceria particles react directly with the SiO₂ surface through a chemical mechanism involving direct Ce–O–Si bond formation (the “tooth” mechanism, proposed by Cook in 1990). This chemical bond formation is highly specific to SiO₂ and does not occur readily with Si₃N₄, which has no reactive Si–O–Si backbone for ceria to attack. The result is that ceria removes SiO₂ at rates 5–10× higher than silica abrasive at the same concentration and pad conditions, while leaving Si₃N₄ nearly untouched.
Selectivity can be further enhanced by adding amino acid additives (typically L-proline, L-arginine, or similar) to the ceria slurry, which preferentially adsorb onto the Si₃N₄ surface and passivate it against ceria attack without significantly affecting SiO₂ removal rate. With optimized amino acid loading, SiO₂:Si₃N₄ selectivities exceeding 500:1 have been demonstrated in laboratory conditions, with 100–200:1 routinely achieved in production.
Endpoint Detection and Stop-Layer Control
Endpoint detection for STI CMP faces a unique challenge: the goal is to stop polishing precisely on the Si₃N₄ surface across the entire wafer — not to reach a particular film thickness target. This means the endpoint signal must indicate nitride exposure, not just film thickness change.
Motor Current Endpoint for STI
The difference in friction coefficient between SiO₂ and Si₃N₄ against the polishing pad creates a measurable change in drive motor current as the polishing surface transitions from oxide-dominant to nitride-dominant contact. The motor current signature for STI CMP typically shows a gradual increase (more of the nitride surface being exposed) followed by a plateau (full nitride exposure). The endpoint is set at the current plateau or at a defined percentage of the current signature transition.
Optical Interferometry for STI
Broadband reflectometry can also be used for STI endpoint, using the distinctive difference in optical reflectivity between TEOS oxide and Si₃N₄. As the oxide overburden is cleared and the nitride surface begins to dominate the reflected spectrum, the interferometric signal changes character — shifting from periodic oxide interference fringes to the characteristic Si₃N₄ reflectivity signature. The accuracy of optical endpoint for STI is somewhat lower than for metal CMP due to the complex pattern-dependent topography of the STI surface, but it provides a useful independent confirmation signal when used alongside motor current monitoring.
Active Area Dishing and Corner Rounding
In STI CMP, “dishing” takes a different form than in copper CMP: it refers to the over-polishing of the oxide within the isolation trench itself, causing the oxide surface to be recessed below the level of the surrounding silicon active area. This active area dishing affects transistor performance in two ways: it alters the effective height of the STI isolation relative to the gate electrode (affecting fringing field and threshold voltage), and it creates a non-planar surface at the active area-STI boundary that interferes with gate lithography and potentially causes poly-silicon residue at the trench corners.
Corner rounding — the gradual rounding of the sharp 90° corner at the top of the STI trench during polishing — is actually a partially desired effect in shallow trench isolation (sharp silicon corners cause electric field crowding and premature transistor breakdown), but excessive corner rounding reduces the effective channel width of the transistor. Both dishing and corner rounding are minimized by using high-selectivity ceria slurry (which stops quickly on nitride, limiting overpolish time) and by careful dummy active area placement to equalize local pattern density.
Pattern Density Effects and Erosion in STI CMP
STI CMP pattern density effects are among the most significant in all of semiconductor CMP, because the STI pattern is the first CMP step in the process flow and any planarity deficiency it introduces propagates and potentially amplifies through all subsequent steps. The fundamental issue is that regions of the die with dense active areas (high nitride density, low oxide fill fraction) polish at a different rate than regions with sparse active areas (low nitride density, high oxide fill fraction).
In dense regions, the remaining oxide load per unit area is lower, so the nitride stop is reached earlier — meaning these regions may be overpolished relative to the endpoint if polishing continues until sparse regions clear. This creates an array erosion profile where the dense-pattern area is at a slightly different height than the sparse-field area. Mitigations include: dummy active area fill (adding non-functional silicon active area tiles in sparse regions), reverse-tone dummy fill (adding non-functional oxide-only tiles in dense STI regions), and pattern-density-aware CMP simulation for recipe optimization.
Post-STI CMP Cleaning: Ceria Particle Removal
Post-STI CMP cleaning presents a specific challenge not encountered in other CMP applications: ceria (CeO₂) particles have a positive surface charge at neutral to slightly alkaline pH (zeta potential ~ +20 to +40 mV at pH 5–7), while the SiO₂ surface they must be removed from has a negative charge at the same pH. This electrostatic attraction between ceria particles and the oxide surface makes them significantly harder to remove than silica or alumina particles that have the same charge sign as the surface.
The solution is to clean at acidic pH (pH 3–5 using dilute citric acid, malic acid, or HCl), which reduces the positive zeta potential of the ceria particles and reduces the magnitude of the electrostatic attraction, allowing PVA brush scrubbing to dislodge them. Alternatively, a dilute EDTA chelating solution can complex the Ce³⁺/Ce⁴⁺ ions that mediate ceria-SiO₂ adhesion, achieving particle lift-off without pH reduction. For a complete post-CMP cleaning methodology, see our guide: Post-CMP Cleaning: Methods, Challenges, and Best Practices.
STI CMP at Advanced Nodes: FinFET and GAA Challenges
The transition from planar MOSFET transistors (32 nm and above) to three-dimensional FinFET architectures (20 nm and below) fundamentally changed the role and requirements of STI CMP. In a FinFET process, the STI CMP step does not simply fill and planarize isolation trenches — it also defines the height of the silicon fins that will form the transistor channel. The final STI oxide surface level, set by the CMP stop-on-nitride height, determines the fin height above the oxide — a dimension that directly controls the transistor’s drive current and subthreshold slope.
At the 3 nm and 2 nm nodes using Gate-All-Around (GAA) nanosheet transistors, STI CMP requirements evolve further. The nanosheet stacks that form the channel require precisely controlled STI fill at extremely fine pitch, and any CMP-induced planarity non-uniformity across the nanosheet stack will cause variation in the number of nanosheets exposed above the STI oxide — directly varying the effective channel width and hence the transistor’s electrical characteristics from die to die. Sub-1 nm STI height uniformity specifications are now required at GAA nodes, pushing ceria slurry formulation, endpoint detection precision, and within-wafer uniformity control to their current limits.
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Silicon nitride is used as the STI CMP stop layer because it has a significantly lower removal rate than silicon dioxide under ceria or silica-based CMP conditions, providing the high selectivity (100:1 or greater) needed to stop polishing reliably on the stop layer surface. Using silicon directly as the stop layer is impractical for two reasons: silicon is also removed by the alkaline CMP chemistry (albeit slowly), and the silicon surface is not the correct level at which to stop — polishing to the silicon surface would remove the thin pad oxide and begin consuming the active silicon region, increasing junction depth variability and potentially causing direct silicon damage. The nitride layer, deposited at the controlled thickness on the pad oxide, provides a defined, robust, and selectively-stoppable surface at exactly the right depth in the layer stack.
LOCOS (Local Oxidation of Silicon) was the dominant isolation technology from the 1970s through the 250 nm generation. In LOCOS, field oxide is grown thermally through nitride mask openings, but the thermal oxidation process causes lateral oxide encroachment under the nitride mask — the characteristic “bird’s beak” — that reduces the effective active device area and causes gradual threshold voltage variation near the active area edges. STI was adopted starting at the 250 nm node because it eliminates the bird’s beak by using a dry etch to define the trench (no lateral encroachment), achieves better planarity than LOCOS (compatible with CMP), and scales better to sub-100 nm dimensions where the bird’s beak would have consumed unacceptable active area.
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