CMP in 3D IC &Heterogeneous Integration: New Frontiers

The 3D Integration Revolution

The semiconductor industry is in the middle of a fundamental architectural transition. After decades of Moore’s Law scaling that made transistors progressively smaller on a single planar chip, the physical and economic limits of 2D scaling are driving the industry toward a third dimension. Three-dimensional integration — stacking multiple chips vertically with high-density interconnects between them — is now the primary strategy for delivering continued performance and bandwidth improvements in AI accelerators, high-performance computing, advanced memory, and mobile processors.

In 2026, 3D integration and advanced packaging are no longer niche or future technologies — they are mainstream production. TSMC’s CoWoS (Chip-on-Wafer-on-Substrate) and SoIC (System-on-Integrated-Chips) platforms are in volume production for NVIDIA’s AI accelerators and Apple’s processors. Intel’s Foveros 3D stacking is deployed in Core Ultra processors. Samsung’s X-Cube and SK Hynix’s High Bandwidth Memory (HBM) use 3D stacking with through-silicon vias. Every one of these platforms depends critically on CMP — and the CMP requirements of advanced packaging push well beyond what conventional front-end CMP demands.

This article complements the advanced-node CMP discussion in our article on CMP Challenges at 7nm, 5nm & Beyond. For the foundational overview of CMP technology, see the CMP Semiconductor Complete Guide.

Why CMP Is Critical in 3D IC

In conventional 2D chip fabrication, CMP creates the flat surfaces needed for photolithography. In 3D IC integration, CMP serves the same fundamental function but with requirements that are in some respects far more stringent — because the surfaces being prepared are the actual bonding interfaces between two or more chips. Any imperfection at these interfaces directly affects bond yield, interconnect resistance, and long-term reliability.

Hybrid Bonding CMP: The Most Demanding Application

Hybrid bonding is the direct copper-to-copper and dielectric-to-dielectric bonding technology that enables chiplet stacking with sub-micron pitch interconnects — providing bandwidth densities 100–1,000× higher than conventional flip-chip bump connections. The bonding process requires two wafers (or a die and a wafer) whose surfaces are so flat and smooth that they spontaneously bond at room temperature through van der Waals attraction and chemical bonding when brought into contact.

Achieving this requires CMP to deliver a surface that meets four simultaneous specifications — all more demanding than any production CMP application in the conventional fab:

Hybrid Bonding CMP Process Design

Meeting these specifications requires a purpose-designed CMP process that differs significantly from standard copper dual-damascene CMP. The key differences are:

• Ultra-low downforce: Polishing pressure must be below 1 psi — sometimes as low as 0.3–0.5 psi — to avoid mechanical deformation of the copper pad structure and dishing in pad arrays.
• Near-zero dishing slurry: Copper slurry formulated with carefully balanced BTA concentration and oxidiser levels to achieve near-zero copper recess while maintaining adequate removal rate. Many hybrid bonding CMP processes use a two-step sequence: a conventional copper CMP step to clear the bulk overburden, followed by a dedicated “planarization slurry” step specifically formulated for co-planarity optimisation.
• Ultra-soft buff pad: A final buff step using a very soft, compliant pad (Shore A 30–40) with a colloidal silica or surfactant-only slurry to reduce surface roughness to the <0.3 nm Ra target without re-introducing non-uniformity.
• Dedicated post-CMP clean: A super-clean sequence using dilute NH₄OH for particle removal, followed by dilute HCl for metallic contamination control, followed by a high-purity DI water rinse and IPA-assisted drying.

Through-Silicon Via (TSV) CMP

Through-silicon vias (TSVs) are vertical conductive pillars that electrically connect stacked dies in a 3D IC package. They are formed by etching deep vias (aspect ratios of 10:1 to 20:1) into the silicon, depositing an insulating liner and barrier, filling with copper by electroplating, and then using CMP to remove the overplated copper from the wafer frontside. After the chip is fabricated, the wafer is thinned from the backside until the TSV copper tips are revealed — a process that also involves a final CMP step to planarize the revealed TSV surface.

Frontside TSV CMP

After TSV copper electroplating, the wafer surface carries 5–20 µm of overplated copper — far thicker than typical BEOL dual-damascene overburden (0.5–1 µm). Removing this thick copper layer by CMP requires high removal rate (up to 1 µm/min) combined with excellent planarity control to avoid the “dimpling” effect — where the top of each TSV copper pillar is polished faster than the surrounding silicon, creating a recessed profile that can cause contact resistance issues. High-pressure, multi-step CMP with dedicated thick-film copper slurries is required.

Backside TSV Reveal CMP

After wafer thinning (by grinding) to expose the TSV backside, a CMP step is used to planarize the thinned silicon surface and reveal the copper TSV tips with a controlled protrusion height — typically 1–3 µm above the silicon surface. This protrusion is intentional: it allows subsequent backside metallisation to contact the TSV tip reliably. The reveal CMP must stop within ±50 nm of the target protrusion height across the entire wafer, requiring slurry with high silicon-to-copper selectivity (to preferentially remove silicon while leaving copper proud) and excellent endpoint detection capability.

Wafer Thinning & Backside CMP

Three-dimensional stacking requires dies to be thinned from their standard 750 µm wafer thickness to 50–100 µm (for standard 3D stacking) or 5–20 µm (for extreme thin-die stacking in HBM and similar applications). The thinning process uses a three-step sequence: rough grinding (to remove bulk silicon rapidly), fine grinding (to achieve the target thickness within ±5 µm), and CMP (to remove the grinding-induced sub-surface damage layer and achieve the surface roughness required for the next step).

Grinding Damage Removal

Diamond grinding leaves a damaged silicon sub-surface layer — an amorphous or heavily dislocated crystal zone extending 1–5 µm below the ground surface. This damage layer must be completely removed before the thinned wafer can be bonded or further processed, because it increases carrier recombination, reduces mechanical strength (making the die more susceptible to cracking), and introduces residual stress that can cause wafer bow. CMP removes the damage layer and leaves a crystallographically perfect, low-roughness silicon surface ready for backside contact or bonding.

CoWoS, SoIC & Chiplet CMP

TSMC’s CoWoS (Chip-on-Wafer-on-Substrate) and SoIC (System-on-Integrated-Chips) platforms represent the two primary 3D integration architectures in high-volume production as of May 2026. Both require multiple CMP steps — but with different specifications depending on the integration approach.

CoWoS Interposer CMP

CoWoS uses a silicon or silicon nitride interposer to connect multiple chiplets side-by-side with short, high-bandwidth interconnects. The interposer fabrication process requires a full set of front-end and back-end CMP steps — oxide ILD, copper dual-damascene, and TSV CMP — identical to those used in logic chip fabrication. CMP specifications for interposers are similar to but slightly more relaxed than leading-edge logic, as the interposer feature sizes (1–5 µm RDL pitch) are less aggressive than front-end device dimensions.

SoIC Face-to-Face Bonding CMP

TSMC’s SoIC technology bonds chiplets face-to-face using hybrid bonding — the most demanding CMP application described in the hybrid bonding section above. In SoIC, two chips with bond pads at their front-side surfaces are brought together and directly bonded copper-to-copper and dielectric-to-dielectric. The CMP surface preparation on both chips must simultaneously meet the <0.3 nm Ra, <2 nm step height, and sub-ppb metal contamination specifications described above.

Surface Specifications for Bonding: Comparison

Metrology Challenges in Advanced Packaging CMP

The sub-nanometre surface specifications of hybrid bonding CMP create metrology challenges that are as significant as the process challenges themselves. Many standard fab metrology tools cannot measure the required specifications with sufficient accuracy or throughput for production monitoring.

• AFM for roughness and step height: Atomic force microscopy is the reference method for measuring Ra and Cu-dielectric step height at sub-nm resolution, but its low throughput (one measurement point per minute) makes it impractical for production wafer-level monitoring. New fast-scan AFM systems with automated stage control are improving throughput to 5–10 points per minute.
• Optical scatterometry for step height: Advanced optical CD tools with modelling capability can measure Cu step height with ~0.5 nm sensitivity at production-compatible speeds (20–50 points per minute). Accuracy at the <2 nm level requires careful optical model calibration against AFM reference data.
• TXRF for surface metal: TXRF remains the standard for surface metal contamination measurement, but its sensitivity limit (~10⁹ atoms/cm² for Cu) is being pushed by the increasingly stringent hybrid bonding requirements. Next-generation TXRF systems with improved X-ray source brightness are targeting 10⁸ atoms/cm² sensitivity by 2027.
• Wafer-level bond void inspection: After bonding, void defects at the bonding interface are detected by scanning acoustic microscopy (SAM) or X-ray tomography. SAM sensitivity to sub-5 µm voids is required for advanced hybrid bonding quality control.

Market Outlook & JEEZ’s Role in Advanced Packaging CMP

The advanced packaging CMP market is at an inflection point in 2026. What was a niche, specialised application two years ago is now a high-volume production requirement at every major advanced packaging fab. TSMC’s CoWoS capacity expansion, Intel Foundry’s Foveros ramp, and the explosive growth of HBM for AI applications are driving rapid volume growth in advanced packaging CMP consumables.

The competitive dynamics of the advanced packaging CMP consumables market are distinct from the established logic and memory CMP segments. Hybrid bonding CMP is a new application where no incumbent supplier has a dominant position — creating an opportunity for technically capable suppliers like JEEZ to qualify alongside established leaders. The key differentiators in this segment are application engineering depth (ability to co-develop process recipes with packaging fabs), surface specification capability (ability to consistently meet Ra <0.3 nm and step height <2 nm requirements), and supply reliability. These are precisely the capabilities that JEEZ is building for the advanced packaging CMP market through 2026 and beyond.