STI CMP Slurry: Ceria Chemistry, SiO₂:Si₃N₄ Selectivity & Advanced Node Guide
Shallow trench isolation (STI) CMP is among the most technically demanding polishing steps in front-end-of-line semiconductor processing. The requirement to achieve SiO2:Si3N4 selectivity ratios of 50:1 to 200:1 while maintaining sub-nanometer uniformity across a 300 mm wafer distinguishes STI from all other oxide CMP applications. This article provides a complete technical guide to STI CMP slurry — ceria chemistry, selectivity mechanisms, PAA additives, process integration, and advanced-node challenges. For a broad introduction to oxide CMP slurry types, see our Oxide CMP Slurry: Complete Technical Guide.
What Is STI CMP and Why Is It Critical?
Shallow trench isolation (STI) is the transistor-level isolation architecture used in all CMOS devices manufactured at the 250 nm node and below. STI structures are formed by etching shallow trenches into the silicon substrate (typically 200–400 nm deep), growing a thin thermal oxide liner on the trench walls, and then depositing a TEOS-based oxide gap-fill to completely fill the trenches and cover the surface with an oxide overburden above the original silicon plane.
STI CMP removes this oxide overburden to reveal a planar surface that is flush with (or slightly above) the original silicon-nitride surface, while preserving the oxide fill inside the trench. The Si3N4 hard mask — deposited before trench etching to protect the active transistor areas — must be preserved intact after CMP, because it defines the boundaries between active and isolation regions. Even a few nanometers of excess nitride removal can displace the active/isolation boundary and degrade transistor performance.
The STI CMP step determines: (1) the planarity of the starting surface for gate patterning; (2) the height of the isolation oxide relative to the active silicon surface (critical for gate overlap and leakage control); and (3) the uniformity of the nitride mask remaining after CMP (critical for fin height in FinFET devices). Any process failure in STI CMP can propagate through every subsequent FEOL step, making it one of the most yield-sensitive steps in logic device fabrication.
The Selectivity Imperative
SiO2:Si3N4 selectivity is the defining performance metric for STI CMP slurry. It is defined as the ratio of the oxide removal rate to the nitride removal rate under the same process conditions:
Selectivity = MRR(SiO2) / MRR(Si3N4)
For mature nodes (180 nm to 45 nm), selectivity ratios of 30:1 to 50:1 are generally adequate — the nitride budget is large enough to absorb some loss. But as device scaling has progressed to 14 nm, 7 nm, 5 nm, and below, the total nitride budget available after STI CMP has shrunk dramatically:
At the 45 nm node, the nitride budget after STI allows ~5 nm loss. At the 7 nm FinFET node, it allows ~2 nm. At the 3 nm GAA node, allowable nitride loss is 1 nm or less — requiring SiO2:Si3N4 selectivity consistently above 150:1.
Colloidal silica slurry achieves selectivity of only 5:1 to 15:1 — completely insufficient for any STI application. Only ceria (CeO2) abrasives, through their unique surface chemistry, can deliver the selectivity ratios required for modern STI CMP. This is why ceria is the only commercially viable abrasive for STI slurry.
Ceria Chemistry & the Ce–O–Si Mechanism
Cerium oxide (CeO2, ceria) polishes SiO2 through a mechanism fundamentally different from the mechanical abrasion that dominates colloidal silica polishing. Ceria particles interact chemically with the SiO2 surface via a Ce–O–Si surface bonding mechanism:
- Cerium ions at the ceria particle surface (particularly Ce3+ species) form temporary Ce–O–Si bridging bonds with SiO2 surface hydroxyls (Si–OH groups)
- The Si–O–Ce bond is substantially stronger than the Si–O–Si bond in the bulk SiO2, enabling mechanical detachment of SiO2 surface units at lower applied pressures than silica abrasive requires
- The detached SiO2 unit (carrying a Ce ion) is released into solution, where hydrolysis breaks the Ce–O–Si bond and regenerates the ceria surface for further bonding
This chemical tooth-gear mechanism gives ceria its dramatically higher per-particle oxide removal efficiency compared to silica. At equal weight concentrations, ceria removes SiO2 approximately 3–5× faster than silica. This is why STI slurries use only 0.5–2 wt% ceria versus 5–15 wt% silica for ILD: the higher removal efficiency of ceria allows adequate MRR at much lower abrasive concentration.
Critically, the Ce–O–Si mechanism operates selectively on SiO2: Si3N4 surfaces do not present the accessible Si–OH groups required for Ce–O–Si bond formation, so nitride surfaces experience primarily mechanical abrasion (much weaker than the chemical mechanism) from the low-concentration ceria particles. The intrinsic SiO2:Si3N4 selectivity of ceria without additives is approximately 10:1 to 30:1 — enhanced significantly by the PAA additives described in the next section.
The Ce3+/Ce4+ ratio on the ceria particle surface is a critical quality parameter: Ce3+ sites are believed to be the primary active centers for Ce–O–Si bond formation. CMP-grade ceria suppliers manage calcination temperature, atmosphere, and surface treatment to optimize this ratio, and it is a key differentiator between high-performance and commodity ceria slurry products.
PAA Additives & Selectivity Enhancement
Anionic polymer additives — most commonly polyacrylic acid (PAA) — are added to ceria STI slurries to dramatically increase SiO2:Si3N4 selectivity beyond the intrinsic ceria level. PAA at molecular weights of 1,000–100,000 g/mol functions through two simultaneous mechanisms:
Ceria Particle Stabilization
At STI slurry pH (5–8), ceria particles are positively charged (isoelectric point of CeO2 ~pH 9). PAA (anionic at pH > ~4.5) adsorbs onto the ceria particle surface through electrostatic attraction, providing a steric and electrostatic stabilization layer that prevents ceria particle aggregation. This stabilization function is critical for defect control: aggregated ceria clusters above ~0.5 µm in diameter are the primary source of micro-scratches in STI CMP.
Si3N4 Surface Passivation
PAA also adsorbs onto Si3N4 surfaces, creating a polymer passivation layer that physically blocks ceria abrasive contact with the nitride. This passivation layer is what pushes selectivity from the intrinsic ceria level (~20:1) to the 50:1–200:1 range required for advanced STI.
The PAA concentration is one of the most process-sensitive parameters in STI slurry formulation. A 20% increase in PAA concentration can raise selectivity from 80:1 to 150:1, but simultaneously reduce oxide MRR by 15–25% due to passivation of SiO2 surfaces as well. The formulator must carefully calibrate PAA concentration to meet both the selectivity target (set by the nitride budget) and the throughput requirement (set by the oxide removal rate target). For a comparison of how abrasive choice affects selectivity, see: Colloidal Silica vs. Ceria Abrasive in Oxide CMP: A Practical Selection Guide.
STI CMP Process Flow
The STI CMP process flow on a 300 mm production tool typically consists of two distinct polishing steps designed to balance bulk removal speed against final selectivity and defect performance:
Step 1: Bulk Oxide Removal
The first step uses the STI slurry at standard conditions (1–3 psi, 80–110 RPM) to remove the bulk of the oxide overburden above the nitride level. This step can also be performed with a higher-MRR ILD colloidal silica slurry if the overburden is large (>500 Å above nitride plane) and the tool supports rapid slurry changeover. Motor current sensors on the polishing motor begin tracking the friction signature of the wafer surface to detect approach of the nitride layer.
Step 2: Selectivity-Controlled Touch-Up
As the polishing surface approaches the nitride plane (detected by motor current trend), the process transitions to a lower-pressure, higher-selectivity step. This step exploits the maximum selectivity of the ceria/PAA system to remove the final oxide overburden while minimizing nitride loss. Optical endpoint detection monitors the nitride surface signature to confirm CMP completion. This two-step approach allows the bulk step to run at higher throughput while the selectivity step controls final quality metrics.
FinFET & GAA Advanced Node Requirements
The transition from planar transistors to FinFET and Gate-All-Around (GAA) architectures has progressively tightened STI CMP requirements in ways that demand continuous innovation in slurry formulation.
FinFET STI: Fin Height Uniformity
In FinFET devices (Intel 22 nm through 5 nm), silicon fins are formed within the STI trench network. The final fin height after STI CMP is determined by the difference between the polished nitride surface height and the silicon floor of the STI trench — a quantity that is sensitive to both nitride removal uniformity and oxide dishing inside narrow fin-to-fin isolation gaps. At 7 nm FinFET, fin height uniformity must be held within ±0.5 nm across the wafer (a WIWNU requirement of <0.5 nm 1σ), requiring STI slurry selectivity consistently above 100:1 combined with WIWNU <1.5%.
GAA Nanosheet: Sub-1 nm Nitride Budget
At sub-3 nm GAA nodes in production in 2025–2026, stacked nanosheet transistors introduce STI-like isolation steps with nitride budgets that approach the measurement uncertainty of standard metrology tools. Slurry SiO2:Si3N4 selectivity above 150:1 is required, and endpoint precision at the angstrom level (optical interferometry with sub-5 Å 3σ precision) is necessary. For a full analysis of STI and oxide CMP challenges at these nodes, see: Oxide CMP Slurry for Advanced Nodes: FinFET, 3D NAND & GAA Integration.
Dishing, Erosion & Defect Management
Dishing: In STI CMP, oxide dishing occurs when the polishing pad conforms to the wide isolation trench geometry and continues polishing the oxide fill below the surrounding nitride level. Dishing is most severe in wide features (>1 µm isolation width) and is controlled by using higher-selectivity (and therefore softer, more selective) polishing conditions for the final touch-up step. Harder pads reduce dishing by resisting conformance to the trench, but must be balanced against uniformity requirements.
Erosion: STI erosion refers to the loss of Si3N4 hard mask thickness in dense active-area arrays, caused by pattern-density-dependent polishing rate variation. Dense arrays present more ceria abrasive contact events per unit area than sparse features, increasing nitride removal rate locally despite high bulk selectivity. Erosion is managed through dummy active-area insertion in design-rule-sparse regions and through slurry selectivity optimization.
Ceria residue: Ceria particles that form Ce–O–Si bonds with the polished SiO2 surface can persist through standard rinse steps and create particle contamination events if not removed by dedicated post-CMP cleaning. See our guide on Post-CMP Cleaning for Oxide Slurry Processes for ceria residue removal protocols. For a complete analysis of STI CMP defect types and detection, see: Oxide CMP Slurry Defects: Root Causes, Detection Methods & Yield Impact.
Frequently Asked Questions: STI CMP Slurry
Why must STI CMP use ceria slurry rather than colloidal silica?
STI CMP requires SiO2:Si3N4 selectivity of 50:1 to 200:1 to stop precisely on the Si3N4 hard mask while removing oxide overburden. Colloidal silica achieves only 5:1 to 15:1 selectivity — using it for STI would result in excessive nitride removal and transistor defects. Ceria’s Ce–O–Si chemical bonding mechanism selectively accelerates oxide removal while leaving nitride largely inert, enabling the high selectivity STI demands.
What is the role of polyacrylic acid (PAA) in STI ceria slurry?
PAA serves two functions: it stabilizes ceria particles by adsorbing onto their positively-charged surface (preventing aggregation and micro-scratch defects), and it passivates Si3N4 surfaces by forming a polymer blocking layer that reduces ceria contact with nitride. Together these effects increase SiO2:Si3N4 selectivity from the intrinsic ceria level of ~20:1 to 50:1–200:1. PAA concentration must be precisely controlled — a 20% change can shift selectivity by 2×.
What is STI dishing and how is it controlled?
STI dishing is the concave profile that develops in oxide-filled isolation trenches when the polishing pad conforms to the trench geometry and continues removing oxide below the surrounding nitride level. It is most severe in wide isolation features (>1 µm). Control strategies include using harder polishing pads for reduced pad conformance, transitioning to a higher-selectivity low-pressure final step, and optimizing PAA concentration to reduce the mechanical removal contribution relative to chemical selectivity.
What SiO₂:Si₃N₄ selectivity is required at the 5 nm FinFET node?
At 5 nm FinFET, the total allowable nitride loss after STI CMP is approximately 2 nm, with fin height uniformity required within ±0.5 nm. These requirements translate to a need for SiO2:Si3N4 selectivity consistently above 100:1, combined with WIWNU below 1.5% (1σ). Achieving this requires advanced dual-polymer additive ceria formulations with point-of-use dilution protocols for in-situ selectivity fine-tuning.
What is STI erosion and how is it different from dishing?
STI erosion is the non-uniform thinning of the Si3N4 hard mask in dense active-area arrays due to pattern-density-dependent polishing rate variation — the dense array presents more abrasive contact events than sparse regions, increasing local nitride removal despite high bulk selectivity. Dishing occurs within individual wide isolation features. Erosion occurs across groups of closely-spaced active areas. Both can occur simultaneously and are managed through design-level dummy pattern insertion and process-level selectivity optimization.
