Tungsten CMP Slurry for Advanced Nodes: Logic, 3D NAND, and DRAM Requirements
The performance requirements for tungsten CMP slurry differ dramatically across the three major semiconductor device families — logic, 3D NAND flash, and DRAM — not because of fundamentally different chemistry, but because the physical structures being planarized, the feature geometries involved, and the electrical consequences of dimensional variation at each application diverge widely. A slurry qualified for bulk tungsten contact removal in a sub-3 nm logic flow may be entirely unsuitable for 3D NAND staircase CMP, and a formulation optimized for DRAM buried wordline recess control may not deliver the planarization efficiency needed for high-layer-count NAND wordline polishing.
This guide provides a systematic breakdown of tungsten CMP slurry requirements for each major device family and application type — what makes each one technically distinct, what specifications matter most, and how to select and qualify the right slurry for each use case. It also covers the long-term question of where tungsten fits in semiconductor roadmaps as cobalt, ruthenium, and molybdenum emerge as candidates at the most advanced nodes.
1. Why Advanced Nodes Demand More From Tungsten CMP Slurry
Technology scaling in semiconductor manufacturing is not merely a process of making features smaller — it is a process of tightening every tolerance simultaneously while maintaining or improving yield. For tungsten CMP, this means that specifications that were achievable with standard slurry formulations at 28 nm are inadequate at 5 nm, and specifications that are manageable at 5 nm will be insufficient at 2 nm and below.
Three interrelated trends drive this tightening:
- Feature geometry scaling: Smaller features have proportionally less tolerance for any dimensional deviation. A 10 Å dishing depth represents a small fraction of a 200 nm contact diameter but is a structurally significant fraction of a 15 nm contact at sub-5 nm nodes.
- Electrical sensitivity: At advanced nodes, every nanometer of dimensional variation translates to measurable variation in resistance, capacitance, threshold voltage, or leakage — electrical parameters that directly affect device performance, power consumption, and reliability.
- Stack complexity: More process layers, more CMP steps, and tighter cumulative tolerance budgets mean that each individual CMP step must consume a smaller fraction of the total dimensional budget than it would at simpler nodes.
2. Logic: MOL Contact CMP at Sub-28nm
Middle-of-line (MOL) contact CMP is the tungsten polishing step at the heart of logic chip fabrication. It planarizes the tungsten-filled contact vias that connect transistor terminals (source, drain, and gate) to the first metal interconnect layer, and it is executed at some point in every logic chip fabrication flow from 28 nm planar CMOS to sub-2 nm gate-all-around (GAA) architectures.
Contact Geometry and Its CMP Implications
Contact via diameter shrinks with each technology node, from approximately 50 nm at 28 nm planar to below 15 nm at 3 nm FinFET and below 10 nm at 2 nm GAA. Aspect ratios remain at 8:1 to 12:1, driven by the requirement to fill a feature that spans the vertical distance from the transistor surface to the first metal level. These geometry constraints create two specific CMP challenges that intensify with scaling:
Contact recess (dishing) tolerance: At sub-5 nm logic nodes, the acceptable contact recess (tungsten surface below the ILD level) is below 50 Å. Contact electrical resistance scales approximately with (1 + dishing depth / contact diameter) — at very small contact diameters, even modest dishing produces measurable resistance increase. This requires minimizing Step 1 overpolish time and transitioning to Step 2 as early as endpoint detection allows.
Within-wafer non-uniformity: WIWNU below 2% (1σ) is required to ensure that the minimum overpolish needed to clear the slowest-polishing region of the 300 mm wafer does not produce excessive dishing at the fastest-polishing region. Achieving this requires slurry with inherently high planarization efficiency and excellent lot-to-lot consistency.
Slurry Requirements for Logic MOL Contact CMP
- Abrasive: Colloidal SiO2 with narrow PSD and large-particle tail <100 particles/mL at >1 μm. Post-CMP scratch counts at leading logic fabs are specified in single digits per cm2.
- Step 1 selectivity: W:Oxide >50:1 to protect ILD during bulk removal. Higher selectivity reduces dielectric loss but requires tight overpolish management to control dishing.
- Step 2 (buff): Non-selective formulation (W:Oxide 1:1–3:1) with low oxide MRR to limit array erosion during the brief buff step needed for Ti/TiN liner clearing and surface improvement.
- Metallic purity: Fe surface contamination below 1010 atoms/cm2 after cleaning. Specify ICP-MS data on incoming slurry lots with Na, K, Fe, Ca all at low single-digit ppb levels.
- Stability: Lot-to-lot MRR variation <5% to maintain tight process control without frequent recalibration of polish time.
Related Guide — Process Selection
Highly Selective vs. Low Selective Tungsten CMP Slurry: Which One Does Your Process Need?
3. Logic: Replacement Metal Gate (RMG) CMP
Replacement metal gate (RMG) is the process architecture used for gate electrode formation at the 28 nm node and below. A sacrificial polysilicon gate is deposited, patterned, and used as a placeholder during source/drain formation and thermal annealing steps. It is then selectively removed, the gate trench is lined with a high-k dielectric and a work function metal layer, and the remaining volume is filled with tungsten (or, at the most advanced nodes, an alternative low-resistivity metal such as ruthenium or molybdenum). CMP then planarizes the metal fill to the ILD level, defining the gate height.
Gate Height Uniformity and Vth Spread
The gate height after RMG CMP directly determines the effective gate length and the overlap between the gate electrode and the underlying high-k dielectric, which in turn determines the transistor’s threshold voltage (Vth). Non-uniformity in gate height across a chip translates into Vth spread among nominally identical transistors, which manifests as performance variation, increased standby power (from leaky cells), and test bin loss at functional testing. The tighter the Vth specification of the device (as in SRAM cells, where Vth variation directly affects the read/write stability margin), the more stringent the CMP height uniformity requirement.
At sub-5 nm logic nodes, gate height non-uniformity targets are in the 1 nm range or below — a demanding CMP specification that requires not just good slurry performance but excellent pad conditioning, endpoint detection, and tool-to-tool matching across a multi-tool fleet.
Slurry Considerations for RMG CMP
RMG CMP uses similar slurry requirements to MOL contact CMP — high selectivity for clearing, colloidal silica abrasive, tight metallic purity — with two specific additional considerations. First, the gate dielectric materials (HfO2-based high-k films) are hard and brittle, making them particularly susceptible to microscratch damage; abrasive quality control is if anything more critical at the RMG step than at the contact step. Second, gate metal residue (tungsten or work function metal) left on the ILD surface after CMP causes device-to-device short circuits at the most advanced nodes; the Step 2 buff must achieve complete residue clearing at very low residue contamination levels.
4. 3D NAND Architecture and CMP Challenge Overview
3D NAND flash memory replaced planar (2D) NAND by stacking memory cells vertically in layers rather than scaling feature size horizontally. This architectural change relaxed the lithographic feature size requirements (each individual cell is relatively large compared to planar NAND at equivalent bit density) while introducing an entirely new set of manufacturing challenges associated with building and planarizing tall, complex thin-film stacks.
In a 3D NAND gate stack, alternating layers of silicon oxide (SiO2) and silicon nitride (Si3N4) are deposited in pairs, typically 30 nm each per pair, stacked to total heights of 3 μm to 8 μm depending on layer count. The nitride layers are later replaced with tungsten in a process called the “gate replacement” or “replacement gate” scheme — the nitride is selectively etched and tungsten is deposited by ALD/CVD to fill the horizontal gate trenches. The top surface of the completed tungsten-filled stack then requires CMP to clear the excess tungsten and achieve a flat starting surface for subsequent process steps.
5. 3D NAND Wordline CMP: Slurry Requirements
Tungsten wordline CMP in 3D NAND must achieve uniform tungsten removal across two radically different surface regions on the same wafer: the dense memory array region (where tungsten-filled wordlines cover the majority of the surface area) and the staircase peripheral region (where successive oxide/tungsten layers are exposed at different heights to form a stepped structure for wordline contact landing pads). The pattern density difference between these regions can be extreme — from >80% tungsten fill in the array to <10% in parts of the staircase — creating a severe planarization challenge.
Stack Stress and Downforce Management
The most critical constraint unique to 3D NAND tungsten CMP is the mechanical fragility of the multi-layer stack. The alternating oxide/tungsten layer structure has inherent stress non-uniformity across the layer interfaces, and the tall stack height makes it susceptible to delamination at these interfaces if the applied CMP downforce exceeds a critical threshold. This threshold is lower than the downforce typically used for logic contact CMP, typically in the range of 1 – 2.5 psi for 3D NAND applications versus 2 – 5 psi for logic.
Operating at lower downforce would normally reduce MRR, which would extend polish times and reduce throughput. The solution employed by 3D NAND-specific slurry formulations is to compensate for reduced mechanical input by enhancing the chemical contribution to MRR — higher oxidizer activity, optimized catalyst loading, and in some formulations, additives that improve the chemical dissolution rate of WO3 reaction products to minimize the passivation effect. The net result is a formulation that achieves acceptable MRR at lower downforce, protecting the stack while maintaining process economics.
Long Polish Time Stability
3D NAND wordline CMP involves significantly longer polish times per wafer than logic contact CMP, because the total tungsten overburden (the material deposited above the top wordline level) can be several hundred nanometers thick and the polish must be performed at moderate downforce and MRR. Slurry stability over these extended polish times — consistent pH, stable H2O2 concentration, no abrasive agglomeration — is therefore more critical for 3D NAND than for logic applications where polish times are shorter. Two-component slurry mixing ratios must be verified to remain accurate over the full polish duration, and slurry delivery systems should be designed to minimize the time between mixing and dispensing.
6. 3D NAND Staircase CMP
The staircase structure in 3D NAND flash is the engineering solution for making electrical contact to each individual wordline level in a multi-hundred-layer stack. Each layer is exposed by a mask-etch process that progressively trims the oxide/tungsten stack to create a stepped “staircase” profile where each step corresponds to one wordline level, with each step’s exposed tungsten surface serving as the landing pad for a vertical via that connects the wordline to the peripheral circuitry.
Staircase CMP must planarize this inherently non-planar stepped structure — a surface with hundreds of discrete height levels — to a flat reference level from which subsequent via lithography can be performed. This is geometrically a different challenge from wordline CMP: instead of uniformly removing a blanket tungsten overburden, staircase CMP must preferentially remove the material at the high spots (the tops of the tallest steps) while leaving the lower steps intact, until the entire stepped structure reaches a common height within the lithographic depth of focus budget.
The key slurry parameter for staircase CMP is planarization efficiency (PE) — the ability to remove material faster from high topographic features than from low ones. High PE is achieved through pad and process parameter selection as much as slurry formulation, but slurry properties (abrasive particle size distribution, hardness, and concentration) contribute significantly. For staircase applications, a slurry with moderate selectivity (to allow both tungsten and oxide removal across the varied surface) and high planarization efficiency is the standard formulation target.
7. DRAM: Buried Wordline CMP
Dynamic random-access memory (DRAM) uses a buried wordline (bWL) architecture in which the transistor gate electrode is recessed below the active silicon surface in a shallow trench, rather than sitting on top of it as in a planar or FinFET logic transistor. After tungsten fills the trench by CVD, a CMP step removes the tungsten overburden and simultaneously recesses the tungsten within the trench to a precisely controlled depth below the silicon surface. This recess depth determines the gate-to-silicon overlap, which directly controls the transistor’s threshold voltage, the leakage current from gate to channel, and ultimately the retention time of the DRAM cell — the time interval between successive refresh cycles that determines the device’s power consumption and refresh rate specification.
The ±5 Å Recess Control Challenge
The recess depth specification at advanced DRAM nodes (sub-15 nm half pitch) is typically in the range of 10 – 30 nm below the active silicon surface, with a tolerance of ±5 Å across the 300 mm wafer. This is one of the tightest dimensional tolerances in production CMP, anywhere in the semiconductor manufacturing process. To put it in context: 5 Å is approximately 2 atomic diameters of silicon — a tolerance that requires CMP process control approaching the fundamental atomistic limit of the planarization mechanism.
Achieving this tolerance requires:
- High Step 1 selectivity: A highly selective slurry (W:Oxide >50:1) is used to clear the tungsten overburden and recess the bWL tungsten to approximately the target depth. The high selectivity limits unintended removal of the surrounding silicon oxide and silicon nitride materials adjacent to the trench.
- Precise endpoint detection: Eddy current endpoint monitoring at the polishing tool must detect the W film thickness at the target removal depth with sub-Å precision. In practice, this requires frequent calibration of the eddy current system against reference wafers measured by XRR or TEM.
- Minimal or no Step 2 buff: Unlike logic CMP, a substantial Step 2 buff step cannot be used in DRAM bWL CMP because even a few seconds of non-selective polishing at typical buff MRR rates would remove additional tungsten beyond the ±5 Å budget. If a buff step is used at all, it is extremely brief and tightly timed.
⚠ DRAM bWL: The Tightest CMP Tolerance in Production
The ±5 Å buried wordline recess control requirement at advanced DRAM nodes is among the most demanding dimensional tolerances in production semiconductor CMP — approaching the atomic scale. Slurry lot-to-lot MRR consistency, endpoint detection precision, and point-of-use mixing ratio accuracy are all critical enablers of this level of process control.
8. DRAM: Storage Node Contact CMP
The storage node contact (SNC) in DRAM connects the bitline to the lower electrode of the storage capacitor, completing the vertical signal path in each memory cell. The SNC is a high-aspect-ratio via (aspect ratios of 10:1 or greater in advanced DRAM) filled with tungsten, and its CMP step planarizes the tungsten surface to the surrounding ILD level in preparation for capacitor bottom electrode deposition.
Unlike bWL CMP, SNC CMP is primarily a surface quality and metallic contamination control step rather than a dimensional control step. The dimensional tolerance for SNC height is more relaxed than for bWL recess, but the contamination requirements are exceptionally stringent: the storage capacitor dielectric that is deposited directly on the tungsten SNC surface is extremely sensitive to metallic contamination. Iron, sodium, potassium, and other metallic contaminants at the interface between the SNC tungsten and the capacitor dielectric can increase the leakage current through the dielectric, reducing the cell’s charge retention time. In DRAM specifications, this manifests as reduced refresh interval or increased cell failure rate in retention testing.
For SNC CMP applications, slurry metallic purity specifications are particularly strict:
- Fe at the tungsten surface after CMP and cleaning: typically <5 × 109 atoms/cm2
- Na, K, Ca: similarly in the 109 – 1010 atoms/cm2 range
- Slurry bulk Fe content (beyond the catalytic Fe(NO3)3): <5 ppb total Fe by ICP-MS
Qualification of a slurry for DRAM SNC applications therefore requires VPD-ICPMS surface metallic contamination data on actual test wafers polished with the candidate slurry, cleaned with the process clean sequence, and measured for metallic contamination at the tungsten surface — not just slurry bulk purity data from the CoA.
9. Cross-Device Requirements Comparison
| Anmeldung | W Feature Size | Dishing / Recess Target | Step 1 Selectivity | Step 2 Needed? | Key Slurry Risk |
|---|---|---|---|---|---|
| Logic MOL Contact (sub-5nm) | <15 nm dia. | <50 Å recess | >50:1 | Yes (brief buff) | Microscratch at low dia.; Fe contamination |
| Logic MOL Contact (28nm+) | 40 – 80 nm dia. | <300 Å recess | Yes (standard buff) | Array erosion if Step 2 too long | |
| Logic RMG Gate | <20 nm gate width | ±1 nm gate height | >50:1 | Yes (residue clearing) | Gate metal residue; high-k scratch damage |
| 3D NAND Wordline | ~10 – 20 nm WL pitch | Planarity ±50 nm | 10:1 – 25:1 | Depends on process | Stack delamination; array/staircase non-uniformity |
| 3D NAND Staircase | Staircase step widths μm – mm range | PE-limited planarization | Moderate; varies | Single-step often used | Pattern density variation; low PE causes non-planarity |
| DRAM Buried WL | 5 – 10 nm trench width | ±5 Å recess depth | >50:1 | None or minimal | Recess overrun; endpoint detection accuracy |
| DRAM Storage Node Contact | <20 nm via dia. | Relaxed vs. bWL | 25:1 – 50:1 | Yes (short buff) | Fe/Na/K contamination; capacitor leakage |
10. Future Nodes: Tungsten’s Evolving Role in Advanced Semiconductor Manufacturing
The long-term role of tungsten in semiconductor manufacturing is evolving as device scaling pushes into territory where tungsten’s electrical resistivity — acceptable at larger feature dimensions — becomes a performance constraint. As tungsten contact and via diameters shrink below 10 nm, the bulk resistivity advantage of tungsten over copper or cobalt is significantly eroded by surface scattering effects, which cause resistivity to increase sharply as feature dimensions approach the material’s electron mean free path.
Cobalt at Local Interconnect
Cobalt (Co) has been qualified and is in production at the local interconnect (M0 and M1) levels in some leading-edge logic flows, replacing tungsten at these levels due to better gap-filling capability and lower resistivity in small geometries. Cobalt CMP requires different slurry chemistry than tungsten CMP — cobalt is less noble than tungsten and more susceptible to chemical attack, requiring inhibitor-containing formulations to prevent galvanic corrosion — but some CMP tool and pad infrastructure carries over between the two applications.
Ruthenium and Molybdenum as Gate Fill Alternatives
Ruthenium (Ru) and molybdenum (Mo) are candidates to replace tungsten as the primary gate fill metal at the 2 nm and sub-2 nm nodes. Ruthenium offers lower resistivity in small geometries and better conformal deposition characteristics for very narrow gate trenches; molybdenum has lower resistivity than tungsten and has been demonstrated in research gate fill processes. Both require CMP processes with distinct chemistry from tungsten CMP, as neither forms the same H2O2-based oxide chemistry as tungsten.
Tungsten’s Sustained Role Through 2030+
Despite these emerging alternative metals at the leading edge, tungsten will remain the dominant contact and via fill metal across the majority of wafers in production through the end of this decade and well into the 2030s. The installed base of CVD tungsten equipment at fabs globally, the established tungsten CMP consumables and process ecosystem, and the cost economics of tungsten-based integration versus emerging alternatives ensure that volume production at nodes from 28 nm to sub-7 nm will continue to use tungsten CMP processes for their contact and via formation steps. The CMP slurry market impact of any transition at the leading edge (sub-2 nm) will be modest for at least the next five to seven years, given the lead time required to scale up alternative metal processes to high-volume production.
Related Guide — Supplier Selection
Tungsten CMP Slurry Suppliers Compared: Entegris, DuPont, Merck EMD, and When to Consider Alternatives
Summary
Tungsten CMP requirements differ fundamentally across logic, 3D NAND, and DRAM applications — in the feature geometry being planarized, the dimensional tolerance that determines device electrical performance, the selectivity required at each process step, and the defect sensitivities that matter most. Logic MOL contact CMP demands tight dishing control and ultra-low defectivity at sub-50 Å recess tolerances. 3D NAND requires low-downforce polishing of tall stacks with challenging pattern density variation. DRAM buried wordline CMP operates with the tightest recess depth tolerance in production CMP at ±5 Å. Selecting the right slurry formulation requires matching these application-specific requirements to formulation properties — selectivity, abrasive type, PSD, and chemical stability — rather than treating tungsten CMP as a single application category.
JEEZ Tungsten CMP Slurry Solutions for Your Application
JEEZ offers application-matched tungsten CMP slurry formulations for logic contact, 3D NAND wordline, and DRAM applications. Contact us to discuss your specific node, device type, and process requirements — sample qualification packages are available for all application types.
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