{"id":1643,"date":"2026-03-13T09:16:05","date_gmt":"2026-03-13T01:16:05","guid":{"rendered":"https:\/\/jeez-semicon.com\/?p=1643"},"modified":"2026-03-13T09:53:14","modified_gmt":"2026-03-13T01:53:14","slug":"how-to-specify-a-polishing-template-6-parameters-engineers-must-define","status":"publish","type":"post","link":"https:\/\/jeez-semicon.com\/de\/blog\/how-to-specify-a-polishing-template-6-parameters-engineers-must-define\/","title":{"rendered":"How to Specify a Polishing Template: 6 Parameters Engineers Must Define"},"content":{"rendered":"<!DOCTYPE html>\n<html lang=\"en\">\n<head>\n<meta charset=\"UTF-8\" \/>\n<meta name=\"viewport\" content=\"width=device-width, initial-scale=1.0\" \/>\n\n<!-- \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\n     SEO META TAGS\n     \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 -->\n<meta name=\"description\" content=\"A precise polishing template specification prevents TTV excursions, edge failures, and costly re-qualification loops. Learn the 6 critical parameters every semiconductor engineer must define before ordering.\" \/>\n<meta name=\"keywords\" content=\"polishing template specifications, how to specify polishing template, wafer polishing template parameters, polishing template work hole depth, polishing template backing pad specification, semiconductor polishing template datasheet, polishing template engineering guide\" \/>\n<link rel=\"canonical\" href=\"https:\/\/jeez-semicon.com\/blog\/How-to-Specify-a-Polishing-Template-6-Parameters-Engineers-Must-Define\" \/>\n\n<!-- Open Graph -->\n<meta property=\"og:title\" content=\"How to Specify a Polishing Template: 6 Parameters Engineers Must Define\" \/>\n<meta property=\"og:description\" content=\"Step-by-step engineering specification guide for semiconductor polishing templates. Covers work-hole depth, carrier plate material, backing pad, edge enhancement, and cleanroom requirements.\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:url\" content=\"https:\/\/jeez-semicon.com\/blog\/How-to-Specify-a-Polishing-Template-6-Parameters-Engineers-Must-Define\" \/>\n\n<!-- Schema -->\n<script type=\"application\/ld+json\">\n{\n  \"@context\": \"https:\/\/schema.org\",\n  \"@graph\": [\n    {\n      \"@type\": \"Article\",\n      \"headline\": \"How to Specify a Polishing Template: 6 Parameters Engineers Must Define\",\n      \"description\": \"Engineering guide covering the six critical specification parameters for semiconductor polishing templates, including measurement methods, tolerance rationale, and common specification errors.\",\n      \"author\": {\n        \"@type\": \"Organization\",\n        \"name\": \"Jizhi Electronic Technology Co., Ltd.\",\n        \"url\": \"https:\/\/jeez-semicon.com\"\n      },\n      \"publisher\": {\n        \"@type\": \"Organization\",\n        \"name\": \"Jizhi Electronic Technology Co., Ltd.\",\n        \"url\": \"https:\/\/jeez-semicon.com\"\n      },\n      \"mainEntityOfPage\": {\n        \"@type\": \"WebPage\",\n        \"@id\": \"https:\/\/jeez-semicon.com\/blog\/How-to-Specify-a-Polishing-Template-6-Parameters-Engineers-Must-Define\"\n      }\n    },\n    {\n      \"@type\": \"HowTo\",\n      \"name\": \"How to Specify a Polishing Template for Semiconductor Wafer Processing\",\n      \"description\": \"Step-by-step guide to defining the six critical parameters needed to specify a polishing template for semiconductor wafer polishing.\",\n      \"step\": [\n        {\n          \"@type\": \"HowToStep\",\n          \"name\": \"Define wafer diameter and final target thickness\",\n          \"text\": \"Establish the wafer OD for work-hole diameter calculation and the final target thickness (FTT) that sets work-hole depth. Work-hole depth equals FTT minus backing pad compression offset, with tolerance \u00b15 \u00b5m for prime silicon.\"\n        },\n        {\n          \"@type\": \"HowToStep\",\n          \"name\": \"Confirm carrier head model and retaining ring geometry\",\n          \"text\": \"Identify the polishing machine model and carrier head type. Provide the retaining ring inner diameter, pocket depth, and any keying or alignment features. A dimensioned drawing of the carrier head is the most reliable reference.\"\n        },\n        {\n          \"@type\": \"HowToStep\",\n          \"name\": \"Select carrier plate material against slurry chemistry\",\n          \"text\": \"Match carrier plate material to slurry pH range: FR-4 for alkaline Si polishing (pH 8\u201312), G-10 for mildly acidic environments (pH 5\u201312), CXT seamless grade for SiC and aggressive chemistries (pH 2\u201313).\"\n        },\n        {\n          \"@type\": \"HowToStep\",\n          \"name\": \"Specify backing pad type and hardness\",\n          \"text\": \"Define Shore A durometer, pad thickness, and porosity class based on substrate hardness, process pressure, and TTV target. Harder pads (Shore A 60\u201380) for high-removal SSP; softer pads (Shore A 30\u201355) for CMP, thin wafers, and compound semiconductors.\"\n        },\n        {\n          \"@type\": \"HowToStep\",\n          \"name\": \"Determine edge enhancement ring requirement\",\n          \"text\": \"Specify whether an edge enhancement ring (EER) is required based on edge exclusion target and historical edge rolloff data. Required for edge exclusion below 2 mm or where persistent edge rolloff is a known process issue.\"\n        },\n        {\n          \"@type\": \"HowToStep\",\n          \"name\": \"Define cleanroom class and traceability requirements\",\n          \"text\": \"Specify assembly cleanroom class (standard ISO 5 \/ Class 100), raw material traceability retention period (minimum 5 years), and any additional documentation requirements such as CoC, material certificates, or per-unit particle count data.\"\n        }\n      ]\n    },\n    {\n      \"@type\": \"FAQPage\",\n      \"mainEntity\": [\n        {\n          \"@type\": \"Question\",\n          \"name\": \"What is the most critical parameter when specifying a polishing template?\",\n          \"acceptedAnswer\": {\n            \"@type\": \"Answer\",\n            \"text\": \"Work-hole depth is the single most critical parameter. It directly controls the mechanical position of the wafer surface relative to the polishing pad under load, and a deviation of even 10 \u00b5m in this dimension translates directly into systematic TTV error across every wafer polished on that template. The measurement reference plane (backing pad working surface vs. carrier plate top face) must be explicitly confirmed with the supplier.\"\n          }\n        },\n        {\n          \"@type\": \"Question\",\n          \"name\": \"How do I determine the correct work-hole depth for my wafer?\",\n          \"acceptedAnswer\": {\n            \"@type\": \"Answer\",\n            \"text\": \"Work-hole depth = Final Target Thickness (FTT) minus the backing pad compression offset under process load. The compression offset depends on backing pad hardness, process pressure, and pad age. For a new pad at nominal process pressure, compression offset is typically 5\u201320 \u00b5m for Shore A 60\u201375 pads. Your template supplier should calculate the nominal work-hole depth based on your specified FTT and backing pad specification.\"\n          }\n        },\n        {\n          \"@type\": \"Question\",\n          \"name\": \"What information do I need about my carrier head to specify a polishing template?\",\n          \"acceptedAnswer\": {\n            \"@type\": \"Answer\",\n            \"text\": \"At minimum: polishing machine model and carrier head type designation, retaining ring inner diameter, carrier head pocket depth (the recess into which the template seats), and any keying or alignment features. If possible, provide a dimensioned drawing of the carrier head pocket \u2014 this eliminates geometric ambiguity and prevents the most common first-article dimensional mismatches.\"\n          }\n        },\n        {\n          \"@type\": \"Question\",\n          \"name\": \"Can I use the same polishing template specification for different substrates?\",\n          \"acceptedAnswer\": {\n            \"@type\": \"Answer\",\n            \"text\": \"Only if the substrates share the same final target thickness, the same slurry chemistry compatibility requirements, and the same backing pad compliance needs. In practice, Si and SiC substrates require different specifications even on the same machine platform: SiC requires CXT-grade carrier plate material and a harder backing pad, while Si uses standard FR-4 or G-10 with a softer pad. Using a single specification across incompatible substrates is a common source of process excursions.\"\n          }\n        }\n      ]\n    }\n  ]\n}\n<\/script>\n\n<style>\n  @import url('https:\/\/fonts.googleapis.com\/css2?family=DM+Serif+Display:ital@0;1&family=DM+Sans:opsz,wght@9..40,300;9..40,400;9..40,500;9..40,600&family=JetBrains+Mono:wght@400;500&display=swap');\n\n  :root {\n    --navy:      #0a1628;\n    --navy-mid:  #112240;\n    --blue:      #1a56db;\n    --blue-lite: #3b82f6;\n    --cyan:      #06b6d4;\n    --slate:     #334155;\n    --muted:     #64748b;\n    --border:    #e2e8f0;\n    --bg:        #f8fafc;\n    --white:     #ffffff;\n    --accent:    #f59e0b;\n    --green:     #10b981;\n    --teal:      #0f766e;\n    --red:       #ef4444;\n    --radius:    10px;\n    --shadow:    0 4px 24px rgba(10,22,40,.08);\n    --shadow-lg: 0 12px 48px rgba(10,22,40,.14);\n  }\n\n  *, *::before, *::after { box-sizing: border-box; margin: 0; padding: 0; }\n\n  body {\n    font-family: 'DM Sans', sans-serif;\n    font-size: 16px;\n    line-height: 1.75;\n    color: var(--slate);\n    background: var(--white);\n    -webkit-font-smoothing: antialiased;\n  }\n\n  .page-wrap { max-width: 880px; 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gap: 10px; }\n  .related-links a {\n    display: inline-flex; align-items: center; gap: 6px;\n    background: rgba(255,255,255,.08); border: 1px solid rgba(255,255,255,.15);\n    color: rgba(255,255,255,.9); text-decoration: none;\n    font-size: 13px; font-weight: 500;\n    padding: 8px 14px; border-radius: 6px;\n    transition: background .2s, border-color .2s;\n  }\n  .related-links a:hover { background: rgba(255,255,255,.16); border-color: rgba(255,255,255,.35); color: #fff; }\n  .related-links a::before { content: '\u2197'; font-size: 11px; color: var(--cyan); }\n\n  \/* \u2500\u2500 FAQ \u2500\u2500 *\/\n  .faq-item { border-bottom: 1px solid var(--border); padding: 20px 0; }\n  .faq-item:last-child { border-bottom: none; }\n  .faq-q {\n    font-weight: 600; color: var(--navy-mid); font-size: 16px;\n    margin-bottom: 10px; display: flex; gap: 10px; align-items: flex-start;\n  }\n  .faq-q::before {\n    content: 'Q';\n    font-family: 'JetBrains Mono', monospace; font-size: 12px;\n    color: var(--white); background: var(--blue); border-radius: 4px;\n    padding: 2px 6px; flex-shrink: 0; margin-top: 1px;\n  }\n  .faq-a { font-size: 15px; color: var(--slate); padding-left: 32px; }\n\n  \/* \u2500\u2500 CTA \u2500\u2500 *\/\n  .cta-banner {\n    background: linear-gradient(135deg, #1e3a5f 0%, var(--navy) 100%);\n    border-radius: var(--radius); padding: 44px 40px;\n    text-align: center; color: var(--white); margin: 56px 0 0;\n    box-shadow: var(--shadow-lg); position: relative; overflow: hidden;\n  }\n  .cta-banner::before {\n    content: ''; position: absolute; inset: 0;\n    background: radial-gradient(ellipse at 70% 50%, rgba(6,182,212,.12) 0%, transparent 60%);\n    pointer-events: none;\n  }\n  .cta-banner h2 {\n    font-family: 'DM Serif Display', serif;\n    font-size: clamp(22px, 3.5vw, 30px); color: var(--white); margin: 0 0 12px;\n  }\n  .cta-banner p { color: rgba(255,255,255,.72); font-size: 16px; max-width: 520px; margin: 0 auto 28px; }\n  .cta-btn {\n    display: inline-flex; align-items: center; gap: 8px;\n    background: var(--cyan); color: var(--navy);\n    text-decoration: none; font-weight: 600; font-size: 15px;\n    padding: 14px 32px; border-radius: 8px;\n    transition: opacity .2s, transform .15s;\n  }\n  .cta-btn:hover { opacity: .9; transform: translateY(-1px); color: var(--navy); }\n\n  \/* \u2500\u2500 Back to pillar \u2500\u2500 *\/\n  .back-to-pillar {\n    display: inline-flex; align-items: center; gap: 8px;\n    background: var(--bg); border: 1px solid var(--border);\n    color: var(--slate); text-decoration: none;\n    font-size: 13.5px; font-weight: 500;\n    padding: 10px 18px; border-radius: 8px; margin: 40px 0 0;\n    transition: border-color .2s, color .2s;\n  }\n  .back-to-pillar::before { content: '\u2190'; color: var(--blue); }\n  .back-to-pillar:hover { border-color: var(--blue); color: var(--blue); }\n<\/style>\n<\/head>\n<body>\n\n<!-- \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 HERO \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 -->\n<div class=\"hero\">\n  <div class=\"hero-eyebrow\">Engineering Specification Guide<\/div>\n\n  <p class=\"hero-sub\">Incomplete or ambiguous polishing template specifications are the primary cause of first-article failures, TTV excursions, and unnecessary re-qualification cycles. This guide defines each parameter precisely \u2014 and explains why each one matters.<\/p>\n  <p class=\"hero-meta\">\n    <span>Von Jizhi Electronic Technology Co, Ltd.<\/span>\n    <span>\u00b7<\/span>\n    <span>Spezialisten f\u00fcr das Polieren von Halbleitern<\/span>\n    <span>\u00b7<\/span>\n    <span>12 Minuten lesen<\/span>\n  <\/p>\n<\/div>\n\n<!-- \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 BODY \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 -->\n<div class=\"page-wrap\">\n\n  <!-- Breadcrumb -->\n  <nav class=\"breadcrumb\" aria-label=\"Brotkr\u00fcmel\">\n    <a href=\"https:\/\/jeez-semicon.com\/de\/blog\/Polishing-Templates-for-Semiconductor-Silicon-Wafer-Processing\/\" target=\"_blank\">\u2190 Polierschablonen: Vollst\u00e4ndiger Leitfaden<\/a>\n    <span>\/<\/span>\n    6-Parameter-Spezifikationsleitfaden\n  <\/nav>\n\n  <!-- TOC -->\n  <nav class=\"toc-box\" aria-label=\"Inhalts\u00fcbersicht\">\n    <h2>Inhalts\u00fcbersicht<\/h2>\n    <ol class=\"toc-list\">\n      <li><a href=\"#why-spec-matters\">Why Specification Precision Matters<\/a><\/li>\n      <li><a href=\"#overview\">The 6 Parameters at a Glance<\/a><\/li>\n      <li><a href=\"#p1\">P1 \u2014 Wafer Diameter &amp; Final Target Thickness<\/a><\/li>\n      <li><a href=\"#p2\">P2 \u2014 Carrier Head Model &amp; Geometry<\/a><\/li>\n      <li><a href=\"#p3\">P3 \u2014 Carrier Plate Material<\/a><\/li>\n      <li><a href=\"#p4\">P4 \u2014 Backing Pad Type &amp; Hardness<\/a><\/li>\n      <li><a href=\"#p5\">P5 \u2014 Edge Enhancement Ring Requirement<\/a><\/li>\n      <li><a href=\"#p6\">P6 \u2014 Cleanroom Class &amp; Traceability<\/a><\/li>\n      <li><a href=\"#common-errors\">5 Common Specification Errors &amp; How to Avoid Them<\/a><\/li>\n      <li><a href=\"#checklist\">Pre-Order Specification Checklist<\/a><\/li>\n      <li><a href=\"#faq\">H\u00e4ufig gestellte Fragen<\/a><\/li>\n    <\/ol>\n  <\/nav>\n\n  <!-- \u2550\u2550\u2550 SECTION 1 \u2550\u2550\u2550 -->\n  <h2 id=\"why-spec-matters\">Why Specification Precision Matters More Than You Might Expect<\/h2>\n\n  <p>A polishing template looks deceptively simple: a flat disc with one or more circular holes, bonded to a pad. There are no moving parts, no electronics, no complex chemistry in the material itself. Yet the dimensional precision of a polishing template has a direct, one-to-one relationship with wafer flatness at the nanometer level \u2014 the most critical quality attribute in silicon wafer manufacturing and, increasingly, in silicon carbide and compound semiconductor production.<\/p>\n\n  <p>Consider the scale of this relationship. A 10 \u00b5m error in work-hole depth \u2014 the distance from the backing pad surface to the bottom of the pocket that holds the wafer \u2014 translates into a 10 \u00b5m systematic TTV error across every wafer polished on that template. At a 300 mm node where the TTV specification may be 1.0 \u00b5m or tighter, a 10 \u00b5m specification error is not a marginal miss \u2014 it is an order-of-magnitude excursion. The template goes directly to scrap, and every wafer polished before the excursion is detected must be re-evaluated.<\/p>\n\n  <p>The same principle applies to every other parameter in the specification. A backing pad hardness that is 10 Shore A units too soft leads to excessive wafer movement and edge rolloff. A carrier plate material specified without confirming slurry pH compatibility leads to progressive delamination, contamination, and dimensional drift over 20\u201340 polishing cycles. A carrier head geometry assumption that is 0.5 mm wrong on the retaining ring inner diameter produces a template that physically cannot seat in the carrier head.<\/p>\n\n  <p>Understanding the fundamentals of <a href=\"https:\/\/jeez-semicon.com\/de\/blog\/Polishing-Templates-for-Semiconductor-Silicon-Wafer-Processing\/\" target=\"_blank\" class=\"text-link-pill\">how polishing templates work<\/a> makes clear why each of these parameters is load-bearing. The six parameters described in this guide are not a bureaucratic checklist \u2014 each one controls a distinct failure mode that will manifest in production if the specification is wrong or ambiguous.<\/p>\n\n  <hr class=\"divider\" \/>\n\n  <!-- \u2550\u2550\u2550 SECTION 2 \u2550\u2550\u2550 -->\n  <h2 id=\"overview\">The 6 Parameters at a Glance<\/h2>\n\n  <div class=\"table-wrap\">\n    <table>\n      <thead>\n        <tr>\n          <th>#<\/th>\n          <th>Parameter<\/th>\n          <th>Primary Process Impact<\/th>\n          <th>Criticality<\/th>\n        <\/tr>\n      <\/thead>\n      <tbody>\n        <tr>\n          <td><strong>P1<\/strong><\/td>\n          <td>Wafer diameter &amp; final target thickness<\/td>\n          <td>TTV, work-hole depth, wafer retention force<\/td>\n          <td><span class=\"badge badge-red\">Critical<\/span><\/td>\n        <\/tr>\n        <tr>\n          <td><strong>P2<\/strong><\/td>\n          <td>Carrier head model &amp; geometry<\/td>\n          <td>Template seating, pressure uniformity, machine fit<\/td>\n          <td><span class=\"badge badge-red\">Critical<\/span><\/td>\n        <\/tr>\n        <tr>\n          <td><strong>P3<\/strong><\/td>\n          <td>Material der Tr\u00e4gerplatte<\/td>\n          <td>Chemical compatibility, template life, contamination risk<\/td>\n          <td><span class=\"badge badge-red\">Critical<\/span><\/td>\n        <\/tr>\n        <tr>\n          <td><strong>P4<\/strong><\/td>\n          <td>Backing pad type &amp; hardness<\/td>\n          <td>Pressure distribution, wafer retention, TTV, edge rolloff<\/td>\n          <td><span class=\"badge badge-amber\">Hoch<\/span><\/td>\n        <\/tr>\n        <tr>\n          <td><strong>P5<\/strong><\/td>\n          <td>Edge enhancement ring requirement<\/td>\n          <td>Edge exclusion, edge rolloff, usable die area<\/td>\n          <td><span class=\"badge badge-amber\">Hoch<\/span><\/td>\n        <\/tr>\n        <tr>\n          <td><strong>P6<\/strong><\/td>\n          <td>Cleanroom class &amp; traceability<\/td>\n          <td>Particle contamination, quality system compliance<\/td>\n          <td><span class=\"badge badge-blue\">Standard<\/span><\/td>\n        <\/tr>\n      <\/tbody>\n    <\/table>\n  <\/div>\n\n  <p>The three Critical parameters (P1\u2013P3) define whether the template will physically work in your process at all. An error in any of them produces a template that cannot be used \u2014 and must be redesigned and re-fabricated before any process testing can begin. The two High-impact parameters (P4\u2013P5) determine the quality of the polishing result. Errors here produce templates that fit the machine but deliver substandard TTV or edge profiles. P6 governs the cleanroom and documentation standards that your quality system requires; it is rarely a cause of first-article failure but is important for production qualification and ongoing supply.<\/p>\n\n  <hr class=\"divider\" \/>\n\n  <!-- \u2550\u2550\u2550 THE 6 PARAMETERS \u2550\u2550\u2550 -->\n  <h2 id=\"parameters-section\">The 6 Parameters: Full Engineering Specification Guide<\/h2>\n\n  <div class=\"param-section\">\n\n    <!-- P1 -->\n    <div class=\"param-block\" id=\"p1\">\n      <div class=\"param-header\">\n        <div class=\"param-header-text\">\n          <h3>Wafer Diameter &amp; Final Target Thickness (FTT)<\/h3>\n          <span class=\"param-subtitle\">Sets work-hole diameter and depth \u2014 the two most critical dimensions<\/span>\n        <\/div>\n        <div class=\"param-impact\"><span class=\"impact-pill impact-critical\">Critical<\/span><\/div>\n      <\/div>\n      <div class=\"param-body\">\n        <p>These two values are the dimensional foundation of the entire template specification. They directly determine the two most important machined dimensions: work-hole diameter and work-hole depth.<\/p>\n\n        <p><strong>Work-hole diameter<\/strong> is calculated as the wafer OD plus a radial clearance of 0.2\u20130.5 mm. This clearance is not arbitrary \u2014 it must be tight enough to prevent lateral wafer slippage during polishing (which causes scratch defects and non-circular TTV patterns) while loose enough to allow the wafer to seat cleanly into the pocket without stress-induced bow. For 300 mm silicon, a radial clearance of 0.25\u20130.35 mm is typical. For fragile compound semiconductor substrates (GaAs, InP), tighter clearances of 0.15\u20130.25 mm are used to reduce lateral movement risk, but require more precise incoming wafer OD control to prevent jamming.<\/p>\n\n        <p><strong>Work-hole depth<\/strong> is the most critical single dimension in the polishing template. It controls the mechanical &#8220;stand-off&#8221; of the wafer surface relative to the polishing pad contact plane, which directly determines the downforce applied to the wafer under carrier head load. Too deep, and the wafer is recessed below the pad contact plane \u2014 polishing pressure is reduced and material removal rate drops, while the edge sees relatively higher pressure, producing edge rollup. Too shallow, and the wafer protrudes above the template surface \u2014 edge pressure is reduced and edge rolloff results, with center-high TTV as a secondary effect.<\/p>\n\n        <div class=\"formula-box\">\n          <div class=\"formula-title\">Work-Hole Depth Calculation<\/div>\n          <div class=\"formula-line\">Work-hole depth = FTT \u2212 Pad compression offset (\u0394P)<\/div>\n          <div class=\"formula-line highlight\">\u0394P = f(Shore A hardness, process pressure, pad age)<\/div>\n          <div class=\"formula-line\">Typical \u0394P range: 5\u201320 \u00b5m for Shore A 60\u201375 pad at standard SSP pressure<\/div>\n          <div class=\"formula-note\">* \u0394P must be validated empirically for each pad compound and process pressure combination<\/div>\n        <\/div>\n\n        <p>The most common specification error related to FTT is confusing the incoming wafer thickness (before polishing) with the final target thickness (after polishing). Work-hole depth is set against FTT \u2014 the thickness of the wafer when it exits the polisher. Specifying work-hole depth against incoming wafer thickness produces a template that is systematically too deep by the material removal amount, which is typically 5\u201350 \u00b5m depending on the process.<\/p>\n\n        <div class=\"param-specs\">\n          <div class=\"spec-item\">\n            <div class=\"spec-label\">Work-hole depth tolerance<\/div>\n            <div class=\"spec-value\">\u00b1 5 \u00b5m (prime Si)<\/div>\n          <\/div>\n          <div class=\"spec-item\">\n            <div class=\"spec-label\">Radial clearance range<\/div>\n            <div class=\"spec-value\">0.15 \u2013 0.50 mm<\/div>\n          <\/div>\n          <div class=\"spec-item\">\n            <div class=\"spec-label\">Wafer diameter range<\/div>\n            <div class=\"spec-value\">50 mm \u2013 600 mm<\/div>\n          <\/div>\n          <div class=\"spec-item\">\n            <div class=\"spec-label\">Measurement reference<\/div>\n            <div class=\"spec-value\">Backing pad surface<\/div>\n          <\/div>\n        <\/div>\n\n        <div class=\"param-error\">\n          Common Error: Specifying work-hole depth against the carrier plate top face rather than the backing pad working surface. These differ by the full pad thickness (typically 0.5\u20131.2 mm). Confirming the measurement reference plane in writing with your supplier before design release prevents the most frequently encountered first-article error.\n        <\/div>\n      <\/div>\n    <\/div>\n\n    <!-- P2 -->\n    <div class=\"param-block\" id=\"p2\">\n      <div class=\"param-header\">\n        <div class=\"param-header-text\">\n          <h3>Carrier Head Model &amp; Carrier Head Geometry<\/h3>\n          <span class=\"param-subtitle\">Defines template outer dimensions, seating fit, and pressure transmission path<\/span>\n        <\/div>\n        <div class=\"param-impact\"><span class=\"impact-pill impact-critical\">Critical<\/span><\/div>\n      <\/div>\n      <div class=\"param-body\">\n        <p>The polishing template must fit precisely within the carrier head&#8217;s retaining ring pocket. Get this wrong and the template physically cannot be installed \u2014 there is no partial credit for a near-fit geometry. The carrier head information required to specify a template breaks down into three sub-parameters.<\/p>\n\n        <p><strong>Machine platform and carrier head model.<\/strong> Common platforms each have a documented nominal template geometry: Strasbaugh 6EC and 6DS-SP, Peter Wolters AC2000 and AC3000, Speedfam 9B and 9DSP, Lapmaster 20S and 36S, DISCO DAS8830. For well-established platforms with documented catalog templates, the carrier head geometry is known and the template OD, thickness range, and pocket depth are derivable from existing product data. For lesser-known or OEM platforms, a direct measurement of the carrier head pocket is required.<\/p>\n\n        <p><strong>Retaining ring inner diameter.<\/strong> This is the inner diameter of the retaining ring that constrains the template within the carrier head. The template OD must be 0.1\u20130.3 mm smaller than the retaining ring ID to allow free thermal expansion while preventing lateral play that would shift the template&#8217;s work hole(s) out of concentricity with the carrier head axis. Provide this dimension with a tolerance statement \u2014 &#8220;approximately 300 mm&#8221; is not a usable specification.<\/p>\n\n        <p><strong>Carrier head pocket depth.<\/strong> The recess in the carrier head into which the template seats. Template total thickness (carrier plate + backing pad) must be compatible with this pocket depth to ensure the template seats flat, the backing pad is not over-compressed in the unloaded condition, and the retaining ring can be installed and removed without excessive force.<\/p>\n\n        <div class=\"example-pair\">\n          <div class=\"example-card\">\n            <div class=\"example-card-head wrong\">\u2717 Insufficient Specification<\/div>\n            <div class=\"example-card-body\">\n              Machine: Strasbaugh<br>\n              Wafer size: 300 mm<br><br>\n              <span class=\"note\">Missing: carrier head model revision, retaining ring ID measurement, pocket depth. &#8220;Strasbaugh&#8221; has 5+ carrier head configurations for 300 mm \u2014 none of which are interchangeable.<\/span>\n            <\/div>\n          <\/div>\n          <div class=\"example-card\">\n            <div class=\"example-card-head correct\">\u2713 Complete Specification<\/div>\n            <div class=\"example-card-body\">\n              Machine: Strasbaugh 6EC<br>\n              Carrier head: Type B (6EC-CB)<br>\n              Retaining ring ID: 305.5 \u00b1 0.1 mm<br>\n              Pocket depth: 6.2 \u00b1 0.05 mm<br>\n              <span class=\"note\">Dimensioned drawing attached. All critical tolerances stated explicitly.<\/span>\n            <\/div>\n          <\/div>\n        <\/div>\n\n        <div class=\"param-specs\">\n          <div class=\"spec-item\">\n            <div class=\"spec-label\">Template OD clearance<\/div>\n            <div class=\"spec-value\">0.1 \u2013 0.3 mm under RR ID<\/div>\n          <\/div>\n          <div class=\"spec-item\">\n            <div class=\"spec-label\">Plate flatness (bow)<\/div>\n            <div class=\"spec-value\">\u2264 10 \u00b5m (standard)<\/div>\n          <\/div>\n          <div class=\"spec-item\">\n            <div class=\"spec-label\">Thickness tolerance<\/div>\n            <div class=\"spec-value\">\u00b1 25 \u00b5m total stack<\/div>\n          <\/div>\n          <div class=\"spec-item\">\n            <div class=\"spec-label\">Best practice<\/div>\n            <div class=\"spec-value\">Provide head drawing<\/div>\n          <\/div>\n        <\/div>\n      <\/div>\n    <\/div>\n\n    <!-- P3 -->\n    <div class=\"param-block\" id=\"p3\">\n      <div class=\"param-header\">\n        <div class=\"param-header-text\">\n          <h3>Material der Tr\u00e4gerplatte<\/h3>\n          <span class=\"param-subtitle\">Must be chemically compatible with slurry pH and temperature across full template service life<\/span>\n        <\/div>\n        <div class=\"param-impact\"><span class=\"impact-pill impact-critical\">Critical<\/span><\/div>\n      <\/div>\n      <div class=\"param-body\">\n        <p>Carrier plate material selection is a chemical engineering decision, not a procurement convenience. The carrier plate is in continuous contact with polishing slurry throughout every polishing cycle. Over time, an incompatible material will swell, delaminate, leach contaminants into the slurry, and change dimensions \u2014 all of which degrade process performance and, in severe cases, contaminate the wafer surface.<\/p>\n\n        <p>Three material families cover the vast majority of semiconductor polishing applications. The selection logic follows a simple hierarchy: start with FR-4, step up to G-10 if the slurry is mildly acidic, and specify CXT-grade if the chemistry is outside the laminate envelope entirely. For the detailed material property comparison, our article on <a href=\"https:\/\/jeez-semicon.com\/de\/blog\/FR-4-vs-G-10-Fiberglass-Polishing-Templates-Material-Properties-Selection-Guide\/\" target=\"_blank\" class=\"text-link-pill\">FR-4 vs G-10 fiberglass polishing templates<\/a> covers the full property data.<\/p>\n\n        <div class=\"table-wrap\">\n          <table>\n            <thead>\n              <tr>\n                <th>Material<\/th>\n                <th>pH-Bereich<\/th>\n                <th>Typische Anwendung<\/th>\n                <th>Key Limitation<\/th>\n              <\/tr>\n            <\/thead>\n            <tbody>\n              <tr class=\"row-ok\">\n                <td><strong>FR-4<\/strong><\/td>\n                <td>8 - 12<\/td>\n                <td>Si SSP with alkaline silica slurry<\/td>\n                <td>Epoxy swells in acid; requires edge sealing to prevent fiber shedding<\/td>\n              <\/tr>\n              <tr class=\"row-ok\">\n                <td><strong>G-10<\/strong><\/td>\n                <td>5 - 12<\/td>\n                <td>Si SSP + mildly acidic slurries (citric, HNO\u2083-buffered)<\/td>\n                <td>Not suitable below pH 5; similar fiber-shedding risk if edges unsealed<\/td>\n              <\/tr>\n              <tr class=\"row-warn\">\n                <td><strong>CXT Seamless<\/strong><\/td>\n                <td>2 - 13<\/td>\n                <td>SiC CMP (KMnO\u2084), GaAs bromine-based, aggressive oxide CMP<\/td>\n                <td>Higher unit cost; custom-only; longer fabrication lead time<\/td>\n              <\/tr>\n            <\/tbody>\n          <\/table>\n        <\/div>\n\n        <p>When specifying carrier plate material, do not rely on slurry product names alone \u2014 specify the pH range and any oxidant components explicitly. The same slurry brand may be formulated differently for different substrate applications, and supplier formulations change over time. A material selection made against &#8220;Cabot Microelectronics SS25&#8221; slurry in 2018 may not be valid against the current formulation of the same product.<\/p>\n\n        <p>For SiC CMP applications, the CXT seamless grade is not optional \u2014 it is a process requirement. Standard FR-4 templates in KMnO\u2084 slurry at pH 2\u20134 typically show visible delamination within 15\u201325 polishing cycles, followed by progressive slurry penetration into the carrier plate laminate, dimensional swelling, and ultimately work-hole geometry distortion that produces systematic TTV excursions. Full technical guidance on SiC-specific template requirements is in our <a href=\"https:\/\/jeez-semicon.com\/de\/blog\/SiC-Wafer-Polishing-Templates-Chemically-Resistant-Solutions-for-Silicon-Carbide-Processing\/\" target=\"_blank\" class=\"text-link-pill\">SiC wafer polishing template guide<\/a>.<\/p>\n\n        <div class=\"param-specs\">\n          <div class=\"spec-item\">\n            <div class=\"spec-label\">Required inputs<\/div>\n            <div class=\"spec-value\">Slurry type + pH range<\/div>\n          <\/div>\n          <div class=\"spec-item\">\n            <div class=\"spec-label\">Oxidant components<\/div>\n            <div class=\"spec-value\">Must be stated explicitly<\/div>\n          <\/div>\n          <div class=\"spec-item\">\n            <div class=\"spec-label\">Process temperature<\/div>\n            <div class=\"spec-value\">State if &gt; 40\u00b0C<\/div>\n          <\/div>\n          <div class=\"spec-item\">\n            <div class=\"spec-label\">Edge treatment<\/div>\n            <div class=\"spec-value\">Seal required (FR-4, G-10)<\/div>\n          <\/div>\n        <\/div>\n      <\/div>\n    <\/div>\n\n    <!-- P4 -->\n    <div class=\"param-block\" id=\"p4\">\n      <div class=\"param-header\">\n        <div class=\"param-header-text\">\n          <h3>St\u00fctzteller Typ &amp; H\u00e4rte<\/h3>\n          <span class=\"param-subtitle\">Controls pressure distribution uniformity, wafer retention, and edge rolloff tendency<\/span>\n        <\/div>\n        <div class=\"param-impact\"><span class=\"impact-pill impact-high\">Hoch<\/span><\/div>\n      <\/div>\n      <div class=\"param-body\">\n        <p>The backing pad is the mechanical interface between the rigid carrier plate and the wafer backside. Its compliance \u2014 the combination of Shore A hardness, thickness, and internal porosity \u2014 determines how faithfully the carrier head&#8217;s applied pressure is distributed across the wafer area, and how much the wafer is allowed to flex relative to the polishing pad surface.<\/p>\n\n        <p>Specifying backing pad hardness requires knowing three things about your process: the substrate material and its hardness, the nominal carrier head process pressure (in g\/cm\u00b2 or psi), and the target TTV and edge profile requirements. The relationship between these inputs and optimal pad hardness follows a consistent pattern:<\/p>\n\n        <ul>\n          <li><strong>Hard substrates + high process pressure<\/strong> (SiC CMP at 5\u20137 psi) \u2192 hard backing pad (Shore A 70\u201385). A soft pad would over-compress under high load, reducing effective work-hole depth control and creating TTV instability over the template&#8217;s service life as the pad fatigues.<\/li>\n          <li><strong>Soft or fragile substrates at moderate pressure<\/strong> (GaAs, thin Si at 1\u20133 psi) \u2192 soft pad (Shore A 30\u201355). The soft pad absorbs carrier head pressure non-uniformities and reduces the risk of stress concentrations at the wafer edge that could initiate fracture in brittle III-V materials.<\/li>\n          <li><strong>Standard Si SSP at nominal pressure<\/strong> (2\u20135 psi) \u2192 medium pad (Shore A 55\u201375). This is the most common configuration and the one for which standard catalog templates are optimized.<\/li>\n        <\/ul>\n\n        <p>Pad thickness matters independently of hardness. Thicker pads provide greater compliance and are preferred for applications where the carrier head has a non-uniform pressure profile (a common characteristic of older or heavily worn carrier heads). Thinner pads provide more precise depth control and are preferred for ultra-tight TTV applications where every micrometer of pad compression must be accounted for.<\/p>\n\n        <div class=\"param-specs\">\n          <div class=\"spec-item\">\n            <div class=\"spec-label\">Required inputs<\/div>\n            <div class=\"spec-value\">Substrate + process pressure<\/div>\n          <\/div>\n          <div class=\"spec-item\">\n            <div class=\"spec-label\">Hardness range<\/div>\n            <div class=\"spec-value\">Shore A 30 \u2013 85<\/div>\n          <\/div>\n          <div class=\"spec-item\">\n            <div class=\"spec-label\">Thickness range<\/div>\n            <div class=\"spec-value\">0.4 \u2013 1.2 mm<\/div>\n          <\/div>\n          <div class=\"spec-item\">\n            <div class=\"spec-label\">Thickness uniformity<\/div>\n            <div class=\"spec-value\">\u00b1 15 \u00b5m across pad area<\/div>\n          <\/div>\n        <\/div>\n\n        <div class=\"param-error\">\n          Common Error: Specifying &#8220;standard backing pad&#8221; without stating hardness or thickness. Suppliers may interpret this differently, leading to TTV performance that cannot be reproduced between lots. Always specify Shore A hardness and nominal thickness explicitly, with tolerances.\n        <\/div>\n      <\/div>\n    <\/div>\n\n    <!-- P5 -->\n    <div class=\"param-block\" id=\"p5\">\n      <div class=\"param-header\">\n        <div class=\"param-header-text\">\n          <h3>Randverst\u00e4rkungsring (EER) Anforderung<\/h3>\n          <span class=\"param-subtitle\">Determines edge exclusion zone and edge rolloff profile<\/span>\n        <\/div>\n        <div class=\"param-impact\"><span class=\"impact-pill impact-high\">Hoch<\/span><\/div>\n      <\/div>\n      <div class=\"param-body\">\n        <p>The edge enhancement ring (EER) is an optional but increasingly important feature in polishing templates for advanced process nodes. Its purpose is to modify the pressure distribution in the annular zone between the wafer OD and the work-hole wall \u2014 the region that controls edge flatness and determines the size of the edge exclusion zone.<\/p>\n\n        <p>Without an EER, the template in the annular zone adjacent to the wafer edge provides relatively little mechanical support to the polishing pad. The pad deflects slightly under the wafer edge, reducing local contact pressure and creating a characteristic &#8220;rolloff&#8221; \u2014 a zone of lower-than-average material removal rate that leaves the wafer edge thicker than the center. For 300 mm silicon wafers at legacy process nodes, a 3\u20135 mm edge exclusion zone was standard and acceptable. For advanced logic and memory at 5 nm and below, edge exclusion targets of 1.0\u20131.5 mm require a polishing template with engineered edge support.<\/p>\n\n        <p>The EER achieves this by adding a precision-machined annular feature on the template back face, concentrically positioned relative to the work hole. This feature increases local stiffness in the edge zone, countering the pad deflection that causes rolloff. The geometry of the EER \u2014 inner and outer diameter, height, material \u2014 is custom-engineered to the specific wafer diameter, final thickness, backing pad specification, and target edge profile. Read the detailed technical engineering background in our article on <a href=\"https:\/\/jeez-semicon.com\/de\/blog\/How-Polishing-Template-Edge-Design-Controls-Wafer-Edge-Profile-Reduces-Edge-Exclusion\/\" target=\"_blank\" class=\"text-link-pill\">edge profile control and edge exclusion reduction<\/a>.<\/p>\n\n        <p>To specify the EER requirement, provide two inputs: your target edge exclusion in millimeters, and your historical edge profile data (maximum rolloff height at 1 mm and 2 mm from the wafer edge) from your current process. If you have no historical data, the EER geometry is initially estimated from the wafer diameter and backing pad specification, then iterated based on first-article process data.<\/p>\n\n        <div class=\"param-specs\">\n          <div class=\"spec-item\">\n            <div class=\"spec-label\">Required if EE target<\/div>\n            <div class=\"spec-value\">&lt; 2 mm<\/div>\n          <\/div>\n          <div class=\"spec-item\">\n            <div class=\"spec-label\">Required inputs<\/div>\n            <div class=\"spec-value\">EE target + rolloff data<\/div>\n          <\/div>\n          <div class=\"spec-item\">\n            <div class=\"spec-label\">EER geometry<\/div>\n            <div class=\"spec-value\">Custom per application<\/div>\n          <\/div>\n          <div class=\"spec-item\">\n            <div class=\"spec-label\">Iteration expected?<\/div>\n            <div class=\"spec-value\">Yes \u2014 1 to 2 cycles typical<\/div>\n          <\/div>\n        <\/div>\n      <\/div>\n    <\/div>\n\n    <!-- P6 -->\n    <div class=\"param-block\" id=\"p6\">\n      <div class=\"param-header\">\n        <div class=\"param-header-text\">\n          <h3>Cleanroom Class &amp; Traceability Requirements<\/h3>\n          <span class=\"param-subtitle\">Governs particle contamination risk and quality system compliance<\/span>\n        <\/div>\n        <div class=\"param-impact\"><span class=\"impact-pill impact-medium\">Standard<\/span><\/div>\n      <\/div>\n      <div class=\"param-body\">\n        <p>Polishing templates are assembled in a cleanroom environment, and the class of that environment determines the maximum particle population on the template surface at the point of packaging. For most semiconductor production applications, ISO Class 5 (Class 100) assembly is adequate \u2014 this is Jizhi&#8217;s standard production environment. For advanced front-end-of-line applications at 28 nm and below, where wafer surface particle budgets are extremely tight, ISO Class 4 assembly (10\u00d7 cleaner than Class 5) may be specified.<\/p>\n\n        <p>Beyond cleanroom class, there are four documentation elements that should be explicitly stated in the specification, as they form the quality system backbone for the template&#8217;s entire production life:<\/p>\n\n        <ul>\n          <li><strong>Raw material traceability retention period.<\/strong> Standard Jizhi practice is a minimum of 5 years, covering carrier plate material, backing pad compound, and all adhesive systems. If your quality system or customer audit requirements mandate a longer retention period, specify this explicitly.<\/li>\n          <li><strong>Certificate of Conformance (CoC).<\/strong> A written statement confirming that the delivered lot was manufactured in accordance with the released drawing and all specified quality requirements. This is standard for semiconductor consumable supply; confirm whether your receiving inspection requires a per-lot or per-unit CoC.<\/li>\n          <li><strong>Material certificates.<\/strong> Raw material mill certificates for the carrier plate laminate, confirming composition, dielectric properties, and dimensional conformance to the relevant NEMA or IPC standard. Required for most semiconductor quality audits.<\/li>\n          <li><strong>Per-unit dimensional inspection data.<\/strong> For high-specification applications, a CMM measurement report for each individual template (rather than a sampling-based lot report) may be required. This increases cost and lead time; specify only if your process control requirements genuinely demand it.<\/li>\n        <\/ul>\n\n        <div class=\"callout tip\">\n          <span class=\"callout-icon\">\ud83d\udca1<\/span>\n          <div class=\"callout-body\">\n            <strong>Contamination Control in Use<\/strong>\n            Specifying cleanroom assembly class only covers the template at the point of manufacture. Maintaining that cleanliness level through shipping, receiving, storage, and installation is equally important. Our article on <a href=\"https:\/\/jeez-semicon.com\/de\/blog\/Contamination-Control-in-Polishing-Templates-Clean-Room-Assembly-Particle-Prevention\/\" target=\"_blank\">contamination control in polishing templates<\/a> provides the in-fab handling protocol.\n          <\/div>\n        <\/div>\n\n        <div class=\"param-specs\">\n          <div class=\"spec-item\">\n            <div class=\"spec-label\">Standard assembly class<\/div>\n            <div class=\"spec-value\">ISO 5 \/ Class 100<\/div>\n          <\/div>\n          <div class=\"spec-item\">\n            <div class=\"spec-label\">Advanced assembly class<\/div>\n            <div class=\"spec-value\">ISO 4 (on request)<\/div>\n          <\/div>\n          <div class=\"spec-item\">\n            <div class=\"spec-label\">Traceability retention<\/div>\n            <div class=\"spec-value\">\u2265 5 years (standard)<\/div>\n          <\/div>\n          <div class=\"spec-item\">\n            <div class=\"spec-label\">Verpackung<\/div>\n            <div class=\"spec-value\">Individual N\u2082-sealed PE bag<\/div>\n          <\/div>\n        <\/div>\n      <\/div>\n    <\/div>\n\n  <\/div><!-- \/.param-section -->\n\n  <hr class=\"divider\" \/>\n\n  <!-- \u2550\u2550\u2550 SECTION \u2014 COMMON ERRORS \u2550\u2550\u2550 -->\n  <h2 id=\"common-errors\">5 Common Specification Errors &amp; How to Avoid Them<\/h2>\n\n  <p>The following five errors appear repeatedly in polishing template specification submissions. Each has a distinct failure mode and a straightforward prevention method.<\/p>\n\n  <h3>Error 1: Confusing Incoming Wafer Thickness with Final Target Thickness<\/h3>\n  <p>Work-hole depth is set against the final target thickness \u2014 the wafer after polishing. Providing the incoming (pre-polishing) wafer thickness produces a template that is systematically too deep, resulting in reduced polishing pressure and a center-thick TTV pattern. Prevention: always label the value you provide as either &#8220;incoming thickness before polishing&#8221; or &#8220;FTT after polishing&#8221; \u2014 never just &#8220;wafer thickness.&#8221;<\/p>\n\n  <h3>Error 2: Omitting the Work-Hole Depth Measurement Reference Plane<\/h3>\n  <p>Work-hole depth can be measured from either the backing pad working surface or the carrier plate top face. These differ by the full pad thickness \u2014 typically 0.5\u20131.2 mm. A specification that simply states &#8220;work-hole depth: 725 \u00b5m&#8221; without defining the reference plane is ambiguous and will produce a first-article template that is wrong by the full pad thickness. Prevention: always state &#8220;depth from backing pad working surface&#8221; or &#8220;depth from carrier plate top face&#8221; explicitly, and confirm this in writing with the supplier before fabrication begins.<\/p>\n\n  <h3>Error 3: Specifying Slurry by Brand Name Without pH Range<\/h3>\n  <p>Slurry formulations change over time, and the same product name may cover multiple pH variants in a supplier&#8217;s portfolio. &#8220;We use Cabot SS25&#8221; is not a material compatibility specification. Prevention: always state the pH range and any oxidant components (H\u2082O\u2082, KMnO\u2084, NH\u2084OH, HF, etc.) explicitly. This is the information your template supplier needs to validate material selection \u2014 the slurry brand name alone is insufficient.<\/p>\n\n  <h3>Error 4: Assuming Carrier Head Geometry from Machine Platform Name<\/h3>\n  <p>Multiple carrier head configurations exist for most major polishing platforms, and template geometry differs between them. A Strasbaugh 6EC with a Type A carrier head and a Strasbaugh 6EC with a Type B head require different templates. Prevention: provide the carrier head model designation, not just the machine platform name. If the carrier head type is unknown, measure the retaining ring ID and pocket depth directly and provide the raw measurements with a tolerance statement.<\/p>\n\n  <h3>Error 5: Specifying Backing Pad as &#8220;Standard&#8221; Without Hardness<\/h3>\n  <p>Different suppliers use different backing pad compounds as their &#8220;standard&#8221; \u2014 and even within a single supplier, standard pad hardness may be optimized for different wafer diameters. A 300 mm standard pad and a 150 mm standard pad are often different compounds with different Shore A values. Prevention: always specify backing pad hardness by Shore A range (e.g., &#8220;Shore A 60\u201370&#8221;) and nominal thickness. If you do not know what hardness your current template uses, ask your current supplier for the specification before switching.<\/p>\n\n  <hr class=\"divider\" \/>\n\n  <!-- \u2550\u2550\u2550 CHECKLIST \u2550\u2550\u2550 -->\n  <h2 id=\"checklist\">Pre-Order Specification Checklist<\/h2>\n\n  <p>Use the following checklist before submitting a polishing template specification to Jizhi or any other supplier. Each item corresponds to a parameter that, if missing or ambiguous, will generate an engineering clarification request and extend your lead time.<\/p>\n\n  <ul class=\"checklist\">\n    <li><strong>Wafer diameter (mm):<\/strong> state the nominal OD with tolerance if non-standard<\/li>\n    <li><strong>Final target thickness after polishing (\u00b5m):<\/strong> confirm this is FTT, not incoming thickness<\/li>\n    <li><strong>Work-hole count and pattern:<\/strong> single-cavity or multi-cavity; if multi, specify count<\/li>\n    <li><strong>Polishing machine model:<\/strong> manufacturer + model + carrier head type designation<\/li>\n    <li><strong>Retaining ring inner diameter (mm):<\/strong> measured value with tolerance, not nominal guess<\/li>\n    <li><strong>Carrier head pocket depth (mm):<\/strong> or provide a dimensioned drawing of the carrier head<\/li>\n    <li><strong>Slurry type and pH range:<\/strong> include oxidant components if present<\/li>\n    <li><strong>Process temperature:<\/strong> state if above 40\u00b0C<\/li>\n    <li><strong>Carrier plate material:<\/strong> FR-4, G-10, or CXT; or request a material recommendation<\/li>\n    <li><strong>Backing pad Shore A hardness range and nominal thickness (mm):<\/strong> do not leave as &#8220;standard&#8221;<\/li>\n    <li><strong>Edge enhancement ring required? (Yes\/No):<\/strong> if Yes, provide edge exclusion target and historical edge profile data if available<\/li>\n    <li><strong>Cleanroom assembly class:<\/strong> ISO 5 standard, or ISO 4 if required<\/li>\n    <li><strong>Documentation requirements:<\/strong> CoC, material certificates, per-lot or per-unit CMM report<\/li>\n    <li><strong>Quantity:<\/strong> qualification lot size and anticipated production lot size<\/li>\n    <li><strong>Target ship date or required-by date:<\/strong> for lead time planning<\/li>\n  <\/ul>\n\n  <div class=\"callout info\">\n    <span class=\"callout-icon\">\u2139\ufe0f<\/span>\n    <div class=\"callout-body\">\n      <strong>Not Sure How to Fill This In?<\/strong>\n      If you are specifying a polishing template for the first time, or specifying for a non-standard substrate or machine, our engineering team is available for a pre-specification consultation at no charge. Send us what you know and we will identify the gaps and recommend values for any parameters you cannot determine from your current process documentation.\n    <\/div>\n  <\/div>\n\n  <!-- Related articles -->\n  <div class=\"related-box\">\n    <h3>\ud83d\udcd6 Verwandte technische Artikel<\/h3>\n    <p>Continue building your polishing template engineering knowledge:<\/p>\n    <div class=\"related-links\">\n      <a href=\"https:\/\/jeez-semicon.com\/de\/blog\/Custom-Polishing-Templates-for-Silicon-Wafers-Tailored-to-Your-Carrier-Head-Specs\/\" target=\"_blank\">Kundenspezifische Vorlagentechnik<\/a>\n      <a href=\"https:\/\/jeez-semicon.com\/de\/blog\/Standard-vs-Custom-Polishing-Templates-Which-Is-Right-for-Your-Wafer-Process\/\" target=\"_blank\">Vergleich Standard vs. Individuell<\/a>\n      <a href=\"https:\/\/jeez-semicon.com\/de\/blog\/FR-4-vs-G-10-Fiberglass-Polishing-Templates-Material-Properties-Selection-Guide\/\" target=\"_blank\">FR-4 vs. G-10 Material Leitfaden<\/a>\n      <a href=\"https:\/\/jeez-semicon.com\/de\/blog\/SiC-Wafer-Polishing-Templates-Chemically-Resistant-Solutions-for-Silicon-Carbide-Processing\/\" target=\"_blank\">SiC-Polierschablonen<\/a>\n      <a href=\"https:\/\/jeez-semicon.com\/de\/blog\/How-Polishing-Template-Edge-Design-Controls-Wafer-Edge-Profile-Reduces-Edge-Exclusion\/\" target=\"_blank\">Kantenprofil &amp; EER-Design<\/a>\n      <a href=\"https:\/\/jeez-semicon.com\/de\/blog\/Contamination-Control-in-Polishing-Templates-Clean-Room-Assembly-Particle-Prevention\/\" target=\"_blank\">Kontrolle der Kontamination<\/a>\n    <\/div>\n  <\/div>\n\n  <hr class=\"divider\" \/>\n\n  <!-- \u2550\u2550\u2550 FAQ \u2550\u2550\u2550 -->\n  <h2 id=\"faq\">H\u00e4ufig gestellte Fragen<\/h2>\n\n  <div class=\"faq-item\">\n    <div class=\"faq-q\">What is the most critical parameter when specifying a polishing template?<\/div>\n    <div class=\"faq-a\">Work-hole depth is the single most critical parameter. A deviation of even 10 \u00b5m translates directly into systematic TTV error across every wafer polished on that template. The most important sub-detail is the measurement reference plane: work-hole depth must be measured from the backing pad working surface, not the carrier plate top face. Confirming this reference in writing with your supplier before fabrication begins prevents the most frequently encountered first-article error.<\/div>\n  <\/div>\n\n  <div class=\"faq-item\">\n    <div class=\"faq-q\">How do I determine the correct work-hole depth for my wafer?<\/div>\n    <div class=\"faq-a\">Work-hole depth equals Final Target Thickness (FTT) minus the backing pad compression offset under process load. The compression offset depends on backing pad hardness (Shore A), process pressure (g\/cm\u00b2), and pad age. For a new pad at nominal SSP pressure, the offset is typically 5\u201320 \u00b5m for Shore A 60\u201375 compounds. Your template supplier should calculate the nominal work-hole depth based on your stated FTT and backing pad specification \u2014 do not attempt to calculate this without confirming the supplier&#8217;s pad compression data for the specific compound being used.<\/div>\n  <\/div>\n\n  <div class=\"faq-item\">\n    <div class=\"faq-q\">What information do I need about my carrier head to specify a polishing template?<\/div>\n    <div class=\"faq-a\">Minimum required: polishing machine model and carrier head type designation, retaining ring inner diameter (measured, with tolerance), and carrier head pocket depth. The best submission is a dimensioned drawing of the carrier head pocket \u2014 this eliminates all geometric ambiguity and prevents the most common first-article dimensional mismatches. If you cannot obtain a drawing, provide measured values from a direct CMM or caliper measurement of the physical carrier head.<\/div>\n  <\/div>\n\n  <div class=\"faq-item\">\n    <div class=\"faq-q\">Can I use the same polishing template specification for different substrates on the same machine?<\/div>\n    <div class=\"faq-a\">Only if the substrates share identical final target thickness, compatible slurry chemistry (same pH range), and the same backing pad compliance needs. In practice, Si and SiC substrates running on the same machine platform require entirely different template specifications: SiC demands CXT-grade carrier plate material and a harder backing pad, while Si uses standard FR-4 or G-10 with a softer pad. Using a single specification across incompatible substrates is a common source of process excursions and template premature failure.<\/div>\n  <\/div>\n\n  <div class=\"faq-item\">\n    <div class=\"faq-q\">Do I need to specify an edge enhancement ring for every application?<\/div>\n    <div class=\"faq-a\">No. Edge enhancement rings are required when the edge exclusion target is below 2 mm, or when persistent edge rolloff is a known and unresolved issue in your current process. For standard commodity silicon polishing with an edge exclusion specification of 3 mm or greater, standard template geometry without an EER is adequate. If you are unsure whether your process would benefit from EER design, share your historical edge profile data with our engineering team for a no-obligation assessment.<\/div>\n  <\/div>\n\n  <!-- CTA -->\n  <div class=\"cta-banner\">\n    <h2>Holen Sie sich ein Angebot f\u00fcr Ihre Poliervorlagenanforderungen<\/h2>\n    <p>Ready to submit your specification? Share your six parameters with our engineering team and receive a technical review and competitive quote within 48 hours.<\/p>\n    <a href=\"https:\/\/jeez-semicon.com\/de\/contact\/\" class=\"cta-btn\" target=\"_blank\">\n      Kontaktieren Sie uns f\u00fcr ein Angebot \u2192\n    <\/a>\n  <\/div>\n\n  <!-- Back to pillar -->\n  <a href=\"https:\/\/jeez-semicon.com\/de\/blog\/Polishing-Templates-for-Semiconductor-Silicon-Wafer-Processing\/\" target=\"_blank\" class=\"back-to-pillar\">\n    Zur\u00fcck zu Poliervorlagen: Vollst\u00e4ndiger Leitfaden\n  <\/a>\n\n<\/div><!-- \/.page-wrap -->\n<\/body>\n<\/html>","protected":false},"excerpt":{"rendered":"<p>Engineering Specification Guide Incomplete or ambiguous polishing template specifications are the primary cause of first-article failures, TTV excursions, and unnecessary re-qualification cycles. This guide defines each parameter precisely \u2014 and  &#8230;<\/p>","protected":false},"author":1,"featured_media":1683,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[9,59],"tags":[],"class_list":["post-1643","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-blog","category-industry"],"acf":[],"_links":{"self":[{"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/posts\/1643","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/comments?post=1643"}],"version-history":[{"count":2,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/posts\/1643\/revisions"}],"predecessor-version":[{"id":1645,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/posts\/1643\/revisions\/1645"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/media\/1683"}],"wp:attachment":[{"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/media?parent=1643"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/categories?post=1643"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/tags?post=1643"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}