{"id":1767,"date":"2026-04-07T15:55:02","date_gmt":"2026-04-07T07:55:02","guid":{"rendered":"https:\/\/jeez-semicon.com\/?p=1767"},"modified":"2026-04-07T16:33:42","modified_gmt":"2026-04-07T08:33:42","slug":"hard-vs-soft-cmp-polishing-pads-selection-guide","status":"publish","type":"post","link":"https:\/\/jeez-semicon.com\/de\/blog\/hard-vs-soft-cmp-polishing-pads-selection-guide\/","title":{"rendered":"Hard vs. Soft CMP Polishing Pads: The Definitive Selection Guide"},"content":{"rendered":"<!-- ============================================================\r\n     CLUSTER 4 \u2014 Hard vs. Soft CMP Polishing Pads: Selection Guide\r\n     Jizhi Electronic Technology Co., Ltd.\r\n     jeez-semicon.com  |  April 2026\r\n     Paste into WordPress Gutenberg \u2192 Custom HTML block\r\n     URL: \/blog\/Hard-vs-Soft-CMP-Polishing-Pads-Selection-Guide\r\n     ============================================================ -->\r\n<p><style>\r\n@import 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href=\"https:\/\/jeez-semicon.com\/de\/blog\/CMP-Polishing-Pads-The-Complete-Guide\/\" target=\"_blank\" rel=\"noopener\">Back to CMP Polishing Pads: The Complete Guide<\/a> <!-- Hero -->\r\n<div class=\"jz-hero\">\r\n<div class=\"jz-hero-kicker\">Jizhi Electronic Technology \u2014 Selection Guide Series<\/div>\r\n<p class=\"jz-hero-lead\">A rigorous, application-mapped guide to choosing between hard and soft CMP polishing pads \u2014 covering the fundamental physics of the trade-off, process-step-by-step recommendations, stacked pad strategy, and a practical decision framework for fab engineers.<\/p>\r\n<div class=\"jz-hero-meta\">\ud83d\udcc5 April 2026\u23f1 15 min read\ud83c\udfed Jizhi Electronic Technology Co., Ltd.<\/div>\r\n<\/div>\r\n<!-- Tags -->\r\n<div class=\"jz-tags\"><span class=\"jz-tag\">Hard CMP Pad<\/span> <span class=\"jz-tag\">Soft CMP Pad<\/span> <span class=\"jz-tag\">Pad Selection Guide<\/span> <span class=\"jz-tag\">Planarization Efficiency<\/span> <span class=\"jz-tag\">WIWNU<\/span> <span class=\"jz-tag\">Stacked Pad<\/span> <span class=\"jz-tag\">Shore D Hardness<\/span> <span class=\"jz-tag\">Cu BEOL<\/span><\/div>\r\n<!-- Trust bar -->\r\n<div class=\"jz-trust\">\r\n<div class=\"jz-trust-badge\">Process<br \/>Verified<\/div>\r\n<div class=\"jz-trust-text\"><strong>Written by Jizhi Electronic Technology Co., Ltd.<\/strong> \u2014 CMP pad manufacturer supplying both hard polyurethane pads and soft subpads to wafer fabs, equipment makers, and research institutions. Selection recommendations are based on our in-house process characterization data and current April 2026 industry practice.<\/div>\r\n<\/div>\r\n<!-- TOC -->\r\n<div class=\"jz-toc\">\r\n<div class=\"jz-toc-title\">\ud83d\udccb Inhaltsverzeichnis<\/div>\r\n<ol>\r\n<li><a href=\"#core-tradeoff\">The Core Trade-off: Planarity vs. Uniformity<\/a><\/li>\r\n<li><a href=\"#hard-pad-deep\">Hard Pads: Properties and Strengths<\/a><\/li>\r\n<li><a href=\"#soft-pad-deep\">Soft Pads: Properties and Strengths<\/a><\/li>\r\n<li><a href=\"#head-to-head\">Head-to-Head Comparison Table<\/a><\/li>\r\n<li><a href=\"#application-map\">Application-by-Application Selection Map<\/a><\/li>\r\n<li><a href=\"#stacked-strategy\">The Stacked Pad Strategy<\/a><\/li>\r\n<li><a href=\"#decision-tree\">Decision Framework: Which Pad for Your Step?<\/a><\/li>\r\n<li><a href=\"#qualification\">Qualifying a New Pad Hardness<\/a><\/li>\r\n<li><a href=\"#jizhi-range\">Jizhi&#8217;s Hard and Soft Pad Range<\/a><\/li>\r\n<li><a href=\"#faq\">FAQ<\/a><\/li>\r\n<\/ol>\r\n<\/div>\r\n<!-- Intro -->\r\n<p>Every CMP process engineer eventually faces the same fundamental decision: hard pad or soft pad? The question seems deceptively simple \u2014 but it sits at the intersection of contact mechanics, surface chemistry, and wafer-scale uniformity physics. Getting it wrong can mean poor planarization (hard pad selected where soft was needed) or excessive defects and uniformity excursions (soft pad selected where hard was required).<\/p>\r\n<p>This guide provides the definitive answer \u2014 not as a simple rule, but as a structured framework that maps pad hardness to process requirements, film type, node, and defect budget. If you want to first understand how pad hardness affects material removal at a mechanistic level, see: <a class=\"jz-link-chip\" href=\"https:\/\/jeez-semicon.com\/de\/blog\/How-CMP-Polishing-Pads-Work\/\" target=\"_blank\" rel=\"noopener\">How CMP Polishing Pads Work<\/a>. For a broader overview of pad material classes beyond just hardness, see: <a class=\"jz-link-chip\" href=\"https:\/\/jeez-semicon.com\/de\/blog\/CMP-Pad-Materials-Polyurethane-vs-Other-Options\/\" target=\"_blank\" rel=\"noopener\">CMP Pad Materials: Polyurethane vs Other Options<\/a>.<\/p>\r\n<div class=\"jz-stats\">\r\n<div class=\"jz-stat\">\r\n<div class=\"jz-stat-num\">55\u201365<\/div>\r\n<div class=\"jz-stat-label\">Shore D hardness range of production hard pads (IC1000-type)<\/div>\r\n<\/div>\r\n<div class=\"jz-stat\">\r\n<div class=\"jz-stat-num\">28\u201345<\/div>\r\n<div class=\"jz-stat-label\">Shore D hardness range of soft CMP pads \/ subpads<\/div>\r\n<\/div>\r\n<div class=\"jz-stat\">\r\n<div class=\"jz-stat-num\">&lt;1%<\/div>\r\n<div class=\"jz-stat-label\">WIWNU (1\u03c3) target for Cu BEOL CMP at 7 nm and below<\/div>\r\n<\/div>\r\n<div class=\"jz-stat\">\r\n<div class=\"jz-stat-num\">2\u20133\u00d7<\/div>\r\n<div class=\"jz-stat-label\">Planarization efficiency advantage of hard pad over soft on identical incoming topography<\/div>\r\n<\/div>\r\n<\/div>\r\n<!-- \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 SECTION 1 \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 -->\r\n<h2 id=\"core-tradeoff\">1. The Core Trade-off: Planarization Efficiency vs. Within-Wafer Uniformity<\/h2>\r\n<p>The hard-vs-soft pad decision is governed by a single, inescapable physical trade-off: <strong>a harder pad is better at removing topographic features, but a softer pad is better at distributing removal uniformly across the wafer.<\/strong> These two objectives are in direct tension, and no pad can simultaneously maximize both. Understanding why \u2014 at the mechanical level \u2014 is the foundation of informed pad selection.<\/p>\r\n<h3>Why Hard Pads Plannarize Better<\/h3>\r\n<p>A hard pad (Shore D 55\u201365) has a high Young&#8217;s modulus, typically 200\u2013500 MPa. When pressed against a wafer surface with raised topographic features (hills created by underlying device structures), the rigid pad surface bridges over the valleys and concentrates contact force on the hilltops. This selective loading means that material removal preferentially occurs at the high points, progressively reducing step height and approaching global planarization. The phenomenon is analogous to a stiff ruler pressed across a bumpy surface \u2014 only the bumps touch the ruler.<\/p>\r\n<h3>Why Soft Pads Are More Uniform<\/h3>\r\n<p>A soft pad (Shore D 28\u201345) has a low Young&#8217;s modulus, typically 10\u201360 MPa. Under the same applied down-force, it deforms and conforms to the wafer surface topography rather than bridging over it. Contact force is distributed more evenly across both hills and valleys. The result is more uniform material removal \u2014 but at the cost of lower step-height reduction. Additionally, at the wafer scale, a soft pad conforms to the bow and warp of a 300 mm production wafer (commonly 20\u201380 \u00b5m peak-to-valley), reducing the edge-to-center pressure differential that causes non-uniform removal profiles with hard pads.<\/p>\r\n<div class=\"jz-callout info\">\r\n<div class=\"jz-callout-icon\">\u2139\ufe0f<\/div>\r\n<div class=\"jz-callout-body\"><strong>The Planarization Length Scale<\/strong> The hard-pad planarization advantage operates over a specific lateral length scale \u2014 approximately 1\u201310 mm \u2014 corresponding to the distance over which a hard pad can bridge across topographic features without conforming. Features smaller than this length scale are effectively &#8220;invisible&#8221; to the hard pad&#8217;s bridging mechanism and are removed uniformly regardless of their height. Features larger than the bridging length require multiple CMP cycles or alternative planarization approaches. Understanding this length scale for your specific hard pad and process conditions is essential for predicting planarization efficiency.<\/div>\r\n<\/div>\r\n<!-- \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 SECTION 2 \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 -->\r\n<h2 id=\"hard-pad-deep\">2. Hard Pads: Properties, Strengths, and Limitations<\/h2>\r\n<div class=\"jz-vs-wrap\">\r\n<div class=\"jz-vs-col jz-vs-col-hard\">\r\n<div class=\"jz-vs-label jz-vs-label-hard\">HARD PAD \u2014 Strengths<\/div>\r\n<div class=\"jz-vs-title jz-vs-title-hard\">Shore D 55\u201365<\/div>\r\n<ul class=\"jz-vs-list pros\">\r\n<li>High planarization efficiency \u2014 step-height reduction &gt;80% in one pass typical<\/li>\r\n<li>Stable, predictable removal rate over extended conditioning campaigns<\/li>\r\n<li>Better selectivity between high and low features \u2014 ideal for damascene steps<\/li>\r\n<li>Stiffer surface resists asperity flattening \u2014 maintains MRR over longer pad life<\/li>\r\n<li>Higher Preston coefficient Kp \u2014 higher throughput per pressure unit<\/li>\r\n<li>Better compatibility with high-selectivity ceria slurries for STI oxide CMP<\/li>\r\n<\/ul>\r\n<\/div>\r\n<div class=\"jz-vs-col jz-vs-col-soft\">\r\n<div class=\"jz-vs-label jz-vs-label-soft\">HARD PAD \u2014 Limitations<\/div>\r\n<div class=\"jz-vs-title jz-vs-title-soft\">Watch out for:<\/div>\r\n<ul class=\"jz-vs-list cons\">\r\n<li>Higher scratch density \u2014 stiff asperities transmit more force to abrasive particles<\/li>\r\n<li>Poor edge-center uniformity on bowed or warped wafers<\/li>\r\n<li>Risk of low-k dielectric delamination under high shear forces<\/li>\r\n<li>Higher sensitivity to pressure non-uniformity from retaining ring geometry<\/li>\r\n<li>Requires more aggressive conditioning to prevent glazing \u2014 higher conditioner wear<\/li>\r\n<li>Not suitable for ultra-thin films where over-polishing risk is high<\/li>\r\n<\/ul>\r\n<\/div>\r\n<\/div>\r\n<h3>Typical Hard Pad Specifications (Production Grade)<\/h3>\r\n<div class=\"jz-table-wrap\">\r\n<table class=\"jz-table\">\r\n<thead>\r\n<tr>\r\n<th>Parameter<\/th>\r\n<th>Specification Range<\/th>\r\n<th>Pr\u00fcfverfahren<\/th>\r\n<\/tr>\r\n<\/thead>\r\n<tbody>\r\n<tr>\r\n<td>Shore D hardness<\/td>\r\n<td>55\u201365 (\u00b12 within lot)<\/td>\r\n<td>ASTM D2240, 5-point wafer map<\/td>\r\n<\/tr>\r\n<tr>\r\n<td>Compressibility<\/td>\r\n<td>0.5\u20132.5%<\/td>\r\n<td>% thickness change at 25 kPa, 60 s<\/td>\r\n<\/tr>\r\n<tr>\r\n<td>Elastic recovery<\/td>\r\n<td>&gt;70%<\/td>\r\n<td>% recovery 60 s after load removal<\/td>\r\n<\/tr>\r\n<tr>\r\n<td>Mean pore diameter<\/td>\r\n<td>20\u201345 \u00b5m<\/td>\r\n<td>Optical cross-section, image analysis<\/td>\r\n<\/tr>\r\n<tr>\r\n<td>Pore size CV (%)<\/td>\r\n<td>&lt;18%<\/td>\r\n<td>Standard deviation \/ mean \u00d7 100<\/td>\r\n<\/tr>\r\n<tr>\r\n<td>Pad thickness<\/td>\r\n<td>2.0\u20132.5 mm (\u00b10.05 mm)<\/td>\r\n<td>5-point contact gauge<\/td>\r\n<\/tr>\r\n<tr>\r\n<td>Groove depth<\/td>\r\n<td>0,5-0,8 mm<\/td>\r\n<td>Profilometer cross-section<\/td>\r\n<\/tr>\r\n<tr>\r\n<td>Groove width<\/td>\r\n<td>0.3\u20130.6 mm<\/td>\r\n<td>Profilometer cross-section<\/td>\r\n<\/tr>\r\n<\/tbody>\r\n<\/table>\r\n<\/div>\r\n<!-- \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 SECTION 3 \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 -->\r\n<h2 id=\"soft-pad-deep\">3. Soft Pads: Properties, Strengths, and Limitations<\/h2>\r\n<div class=\"jz-vs-wrap\">\r\n<div class=\"jz-vs-col jz-vs-col-hard\">\r\n<div class=\"jz-vs-label jz-vs-label-hard\">SOFT PAD \u2014 Strengths<\/div>\r\n<div class=\"jz-vs-title jz-vs-title-hard\">Shore D 28\u201345<\/div>\r\n<ul class=\"jz-vs-list pros\">\r\n<li>Superior within-wafer uniformity \u2014 conforms to wafer bow and warp<\/li>\r\n<li>Low shear force on fragile films \u2014 safe for low-k dielectrics (k &lt; 2.5)<\/li>\r\n<li>Lower scratch and micro-scratch density \u2014 critical for Cu and barrier CMP<\/li>\r\n<li>Excellent for final surface finishing steps requiring Ra &lt; 0.5 nm<\/li>\r\n<li>Better results on 300 mm wafers with high bow\/warp from stress films<\/li>\r\n<li>Forgiving to minor slurry flow variations and recipe perturbations<\/li>\r\n<\/ul>\r\n<\/div>\r\n<div class=\"jz-vs-col jz-vs-col-soft\">\r\n<div class=\"jz-vs-label jz-vs-label-soft\">SOFT PAD \u2014 Limitations<\/div>\r\n<div class=\"jz-vs-title jz-vs-title-soft\">Watch out for:<\/div>\r\n<ul class=\"jz-vs-list cons\">\r\n<li>Low planarization efficiency \u2014 poor step-height reduction on rough incoming surfaces<\/li>\r\n<li>Faster MRR decay as pad glazes \u2014 requires more frequent conditioning<\/li>\r\n<li>Lower Tg \u2014 more susceptible to thermal softening at elevated process temperatures<\/li>\r\n<li>Higher compressibility variation wafer-to-wafer in early pad life<\/li>\r\n<li>Not suitable for STI, PMD, or any step requiring &gt;50% step-height reduction<\/li>\r\n<li>Sensitive to conditioning parameters \u2014 over-conditioning dramatically increases MRR<\/li>\r\n<\/ul>\r\n<\/div>\r\n<\/div>\r\n<!-- \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 SECTION 4 \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 -->\r\n<h2 id=\"head-to-head\">4. Head-to-Head Comparison: Every Key Metric<\/h2>\r\n<div class=\"jz-table-wrap\">\r\n<table class=\"jz-table\">\r\n<thead>\r\n<tr>\r\n<th>Metric<\/th>\r\n<th class=\"col-hard\">Hard Pad (Shore D 55\u201365)<\/th>\r\n<th class=\"col-soft\">Soft Pad (Shore D 28\u201345)<\/th>\r\n<th>Winner<\/th>\r\n<\/tr>\r\n<\/thead>\r\n<tbody>\r\n<tr>\r\n<td><strong>Planarization efficiency<\/strong><\/td>\r\n<td class=\"win\">High \u2014 bridges topography, removes selectively from high points<\/td>\r\n<td class=\"lose\">Low \u2014 conforms to topography, removes uniformly<\/td>\r\n<td class=\"win\">Hard<\/td>\r\n<\/tr>\r\n<tr>\r\n<td><strong>Within-wafer uniformity (WIWNU)<\/strong><\/td>\r\n<td class=\"lose\">Moderate \u2014 sensitive to wafer bow and retaining ring geometry<\/td>\r\n<td class=\"win\">High \u2014 conforms to wafer-scale shape variations<\/td>\r\n<td class=\"win\">Soft<\/td>\r\n<\/tr>\r\n<tr>\r\n<td><strong>Scratch defect density<\/strong><\/td>\r\n<td class=\"lose\">Higher \u2014 stiff asperities transmit higher local stress<\/td>\r\n<td class=\"win\">Lower \u2014 compliant asperities reduce peak contact stress<\/td>\r\n<td class=\"win\">Soft<\/td>\r\n<\/tr>\r\n<tr>\r\n<td><strong>Low-k film safety<\/strong><\/td>\r\n<td class=\"lose\">Risk of delamination at standard pressures<\/td>\r\n<td class=\"win\">Safe at standard pressures (&lt;3 psi)<\/td>\r\n<td class=\"win\">Soft<\/td>\r\n<\/tr>\r\n<tr>\r\n<td><strong>Material removal rate<\/strong><\/td>\r\n<td class=\"win\">Higher MRR at same P \u00d7 V \u2014 better throughput<\/td>\r\n<td class=\"lose\">Lower MRR \u2014 longer polishing times needed<\/td>\r\n<td class=\"win\">Hard<\/td>\r\n<\/tr>\r\n<tr>\r\n<td><strong>Pad lifetime (wafers\/pad)<\/strong><\/td>\r\n<td class=\"win\">500\u20132,000 wafers \u2014 stiffer surface resists wear<\/td>\r\n<td class=\"mid\">300\u20131,000 wafers \u2014 softer surface glazes faster<\/td>\r\n<td class=\"win\">Hard<\/td>\r\n<\/tr>\r\n<tr>\r\n<td><strong>Slurry utilization<\/strong><\/td>\r\n<td class=\"mid\">Moderate \u2014 closed-cell pores provide good retention<\/td>\r\n<td class=\"win\">High \u2014 open-cell structure absorbs and releases slurry efficiently<\/td>\r\n<td class=\"win\">Soft<\/td>\r\n<\/tr>\r\n<tr>\r\n<td><strong>Conditioning sensitivity<\/strong><\/td>\r\n<td class=\"win\">Lower \u2014 MRR change per unit conditioner force is smaller<\/td>\r\n<td class=\"lose\">Higher \u2014 small conditioning changes cause significant MRR shifts<\/td>\r\n<td class=\"win\">Hard<\/td>\r\n<\/tr>\r\n<tr>\r\n<td><strong>Thermal stability<\/strong><\/td>\r\n<td class=\"win\">Higher Tg (90\u2013120\u00b0C) \u2014 better for high-pressure processes<\/td>\r\n<td class=\"lose\">Lower Tg (55\u201380\u00b0C) \u2014 softens faster under thermal load<\/td>\r\n<td class=\"win\">Hard<\/td>\r\n<\/tr>\r\n<tr>\r\n<td><strong>Cost (unit price)<\/strong><\/td>\r\n<td class=\"mid\">Baseline (1.0\u00d7)<\/td>\r\n<td class=\"win\">Slightly lower (0.8\u20131.1\u00d7) \u2014 depends on formulation<\/td>\r\n<td class=\"mid\">\u00c4hnlich<\/td>\r\n<\/tr>\r\n<\/tbody>\r\n<\/table>\r\n<\/div>\r\n<!-- \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 SECTION 5 \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 -->\r\n<h2 id=\"application-map\">5. Application-by-Application Selection Map<\/h2>\r\n<p>The following application map provides pad hardness recommendations for the most common CMP steps in advanced semiconductor manufacturing. Each recommendation is grounded in the process physics described above and reflects April 2026 fab best practice. For a broader view of how CMP pads are used across the full IC process flow, see: <a class=\"jz-link-chip\" href=\"https:\/\/jeez-semicon.com\/de\/blog\/Semiconductor-CMP-Polishing-Pads\/\" target=\"_blank\" rel=\"noopener\">Semiconductor CMP Polishing Pads<\/a>.<\/p>\r\n<div class=\"jz-app-grid\">\r\n<div class=\"jz-app-card\">\r\n<div class=\"jz-app-card-head\"><span class=\"jz-app-badge jz-app-badge-hard\">HARD PAD<\/span> <span class=\"jz-app-title\">STI Oxide CMP<\/span><\/div>\r\n<div class=\"jz-app-desc\">Shallow trench isolation requires aggressive step-height removal (1,000\u20133,000 \u00c5 of incoming oxide step). Hard pad with ceria-based slurry achieves &gt;90% step-height reduction in a single polish step. Selectivity to Si\u2083N\u2084 stop layer is critical \u2014 hard pad helps maintain mechanical selectivity.<\/div>\r\n<\/div>\r\n<div class=\"jz-app-card\">\r\n<div class=\"jz-app-card-head\"><span class=\"jz-app-badge jz-app-badge-hard\">HARD PAD<\/span> <span class=\"jz-app-title\">Pre-Metal Dielectric (PMD)<\/span><\/div>\r\n<div class=\"jz-app-desc\">BPSG or USG planarization before the first metal level. High incoming topography from gate and contact structures demands hard-pad planarization efficiency. The target film is oxide \u2014 hard pads with silica or ceria slurry are the standard approach.<\/div>\r\n<\/div>\r\n<div class=\"jz-app-card\">\r\n<div class=\"jz-app-card-head\"><span class=\"jz-app-badge jz-app-badge-hard\">HARD PAD<\/span> <span class=\"jz-app-title\">W Plug CMP<\/span><\/div>\r\n<div class=\"jz-app-desc\">Tungsten chemical mechanical polishing removes excess W deposited in contact\/via holes, stopping on the TiN\/TaN barrier layer. Hard pad required for planarization and to maintain the high down-force needed for W&#8217;s moderate hardness. High selectivity to the barrier layer is critical.<\/div>\r\n<\/div>\r\n<div class=\"jz-app-card\">\r\n<div class=\"jz-app-card-head\"><span class=\"jz-app-badge jz-app-badge-soft\">SOFT PAD<\/span> <span class=\"jz-app-title\">Cu Bulk Removal (BEOL Step 1)<\/span><\/div>\r\n<div class=\"jz-app-desc\">The first CMP step in Cu damascene removes the bulk of the overburden copper deposited by electroplating. Moderate hardness soft pad (Shore D 38\u201345) balances reasonable removal rate with protection of the underlying low-k dielectric from delamination under shear.<\/div>\r\n<\/div>\r\n<div class=\"jz-app-card\">\r\n<div class=\"jz-app-card-head\"><span class=\"jz-app-badge jz-app-badge-soft\">SOFT PAD<\/span> <span class=\"jz-app-title\">Cu \/ Barrier Buff (BEOL Step 2)<\/span><\/div>\r\n<div class=\"jz-app-desc\">Final clearing of barrier metal (Ta, TaN) and surface planarization after Cu bulk removal. Very soft pad (Shore D 28\u201338) minimizes scratch generation during this defect-critical finishing step. Post-CMP surface roughness Ra &lt; 0.5 nm is the target.<\/div>\r\n<\/div>\r\n<div class=\"jz-app-card\">\r\n<div class=\"jz-app-card-head\"><span class=\"jz-app-badge jz-app-badge-soft\">SOFT PAD<\/span> <span class=\"jz-app-title\">Low-k ILD Planarization<\/span><\/div>\r\n<div class=\"jz-app-desc\">Porous low-k dielectrics (k &lt; 2.5, porosity 20\u201350%) are mechanically fragile \u2014 Young&#8217;s modulus as low as 3\u20138 GPa. Only soft pads at reduced pressure (&lt;2 psi) can polish these films without crack initiation. Stacked pad configurations with a very soft subpad are standard.<\/div>\r\n<\/div>\r\n<div class=\"jz-app-card\">\r\n<div class=\"jz-app-card-head\"><span class=\"jz-app-badge jz-app-badge-stack\">STACKED<\/span> <span class=\"jz-app-title\">300 mm Advanced Node Oxide<\/span><\/div>\r\n<div class=\"jz-app-desc\">At 7 nm and below, incoming wafer bow exceeds 100 \u00b5m. A stacked configuration (hard IC1000-type top pad + soft Suba-type subpad) provides hard-pad planarization efficiency while the compliant subpad corrects for wafer bow. Industry-standard configuration at leading fabs.<\/div>\r\n<\/div>\r\n<div class=\"jz-app-card\">\r\n<div class=\"jz-app-card-head\"><span class=\"jz-app-badge jz-app-badge-hard\">HARD \/ SPECIALTY<\/span> <span class=\"jz-app-title\">SiC \/ GaN Substrates<\/span><\/div>\r\n<div class=\"jz-app-desc\">Compound semiconductors require specialty hard pads with enhanced chemical resistance and thermal stability. Standard hard PU pads underperform on SiC (Mohs 9.5). See: <a style=\"color: #0090d4;\" href=\"https:\/\/jeez-semicon.com\/de\/blog\/SiC-CMP-Polishing-Pads-for-Third-Generation-Semiconductors\/\" target=\"_blank\" rel=\"noopener\">SiC-specific pad guide<\/a>.<\/div>\r\n<\/div>\r\n<\/div>\r\n<!-- \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 SECTION 6 \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 -->\r\n<h2 id=\"stacked-strategy\">6. The Stacked Pad Strategy: Getting the Best of Both<\/h2>\r\n<p>The most practically important development in CMP pad engineering over the past decade is the widespread adoption of stacked pad configurations \u2014 combining a hard polishing top pad with a compliant foam subpad \u2014 to simultaneously achieve planarization efficiency and within-wafer uniformity. This strategy directly addresses the hard-vs-soft trade-off by decoupling the two functions into separate layers.<\/p>\r\n<h3>How the Stack Works<\/h3>\r\n<p>In a stacked pad configuration, the hard polyurethane top pad (Shore D 55\u201365) provides the polishing surface. Its high Young&#8217;s modulus ensures that contact with the wafer surface is dominated by the asperity-level mechanics that deliver planarization efficiency. Beneath the top pad, a soft foam subpad (typically Shore A 30\u201355, 0.5\u20131.5 mm thick) is laminated directly to the platen. The subpad&#8217;s role is purely mechanical: its bulk compliance absorbs wafer-scale bow and warp, redistributing the contact force from the carrier head more evenly across the wafer surface. The subpad does not contact the slurry or the wafer directly.<\/p>\r\n<div class=\"jz-callout tip\">\r\n<div class=\"jz-callout-icon\">\ud83d\udca1<\/div>\r\n<div class=\"jz-callout-body\"><strong>Tuning the Stack: Subpad as a Process Knob<\/strong> The effective compressibility of the combined pad stack is primarily controlled by the subpad thickness and foam density. A thicker or softer subpad increases the stack&#8217;s macro-scale compliance, improving edge-center uniformity at the cost of some planarization efficiency. A thinner or harder subpad reduces compliance, shifting the balance back toward planarization performance. Process engineers at advanced fabs routinely fine-tune subpad hardness in 5\u201310 Shore A increments to optimize WIWNU profiles, treating the subpad as a variable process parameter rather than a fixed consumable.<\/div>\r\n<\/div>\r\n<h3>Stack Configuration Naming Conventions<\/h3>\r\n<div class=\"jz-table-wrap\">\r\n<table class=\"jz-table\">\r\n<thead>\r\n<tr>\r\n<th>Stack Type<\/th>\r\n<th>Top Pad<\/th>\r\n<th>Subpad<\/th>\r\n<th>Application Sweet Spot<\/th>\r\n<\/tr>\r\n<\/thead>\r\n<tbody>\r\n<tr>\r\n<td><strong>Hard \/ Hard<\/strong><\/td>\r\n<td>Shore D 60\u201365<\/td>\r\n<td>Shore D 45\u201355 (stiffer foam)<\/td>\r\n<td>Maximum planarization, mature node oxide \u2014 wafer bow not a concern<\/td>\r\n<\/tr>\r\n<tr>\r\n<td><strong>Hard \/ Soft (standard stack)<\/strong><\/td>\r\n<td>Shore D 55\u201362<\/td>\r\n<td>Shore A 35\u201350 (soft foam)<\/td>\r\n<td>300 mm advanced node oxide and W CMP \u2014 industry standard configuration<\/td>\r\n<\/tr>\r\n<tr>\r\n<td><strong>Medium \/ Soft<\/strong><\/td>\r\n<td>Shore D 45\u201355<\/td>\r\n<td>Shore A 25\u201340 (very soft foam)<\/td>\r\n<td>Cu bulk step \u2014 balance of MRR and uniformity, moderate low-k protection<\/td>\r\n<\/tr>\r\n<tr>\r\n<td><strong>Soft \/ Very Soft<\/strong><\/td>\r\n<td>Shore D 28\u201342<\/td>\r\n<td>Shore A 20\u201330 (ultra-soft foam)<\/td>\r\n<td>Ultra-thin low-k finishing, Cu barrier buff \u2014 maximum defect protection<\/td>\r\n<\/tr>\r\n<\/tbody>\r\n<\/table>\r\n<\/div>\r\n<!-- \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 SECTION 7 \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 -->\r\n<h2 id=\"decision-tree\">7. Decision Framework: Choosing the Right Pad Hardness<\/h2>\r\n<p>The following decision tree provides a systematic path from process step description to pad hardness recommendation. Work through the questions in order \u2014 the first applicable branching point gives the recommendation.<\/p>\r\n<div class=\"jz-tree\">\r\n<div class=\"jz-tree-row\">\r\n<div class=\"jz-tree-q\">Is the target film ultra-hard (SiC, GaN, sapphire, Mohs &gt; 8)?<\/div>\r\n<div class=\"jz-tree-yes\">Specialty hard pad or fixed-abrasive pad required. See SiC guide.<\/div>\r\n<div class=\"jz-tree-no\">Continue to next question.<\/div>\r\n<\/div>\r\n<div class=\"jz-tree-row\">\r\n<div class=\"jz-tree-q\">Is incoming step height &gt; 500 \u00c5 (significant topography to remove)?<\/div>\r\n<div class=\"jz-tree-yes\">Hard pad (Shore D 55\u201365). Planarization efficiency is the priority.<\/div>\r\n<div class=\"jz-tree-no\">Continue to next question.<\/div>\r\n<\/div>\r\n<div class=\"jz-tree-row\">\r\n<div class=\"jz-tree-q\">Is the target film a fragile low-k dielectric (k &lt; 2.8) or ultra-thin metal (&lt; 50 nm)?<\/div>\r\n<div class=\"jz-tree-yes\">Soft pad (Shore D 28\u201342) at reduced pressure (&lt; 2 psi). Shear protection is the priority.<\/div>\r\n<div class=\"jz-tree-no\">Continue to next question.<\/div>\r\n<\/div>\r\n<div class=\"jz-tree-row\">\r\n<div class=\"jz-tree-q\">Is within-wafer non-uniformity (WIWNU 1\u03c3) required below 1%?<\/div>\r\n<div class=\"jz-tree-yes\">Soft pad or stacked (hard top + soft subpad). Uniformity is the priority.<\/div>\r\n<div class=\"jz-tree-no\">Continue to next question.<\/div>\r\n<\/div>\r\n<div class=\"jz-tree-row\">\r\n<div class=\"jz-tree-q\">Is wafer bow or warp &gt; 50 \u00b5m (common in 300 mm stress-film wafers)?<\/div>\r\n<div class=\"jz-tree-yes\">Stacked pad configuration (hard top + soft subpad) to correct for bow-induced pressure non-uniformity.<\/div>\r\n<div class=\"jz-tree-no\">Hard pad (Shore D 55\u201360) is the safe default for standard oxide and metal CMP steps.<\/div>\r\n<\/div>\r\n<\/div>\r\n<!-- \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 SECTION 8 \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 -->\r\n<h2 id=\"qualification\">8. Qualifying a New Pad Hardness in Production<\/h2>\r\n<p>Switching pad hardness \u2014 even within the same product family \u2014 is a significant process change that requires structured qualification. A change in Shore D hardness of even 5 points can shift the Preston coefficient by 8\u201315%, requiring recipe pressure adjustments. Here is the standard qualification protocol:<\/p>\r\n<div class=\"jz-steps\">\r\n<div class=\"jz-step\">\r\n<div class=\"jz-step-num\">1<\/div>\r\n<div class=\"jz-step-body\">\r\n<h4>Establish Baseline Metrics on Qualified Pad<\/h4>\r\n<p>Run a minimum of 3 qualification lots (25 wafers each) on the currently qualified pad at the locked production recipe. Record mean removal rate, WIWNU (1\u03c3), post-CMP scratch density (from KLA\/Hitachi inspection), and electrical test results (if applicable). These become the acceptance criteria for the new hardness.<\/p>\r\n<\/div>\r\n<\/div>\r\n<div class=\"jz-step\">\r\n<div class=\"jz-step-num\">2<\/div>\r\n<div class=\"jz-step-body\">\r\n<h4>Run Initial Characterization Splits<\/h4>\r\n<p>Polish a minimum of 50 monitor wafers on the new-hardness pad at the existing production recipe parameters. Do not adjust the recipe yet. Compare MRR (target: within \u00b115% of baseline), WIWNU (target: within \u00b10.5% 1\u03c3), and scratch density (target: within \u00b120%). Expect MRR to shift \u2014 the Preston coefficient changes with hardness. Recipe adjustment will be needed.<\/p>\r\n<\/div>\r\n<\/div>\r\n<div class=\"jz-step\">\r\n<div class=\"jz-step-num\">3<\/div>\r\n<div class=\"jz-step-body\">\r\n<h4>Adjust Recipe to Match Baseline MRR<\/h4>\r\n<p>If switching to a harder pad (MRR increased), reduce down-force pressure proportionally. If switching to a softer pad (MRR decreased), increase pressure. Use the Preston equation (MRR = Kp \u00d7 P \u00d7 V) as a first-order guide \u2014 the Kp of the new pad relative to the baseline can be estimated from the initial characterization data. Re-run 3 lots at the adjusted recipe to confirm MRR within \u00b18% of baseline.<\/p>\r\n<\/div>\r\n<\/div>\r\n<div class=\"jz-step\">\r\n<div class=\"jz-step-num\">4<\/div>\r\n<div class=\"jz-step-body\">\r\n<h4>Validate Conditioning Protocol<\/h4>\r\n<p>Pad conditioning parameters (conditioner down-force, sweep speed, in-situ vs. ex-situ ratio) optimized for the original hardness may need adjustment. Harder pads require more aggressive conditioning to prevent glazing; softer pads are more sensitive to over-conditioning. Optimize the conditioning protocol independently before committing to production qualification lots.<\/p>\r\n<\/div>\r\n<\/div>\r\n<div class=\"jz-step\">\r\n<div class=\"jz-step-num\">5<\/div>\r\n<div class=\"jz-step-body\">\r\n<h4>Run Full Qualification Lot and Engineering Sign-Off<\/h4>\r\n<p>Run 3 full-size production lots (25 wafers each) at the optimized recipe. All metrics must meet acceptance criteria. Obtain engineering and process owner sign-off. Update the process specification (process spec) with the new pad hardness, recipe parameters, and conditioning protocol before any production release.<\/p>\r\n<\/div>\r\n<\/div>\r\n<\/div>\r\n<p>For detailed guidance on pad conditioning protocols \u2014 which differ between hard and soft pad types \u2014 see: <a class=\"jz-link-chip\" href=\"https:\/\/jeez-semicon.com\/de\/blog\/CMP-Pad-Conditioning-and-Lifespan-Management\/\" target=\"_blank\" rel=\"noopener\">CMP Pad Conditioning and Lifespan Management<\/a>. For the relationship between pad hardness and material removal rate at a quantitative level, see: <a class=\"jz-link-chip\" href=\"https:\/\/jeez-semicon.com\/de\/blog\/CMP-Material-Removal-Rate-and-Pad-Parameters\/\" target=\"_blank\" rel=\"noopener\">CMP Material Removal Rate and Pad Parameters<\/a>.<\/p>\r\n<!-- \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 SECTION 9 \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 -->\r\n<h2 id=\"jizhi-range\">9. Jizhi&#8217;s Hard and Soft Pad Product Range<\/h2>\r\n<p>Jizhi Electronic Technology manufactures both hard and soft CMP polishing pads using proprietary polyurethane formulations developed through in-house R&amp;D. Our product range is engineered to provide qualified alternatives to IC1000-type hard pads and Politex \/ Suba-type soft pads, with full process characterization data provided for each product.<\/p>\r\n<div class=\"jz-table-wrap\">\r\n<table class=\"jz-table\">\r\n<thead>\r\n<tr>\r\n<th>Product Series<\/th>\r\n<th>Pad Type<\/th>\r\n<th>Shore D<\/th>\r\n<th>Primary Application<\/th>\r\n<th>Verf\u00fcgbarkeit<\/th>\r\n<\/tr>\r\n<\/thead>\r\n<tbody>\r\n<tr>\r\n<td><strong>JZ-H60 Series<\/strong><\/td>\r\n<td>Hard polyurethane<\/td>\r\n<td>58\u201362<\/td>\r\n<td>Oxide ILD, STI, PMD, W plug \u2014 IC1000 equivalent<\/td>\r\n<td>In stock<\/td>\r\n<\/tr>\r\n<tr>\r\n<td><strong>JZ-H65 Series<\/strong><\/td>\r\n<td>Hard polyurethane (high hardness)<\/td>\r\n<td>63\u201367<\/td>\r\n<td>High-topography oxide CMP, aggressive step-height applications<\/td>\r\n<td>In stock<\/td>\r\n<\/tr>\r\n<tr>\r\n<td><strong>JZ-S38 Series<\/strong><\/td>\r\n<td>Soft polyurethane subpad<\/td>\r\n<td>35\u201342<\/td>\r\n<td>Cu bulk removal (BEOL Step 1), stacked pad subpad<\/td>\r\n<td>In stock<\/td>\r\n<\/tr>\r\n<tr>\r\n<td><strong>JZ-S28 Series<\/strong><\/td>\r\n<td>Very soft polyurethane<\/td>\r\n<td>26\u201332<\/td>\r\n<td>Cu \/ barrier buff (BEOL Step 2), ultra-thin low-k finishing<\/td>\r\n<td>In stock<\/td>\r\n<\/tr>\r\n<tr>\r\n<td><strong>JZ-SiC Series<\/strong><\/td>\r\n<td>Specialty hard (SiC-optimized)<\/td>\r\n<td>60\u201368<\/td>\r\n<td>SiC and GaN substrate CMP, 3rd-generation semiconductors<\/td>\r\n<td>In stock \/ custom<\/td>\r\n<\/tr>\r\n<tr>\r\n<td><strong>JZ-Custom OEM<\/strong><\/td>\r\n<td>Customer-specified<\/td>\r\n<td>Any range<\/td>\r\n<td>Custom hardness, groove, and formulation per customer spec<\/td>\r\n<td>3\u20136 week lead time<\/td>\r\n<\/tr>\r\n<\/tbody>\r\n<\/table>\r\n<\/div>\r\n<div class=\"jz-callout cta\">\r\n<div class=\"jz-callout-icon\">\ud83c\udfed<\/div>\r\n<div class=\"jz-callout-body\"><strong>Request Process Characterization Data<\/strong> Every Jizhi CMP pad series comes with a process characterization data package including: Shore D hardness map, pore size distribution, baseline MRR at reference recipe conditions, and WIWNU data. Contact our application engineering team to receive data for your specific process step and tool configuration. <a href=\"https:\/\/jeez-semicon.com\/de\/contact\/\" target=\"_blank\" rel=\"noopener\">Request a data package \u2192<\/a><\/div>\r\n<\/div>\r\n<!-- \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 FAQ \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 -->\r\n<h2>10. Frequently Asked Questions<\/h2>\r\n<div class=\"jz-faq\">\r\n<div class=\"jz-faq-item\">\r\n<div class=\"jz-faq-q\">Can I use a hard pad for Cu CMP if I reduce the down-force pressure?<\/div>\r\n<div class=\"jz-faq-a\">Reducing pressure to compensate for a hard pad in Cu CMP partially addresses the scratch and shear-force problem, but it does not solve the fundamental issue: a hard pad&#8217;s stiff asperities generate higher local contact stress per asperity contact than a soft pad at any given nominal pressure. Additionally, very low pressures can push the process into the hydrodynamic lubrication regime (Stribeck curve), causing unstable MRR and poor uniformity. For Cu BEOL, soft pads at standard pressure are strongly preferred over hard pads at reduced pressure \u2014 the physics favor the soft pad, not the recipe workaround.<\/div>\r\n<\/div>\r\n<div class=\"jz-faq-item\">\r\n<div class=\"jz-faq-q\">Is a softer pad always safer for defect density?<\/div>\r\n<div class=\"jz-faq-a\">Generally yes in terms of scratch defects, but not universally. Very soft pads can generate particle contamination from their open-cell foam structure if the foam sheds debris during conditioning or polishing. Additionally, soft pads used with incompatible slurry chemistry (e.g., highly oxidizing slurry on a low-Tg soft PU) can degrade faster, generating polymer debris that causes contamination defects. Defect density depends on the full pad-slurry-conditioning system, not pad hardness alone.<\/div>\r\n<\/div>\r\n<div class=\"jz-faq-item\">\r\n<div class=\"jz-faq-q\">What Shore D value is considered &#8220;medium hardness&#8221; in CMP pads?<\/div>\r\n<div class=\"jz-faq-a\">The industry does not have a formal &#8220;medium hardness&#8221; category, but pads in the Shore D 46\u201354 range are frequently described as medium hardness. These pads are sometimes used as a compromise when a single pad must serve both oxide-like and Cu-like steps in a simplified process flow. They deliver moderate planarization efficiency and moderate scratch performance \u2014 neither as good as a dedicated hard pad nor as safe as a dedicated soft pad. Most leading fabs avoid this compromise and maintain separate hard and soft pad SKUs for each process step.<\/div>\r\n<\/div>\r\n<div class=\"jz-faq-item\">\r\n<div class=\"jz-faq-q\">How does pad hardness interact with slurry particle size for defect control?<\/div>\r\n<div class=\"jz-faq-a\">Pad hardness and slurry particle size interact multiplicatively for scratch defect generation. A hard pad with large particles (d50 &gt; 150 nm) creates the highest scratch risk. A soft pad with small particles (d50 &lt; 80 nm) creates the lowest. The combination of pad hardness and particle size determines the effective contact stress at the three-body interface \u2014 both parameters must be optimized together. For Cu BEOL defect-critical steps, soft pads are paired with ultra-fine silica slurry (d50 30\u201360 nm). For oxide CMP where throughput matters more than defects, hard pads can use coarser ceria particles (d50 100\u2013200 nm) without unacceptable scratch generation on the less defect-sensitive ILD films.<\/div>\r\n<\/div>\r\n<div class=\"jz-faq-item\">\r\n<div class=\"jz-faq-q\">Does Jizhi offer pad samples for process evaluation before committing to volume purchase?<\/div>\r\n<div class=\"jz-faq-a\">Yes. Jizhi Electronic Technology provides evaluation samples \u2014 typically 3\u20135 pads \u2014 for qualified customers conducting process characterization and pad qualification at their facility. Samples come with full characterization data packages. To request evaluation samples for your specific application (hard, soft, SiC-specific, or custom), please <a href=\"https:\/\/jeez-semicon.com\/de\/contact\/\" target=\"_blank\" rel=\"noopener\">contact our application engineering team<\/a> with your pad size, target application, and CMP tool type.<\/div>\r\n<\/div>\r\n<\/div>\r\n<!-- Related Articles -->\r\n<div class=\"jz-related\">\r\n<div class=\"jz-related-title\">\ud83d\udcda Continue Reading \u2014 CMP Pad Deep Dives<\/div>\r\n<div class=\"jz-related-grid\">\r\n<div class=\"jz-related-item\">\r\n<div class=\"jz-related-cat\">PILLAR \u2014 COMPLETE GUIDE<\/div>\r\n<a href=\"https:\/\/jeez-semicon.com\/de\/blog\/CMP-Polishing-Pads-The-Complete-Guide\/\" target=\"_blank\" rel=\"noopener\">CMP Polishing Pads: The Complete Guide<\/a><\/div>\r\n<div class=\"jz-related-item\">\r\n<div class=\"jz-related-cat\">FUNDAMENTALS<\/div>\r\n<a href=\"https:\/\/jeez-semicon.com\/de\/blog\/What-Is-a-CMP-Polishing-Pad-The-Ultimate-Guide\/\" target=\"_blank\" rel=\"noopener\">What Is a CMP Polishing Pad? The Ultimate Guide<\/a><\/div>\r\n<div class=\"jz-related-item\">\r\n<div class=\"jz-related-cat\">FUNDAMENTALS<\/div>\r\n<a href=\"https:\/\/jeez-semicon.com\/de\/blog\/How-CMP-Polishing-Pads-Work\/\" target=\"_blank\" rel=\"noopener\">How CMP Polishing Pads Work<\/a><\/div>\r\n<div class=\"jz-related-item\">\r\n<div class=\"jz-related-cat\">MATERIALS<\/div>\r\n<a href=\"https:\/\/jeez-semicon.com\/de\/blog\/CMP-Pad-Materials-Polyurethane-vs-Other-Options\/\" target=\"_blank\" rel=\"noopener\">CMP Pad Materials: Polyurethane vs Other Options<\/a><\/div>\r\n<div class=\"jz-related-item\">\r\n<div class=\"jz-related-cat\">ENGINEERING<\/div>\r\n<a href=\"https:\/\/jeez-semicon.com\/de\/blog\/CMP-Pad-Groove-Design-and-Slurry-Distribution\/\" target=\"_blank\" rel=\"noopener\">CMP Pad Groove Design and Slurry Distribution<\/a><\/div>\r\n<div class=\"jz-related-item\">\r\n<div class=\"jz-related-cat\">APPLICATIONS<\/div>\r\n<a href=\"https:\/\/jeez-semicon.com\/de\/blog\/Semiconductor-CMP-Polishing-Pads\/\" target=\"_blank\" rel=\"noopener\">Semiconductor CMP Polishing Pads<\/a><\/div>\r\n<div class=\"jz-related-item\">\r\n<div class=\"jz-related-cat\">APPLICATIONS<\/div>\r\n<a href=\"https:\/\/jeez-semicon.com\/de\/blog\/SiC-CMP-Polishing-Pads-for-Third-Generation-Semiconductors\/\" target=\"_blank\" rel=\"noopener\">SiC CMP Polishing Pads for Third-Generation Semiconductors<\/a><\/div>\r\n<div class=\"jz-related-item\">\r\n<div class=\"jz-related-cat\">OPERATIONS<\/div>\r\n<a href=\"https:\/\/jeez-semicon.com\/de\/blog\/CMP-Pad-Conditioning-and-Lifespan-Management\/\" target=\"_blank\" rel=\"noopener\">CMP Pad Conditioning and Lifespan Management<\/a><\/div>\r\n<div class=\"jz-related-item\">\r\n<div class=\"jz-related-cat\">PROCESS<\/div>\r\n<a href=\"https:\/\/jeez-semicon.com\/de\/blog\/CMP-Material-Removal-Rate-and-Pad-Parameters\/\" target=\"_blank\" rel=\"noopener\">CMP Material Removal Rate and Pad Parameters<\/a><\/div>\r\n<div class=\"jz-related-item\">\r\n<div class=\"jz-related-cat\">QUALITY<\/div>\r\n<a href=\"https:\/\/jeez-semicon.com\/de\/blog\/CMP-Pad-Defect-Control-Scratches-and-Uniformity\/\" target=\"_blank\" rel=\"noopener\">CMP Pad Defect Control: Scratches and Uniformity<\/a><\/div>\r\n<div class=\"jz-related-item\">\r\n<div class=\"jz-related-cat\">SOURCING<\/div>\r\n<a href=\"https:\/\/jeez-semicon.com\/de\/blog\/CMP-Polishing-Pad-Brands-Comparison\/\" target=\"_blank\" rel=\"noopener\">CMP Polishing Pad Brands Comparison<\/a><\/div>\r\n<div class=\"jz-related-item\">\r\n<div class=\"jz-related-cat\">PROCUREMENT<\/div>\r\n<a href=\"https:\/\/jeez-semicon.com\/de\/blog\/CMP-Polishing-Pad-Price-Factors-and-Buying-Guide\/\" target=\"_blank\" rel=\"noopener\">CMP Polishing Pad Price Factors and Buying Guide<\/a><\/div>\r\n<\/div>\r\n<\/div>\r\n<!-- CTA -->\r\n<div class=\"jz-cta-banner\">\r\n<h2>Hard Pad, Soft Pad, or Stacked \u2014 We Have Your Process Covered<\/h2>\r\n<p>Jizhi Electronic Technology supplies the full hardness spectrum of CMP polishing pads, from high-planarization-efficiency hard pads for oxide and tungsten CMP to ultra-soft subpads for Cu BEOL and low-k protection. Process characterization data and application engineering support included.<\/p>\r\n<a class=\"jz-btn jz-btn-white\" href=\"https:\/\/jeez-semicon.com\/de\/semi-categories\/polishing-pad\/\" target=\"_blank\" rel=\"noopener\">Browse CMP Polishing Pads<\/a> <a class=\"jz-btn jz-btn-outline\" href=\"https:\/\/jeez-semicon.com\/de\/contact\/\" target=\"_blank\" rel=\"noopener\">Get a Pad Recommendation<\/a><\/div>\r\n<!--\r\n  \u2554\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\r\n  \u2551  SEO NOTES \u2014 Cluster 4\r\n  \u2560\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\r\n  \u2551  Title tag:  Hard vs. Soft CMP Polishing Pads: Selection Guide 2026 | Jizhi\r\n  \u2551  Meta desc:  Complete guide to choosing hard or soft CMP polishing pads \u2014\r\n  \u2551              planarization vs uniformity trade-off, application map, stacked\r\n  \u2551              pad strategy, and 5-step qualification protocol.\r\n  \u2551  Focus KW:   hard vs soft CMP polishing pad\r\n  \u2551  Secondary:  CMP pad hardness, Shore D CMP pad, stacked CMP pad,\r\n  \u2551              CMP pad selection, polyurethane CMP pad hardness\r\n  \u2551  Schema:     Article + FAQPage\r\n  \u2551  Intent:     Informational \/ Commercial investigation\r\n  \u255a\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\r\n--><\/div>\r\n<!-- .jz-art -->","protected":false},"excerpt":{"rendered":"<p>Back to CMP Polishing Pads: The Complete Guide Jizhi Electronic Technology \u2014 Selection Guide Series A rigorous, application-mapped guide to choosing between hard and soft CMP polishing pads \u2014 covering  &#8230;<\/p>","protected":false},"author":1,"featured_media":1809,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[9,59],"tags":[],"class_list":["post-1767","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-blog","category-industry"],"acf":[],"_links":{"self":[{"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/posts\/1767","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/comments?post=1767"}],"version-history":[{"count":4,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/posts\/1767\/revisions"}],"predecessor-version":[{"id":1823,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/posts\/1767\/revisions\/1823"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/media\/1809"}],"wp:attachment":[{"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/media?parent=1767"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/categories?post=1767"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/tags?post=1767"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}