{"id":2181,"date":"2026-05-26T14:10:30","date_gmt":"2026-05-26T06:10:30","guid":{"rendered":"https:\/\/jeez-semicon.com\/?p=2181"},"modified":"2026-05-26T14:34:36","modified_gmt":"2026-05-26T06:34:36","slug":"common-defects-in-mechanical-polishing-how-to-fix-them","status":"publish","type":"post","link":"https:\/\/jeez-semicon.com\/de\/blog\/common-defects-in-mechanical-polishing-how-to-fix-them\/","title":{"rendered":"Common Defects in Mechanical Polishing and CMP: Root Cause Analysis and Corrective Actions"},"content":{"rendered":"<!-- CLUSTER 8: Common Defects in Mechanical Polishing | JEEZ -->\n<style>\n.jz,.jz *,.jz *::before,.jz *::after{box-sizing:border-box}\n.jz{font-family:'Georgia','Times New Roman',serif;font-size:17px;line-height:1.85;color:#1a1a2e;max-width:860px;margin:0 auto;padding:0 20px 60px}\n.jz h2{font-family:'Trebuchet MS','Segoe UI',sans-serif;font-size:1.72rem;font-weight:700;color:#0a1628;margin:2.8rem 0 1rem;padding-bottom:.45rem;border-bottom:3px solid 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h1{font-size:1.6rem}.jz-cta{padding:28px 18px}}\n<\/style>\n\n<article class=\"jz\" itemscope itemtype=\"https:\/\/schema.org\/Article\">\n\n<div class=\"jz-hero\">\n  <div class=\"jz-hero-label\">Process Engineering \u2014 Defect Reference<\/div>\n  \n  <p class=\"jz-hero-sub\">A comprehensive troubleshooting reference for process engineers \u2014 covering macro-scratches, micro-scratches, dishing, erosion, delamination, orange peel, embedded abrasive, and edge roll-off in both industrial mechanical polishing and semiconductor CMP applications.<\/p>\n  <div class=\"jz-hero-meta\">\n    <span>Updated: May 2026<\/span>\n    <span>By JEEZ Engineering Team<\/span>\n    <span>~1,400 words<\/span>\n  <\/div>\n<\/div>\n\n<nav class=\"jz-toc\" aria-label=\"Inhalts\u00fcbersicht\">\n  <div class=\"jz-toc-title\">Inhalts\u00fcbersicht<\/div>\n  <ol>\n    <li><a href=\"#c8-framework\">Defect Classification Framework<\/a><\/li>\n    <li><a href=\"#c8-scratches\">Macro-Scratches and Micro-Scratches<\/a><\/li>\n    <li><a href=\"#c8-dishing\">Dishing (CMP \u2014 Cu\/W)<\/a><\/li>\n    <li><a href=\"#c8-erosion\">Erosion and Pattern Density Effects<\/a><\/li>\n    <li><a href=\"#c8-delamination\">Delamination<\/a><\/li>\n    <li><a href=\"#c8-orangepeel\">Orange Peel (Industrial Metal Polishing)<\/a><\/li>\n    <li><a href=\"#c8-embedded\">Embedded Abrasive<\/a><\/li>\n    <li><a href=\"#c8-edge\">Edge Roll-Off and Corner Rounding<\/a><\/li>\n    <li><a href=\"#c8-residual\">Residual Metal and Incomplete Clearing (CMP)<\/a><\/li>\n    <li><a href=\"#c8-summary\">Quick-Reference Troubleshooting Table<\/a><\/li>\n    <li><a href=\"#c8-faq\">H\u00e4ufig gestellte Fragen<\/a><\/li>\n  <\/ol>\n<\/nav>\n\n<p itemprop=\"description\">Polishing defects represent some of the highest-impact yield detractors in both semiconductor manufacturing and precision industrial fabrication. In a semiconductor fab, a single CMP-induced scratch event on a 300 mm wafer can kill hundreds of die. In pharmaceutical equipment manufacturing, a surface defect that fails ASME BPE Ra requirements requires the entire polishing sequence to be restarted. In both contexts, rapid and accurate root cause identification \u2014 followed by a targeted corrective action \u2014 is the difference between a controlled process and chronic yield loss. This article is a structured technical troubleshooting reference for the most common polishing defects. For foundational polishing context, see our <a href=\"https:\/\/jeez-semicon.com\/de\/blog\/What-Is-Mechanical-Polishing-a-complete-technical-guide-for-semiconductor-manufacturing\/\" target=\"_blank\" rel=\"noopener\">complete mechanical polishing guide<\/a>.<\/p>\n\n<h2 id=\"c8-framework\">1. Defect Classification Framework<\/h2>\n<p>Polishing defects can be organized by their root cause domain \u2014 which helps direct the troubleshooting investigation to the correct process variable:<\/p>\n<div class=\"jz-table-wrap\">\n  <table class=\"jz-table\">\n    <thead><tr><th>Root Cause Domain<\/th><th>Typical Defects<\/th><th>First Investigation Step<\/th><\/tr><\/thead>\n    <tbody>\n      <tr><td><strong>Consumable quality<\/strong><\/td><td>Macro-scratch, micro-scratch, residual metal<\/td><td>Review slurry LPC data; check pad condition; lot change history<\/td><\/tr>\n      <tr><td><strong>Process parameter<\/strong><\/td><td>Dishing, erosion, edge roll-off, delamination<\/td><td>Review pressure, velocity, polish time, endpoint signal<\/td><\/tr>\n      <tr><td><strong>Workpiece \/ substrate<\/strong><\/td><td>Orange peel, embedded abrasive, pitting<\/td><td>Inspect incoming material; review prior process steps<\/td><\/tr>\n      <tr><td><strong>Grit sequence \/ operator<\/strong><\/td><td>Residual coarse scratches, smearing, glazing<\/td><td>Verify grit sequence records; operator qualification check<\/td><\/tr>\n      <tr><td><strong>Tool \/ equipment<\/strong><\/td><td>Radial scratch patterns, WIWNU excursion<\/td><td>Run bare wafer check; inspect retaining ring; verify conditioner<\/td><\/tr>\n    <\/tbody>\n  <\/table>\n<\/div>\n\n<h2 id=\"c8-scratches\">2. Macro-Scratches and Micro-Scratches<\/h2>\n<div class=\"jz-defect-block\">\n  <div class=\"jz-defect-header\">\n    <div class=\"jz-defect-icon\">\u26a0\ufe0f<\/div>\n    <div>\n      <div class=\"jz-defect-title\">Macro-Scratches \/ Micro-Scratches<\/div>\n      <div class=\"jz-defect-subtitle\">Applicable to: CMP (wafer) and industrial mechanical polishing<\/div>\n    <\/div>\n  <\/div>\n  <div class=\"jz-defect-grid\">\n    <div>\n      <div class=\"jz-defect-col-title\">Grundlegende Ursachen<\/div>\n      <p class=\"jz-defect-col-body\">Large particle contamination (LPC) in CMP slurry \u2014 particles &gt;0.5 \u00b5m act as micro-cutting tools. Pad debris agglomerates. Grit step skipped in industrial polishing. Diamond conditioner shedding. Tool contamination (previous lot residue).<\/p>\n    <\/div>\n    <div>\n      <div class=\"jz-defect-col-title\">Detection<\/div>\n      <p class=\"jz-defect-col-body\">KLA bright-field or dark-field wafer inspection (CMP). Visual inspection under raking light for industrial SS. Profilometer Ra spike at scratch location. Macro: visible &gt;1 \u00b5m wide; micro: detected by high-sensitivity inspection tool.<\/p>\n    <\/div>\n    <div>\n      <div class=\"jz-defect-col-title\">Corrective Actions<\/div>\n      <p class=\"jz-defect-col-body\">Implement in-line 0.2 \u00b5m slurry filtration at point-of-use. Add real-time LPC monitor (AccuSizer or equivalent) with auto-abort interlock. Enforce pad conditioning protocol \u2014 dressing rate, sweep speed, pressure. Perform tool qualification run with bare Si wafer after any wet maintenance. For industrial polishing: never skip grit steps; verify scratch removal before advancing.<\/p>\n    <\/div>\n  <\/div>\n<\/div>\n\n<div class=\"jz-callout red\">\n  <div class=\"jz-callout-title\">CMP Slurry Shelf Life \u2014 A Frequently Overlooked Scratch Source<\/div>\n  <p>Colloidal silica CMP slurry undergoes particle agglomeration if stored beyond its stated shelf life, if frozen and thawed, or if exposed to excessive heat. Agglomerated particles behave as large particles in the CMP tool and generate macro-scratches indistinguishable from true LPC events. Always check slurry manufacturing date and storage conditions when investigating a scratch excursion, and enforce first-in-first-out (FIFO) slurry inventory management.<\/p>\n<\/div>\n\n<h2 id=\"c8-dishing\">3. Dishing (CMP \u2014 Cu\/W)<\/h2>\n<div class=\"jz-defect-block\">\n  <div class=\"jz-defect-header\">\n    <div class=\"jz-defect-icon\">\ud83d\udd3d<\/div>\n    <div>\n      <div class=\"jz-defect-title\">Dishing<\/div>\n      <div class=\"jz-defect-subtitle\">Applicable to: Cu damascene CMP, W plug CMP<\/div>\n    <\/div>\n  <\/div>\n  <div class=\"jz-defect-grid\">\n    <div>\n      <div class=\"jz-defect-col-title\">Grundlegende Ursachen<\/div>\n      <p class=\"jz-defect-col-body\">Cu or W removal rate significantly exceeds surrounding dielectric removal rate after metal clearing. The soft metal is over-polished while the pad continues to remove metal in wide, recessed features. Excessive over-polish time compounds the effect. High BTA concentration in Cu slurry can inhibit Cu dissolution and paradoxically increase dishing at low pattern densities.<\/p>\n    <\/div>\n    <div>\n      <div class=\"jz-defect-col-title\">Detection<\/div>\n      <p class=\"jz-defect-col-body\">AFM or contact profilometer measurement across wide Cu lines post-CMP. Spectroscopic reflectometry for in-line monitoring. Dishing values are typically specified at maximum wide metal feature (e.g., 100 \u00b5m Cu line): spec typically &lt;30 nm for advanced Cu interconnect.<\/p>\n    <\/div>\n    <div>\n      <div class=\"jz-defect-col-title\">Corrective Actions<\/div>\n      <p class=\"jz-defect-col-body\">Implement robust optical endpoint detection to minimize over-polish time. Transition to low-downforce step-2 polish with high-oxide-selectivity slurry. Optimize BTA concentration for your pattern density distribution. Use a barrier-selective slurry in step-2 that removes residual Cu\/barrier without further attacking recessed Cu. Design rule enforcement: limit maximum isolated Cu feature width in critical layers.<\/p>\n    <\/div>\n  <\/div>\n<\/div>\n\n<h2 id=\"c8-erosion\">4. Erosion and Pattern Density Effects<\/h2>\n<div class=\"jz-defect-block\">\n  <div class=\"jz-defect-header\">\n    <div class=\"jz-defect-icon\">\ud83d\udcc9<\/div>\n    <div>\n      <div class=\"jz-defect-title\">Erosion (Oxide Loss in High-Density Metal Arrays)<\/div>\n      <div class=\"jz-defect-subtitle\">Applicable to: Cu damascene CMP, STI CMP<\/div>\n    <\/div>\n  <\/div>\n  <div class=\"jz-defect-grid\">\n    <div>\n      <div class=\"jz-defect-col-title\">Grundlegende Ursachen<\/div>\n      <p class=\"jz-defect-col-body\">In high pattern density regions (e.g., 50% metal fill), the effective pad-wafer contact is softer and the local removal rate is higher than in low-density regions. Oxide between metal lines is removed faster than in sparse areas. The result is a height difference across the die between dense and isolated regions \u2014 the &#8220;density-dependent erosion&#8221; or &#8220;micro-loading&#8221; effect.<\/p>\n    <\/div>\n    <div>\n      <div class=\"jz-defect-col-title\">Detection<\/div>\n      <p class=\"jz-defect-col-body\">Multi-point spectroscopic reflectometry or ellipsometry mapping post-CMP. Cross-sectional TEM at dense vs. isolated regions. Erosion measured as oxide loss (nm) at dense metal array versus field oxide reference.<\/p>\n    <\/div>\n    <div>\n      <div class=\"jz-defect-col-title\">Corrective Actions<\/div>\n      <p class=\"jz-defect-col-body\">Use a slurry with high oxide-to-metal selectivity in bulk polish step to reduce oxide removal at dense regions. Adjust retaining ring and multi-zone carrier pressure to profile the within-wafer removal rate for your specific die layout. Implement dummy metal fill rules in design to equalize pattern density across the die. Optimize pad stiffness \u2014 harder pad reduces the pattern density effect (higher planarity efficiency).<\/p>\n    <\/div>\n  <\/div>\n<\/div>\n\n<h2 id=\"c8-delamination\">5. Delamination<\/h2>\n<div class=\"jz-defect-block\">\n  <div class=\"jz-defect-header\">\n    <div class=\"jz-defect-icon\">\ud83d\udca5<\/div>\n    <div>\n      <div class=\"jz-defect-title\">Delamination<\/div>\n      <div class=\"jz-defect-subtitle\">Applicable to: low-k dielectric CMP, thin film stack polishing<\/div>\n    <\/div>\n  <\/div>\n  <div class=\"jz-defect-grid\">\n    <div>\n      <div class=\"jz-defect-col-title\">Grundlegende Ursachen<\/div>\n      <p class=\"jz-defect-col-body\">Shear stress at pad\u2013wafer interface exceeds the adhesion strength of the low-k dielectric or cap layer interface. Particularly severe for ultra-low-k (k &lt; 2.5) porous dielectrics with Young&#8217;s modulus &lt; 5 GPa. Excessive polish pressure or velocity concentrates stress at film interfaces. Water uptake by the porous dielectric during slurry exposure weakens the structure.<\/p>\n    <\/div>\n    <div>\n      <div class=\"jz-defect-col-title\">Detection<\/div>\n      <p class=\"jz-defect-col-body\">Acoustic emission monitoring (in-situ). KLA inspection for delamination fragments. Cross-sectional SEM\/TEM for interface integrity verification. Electrical test: leakage current increase between adjacent metal lines indicates dielectric delamination.<\/p>\n    <\/div>\n    <div>\n      <div class=\"jz-defect-col-title\">Corrective Actions<\/div>\n      <p class=\"jz-defect-col-body\">Reduce down-force to minimum that achieves required removal rate. Switch to a compliant, low-modulus polishing pad. Minimize slurry contact time with exposed low-k surfaces. Optimize cap layer adhesion (hardmask selection). For porous ultra-low-k: consider UV cure before CMP to improve mechanical strength of the dielectric film.<\/p>\n    <\/div>\n  <\/div>\n<\/div>\n\n<h2 id=\"c8-orangepeel\">6. Orange Peel (Industrial Metal Polishing)<\/h2>\n<div class=\"jz-defect-block\">\n  <div class=\"jz-defect-header\">\n    <div class=\"jz-defect-icon\">\ud83c\udf4a<\/div>\n    <div>\n      <div class=\"jz-defect-title\">Orange Peel Texture<\/div>\n      <div class=\"jz-defect-subtitle\">Applicable to: stainless steel, hardened tool steel, aluminum alloy polishing<\/div>\n    <\/div>\n  <\/div>\n  <div class=\"jz-defect-grid\">\n    <div>\n      <div class=\"jz-defect-col-title\">Grundlegende Ursachen<\/div>\n      <p class=\"jz-defect-col-body\">Coarse grain structure in the workpiece metal (common in castings, heavily cold-worked stock, or improperly annealed material). Individual grains polish at different rates due to crystallographic orientation differences, creating a bumpy, low-spatial-frequency surface texture. Also caused by transitioning to fine grit too early, before coarse defects are fully removed.<\/p>\n    <\/div>\n    <div>\n      <div class=\"jz-defect-col-title\">Detection<\/div>\n      <p class=\"jz-defect-col-body\">Visual inspection under raking (oblique) light reveals the matte, dimpled texture. Not detectable by Ra alone \u2014 Ra may appear within spec while the orange peel spatial wavelength (0.5\u20135 mm) contributes to Wa (waviness) rather than Ra. Optical profilometer shows characteristic mounds at grain scale.<\/p>\n    <\/div>\n    <div>\n      <div class=\"jz-defect-col-title\">Corrective Actions<\/div>\n      <p class=\"jz-defect-col-body\">Anneal the workpiece to refine grain structure before polishing if possible. Return to a coarser grit stage to re-establish a uniform scratch texture before progressing. For tool steels: confirm the hardness range before selecting abrasive; severely over-hardened steel may require soft annealing before polishing. Avoid excessive dwell in early buffing stages before the scratch pattern from prior steps is fully removed.<\/p>\n    <\/div>\n  <\/div>\n<\/div>\n\n<h2 id=\"c8-embedded\">7. Embedded Abrasive<\/h2>\n<div class=\"jz-defect-block\">\n  <div class=\"jz-defect-header\">\n    <div class=\"jz-defect-icon\">\ud83d\udd34<\/div>\n    <div>\n      <div class=\"jz-defect-title\">Embedded Abrasive Particles<\/div>\n      <div class=\"jz-defect-subtitle\">Applicable to: soft metal polishing (Al, Cu, Mg); industrial mechanical polishing<\/div>\n    <\/div>\n  <\/div>\n  <div class=\"jz-defect-grid\">\n    <div>\n      <div class=\"jz-defect-col-title\">Grundlegende Ursachen<\/div>\n      <p class=\"jz-defect-col-body\">Hard abrasive particles (Al\u2082O\u2083, SiC) pressed into a soft metal surface under polishing pressure become mechanically trapped in the subsurface deformation zone. The softer the metal and the harder the abrasive, the higher the embedding tendency. Also occurs when abrasive media is used without adequate flushing, allowing spent particles to accumulate and agglomerate on the surface.<\/p>\n    <\/div>\n    <div>\n      <div class=\"jz-defect-col-title\">Detection<\/div>\n      <p class=\"jz-defect-col-body\">EDS (energy-dispersive X-ray spectroscopy) analysis detects embedded Si or Al on a Cu or Al surface. Scanning electron microscopy (SEM) reveals sub-surface particle inclusions. In pharmaceutical equipment: ICP-MS analysis of rinse water detects particle contamination from embedded abrasive shedding during CIP.<\/p>\n    <\/div>\n    <div>\n      <div class=\"jz-defect-col-title\">Corrective Actions<\/div>\n      <p class=\"jz-defect-col-body\">Follow industrial mechanical polishing with electropolishing \u2014 the anodic dissolution removes the cold-worked surface layer containing embedded particles. For CMP: use colloidal slurry (smoother particles, lower embedding tendency) rather than fumed silica on soft metal layers. Ensure adequate slurry flow and pad conditioning to continuously remove spent abrasive from the pad surface rather than recirculating it. Post-CMP brush cleaning removes residual surface particles.<\/p>\n    <\/div>\n  <\/div>\n<\/div>\n\n<h2 id=\"c8-edge\">8. Edge Roll-Off and Corner Rounding<\/h2>\n<div class=\"jz-defect-block\">\n  <div class=\"jz-defect-header\">\n    <div class=\"jz-defect-icon\">\ud83d\udcd0<\/div>\n    <div>\n      <div class=\"jz-defect-title\">Edge Roll-Off \/ Corner Rounding<\/div>\n      <div class=\"jz-defect-subtitle\">Applicable to: CMP (wafer edge exclusion), industrial polishing of flat plates<\/div>\n    <\/div>\n  <\/div>\n  <div class=\"jz-defect-grid\">\n    <div>\n      <div class=\"jz-defect-col-title\">Grundlegende Ursachen<\/div>\n      <p class=\"jz-defect-col-body\">At the wafer edge (or workpiece boundary), the pad complies downward as it extends beyond the edge, increasing local contact pressure and removal rate. The edge of the wafer sees higher removal rate than the center, resulting in a thinned, rolled-off edge profile. Retaining ring wear or incorrect retaining ring force settings amplify this effect in CMP.<\/p>\n    <\/div>\n    <div>\n      <div class=\"jz-defect-col-title\">Detection<\/div>\n      <p class=\"jz-defect-col-body\">Post-CMP film thickness mapping (spectroscopic reflectometry): characteristic &#8220;bull&#8217;s-eye&#8221; pattern with thin edge ring. Edge exclusion zone (typically 2\u20133 mm from wafer edge) is excluded from process window specification. For industrial plates: profilometer measurement at part edges confirms radius increase.<\/p>\n    <\/div>\n    <div>\n      <div class=\"jz-defect-col-title\">Corrective Actions<\/div>\n      <p class=\"jz-defect-col-body\">Optimize retaining ring down-force: increasing retaining ring force reduces edge roll-off by limiting pad deflection at the wafer edge. Adjust multi-zone carrier edge zone pressure upward to compensate for higher local removal rate. Implement edge exclusion rules in device placement to keep critical features away from the roll-off zone. For industrial polishing: reduce polishing dwell time at part edges; consider fixturing that extends the backing plate beyond the workpiece edge.<\/p>\n    <\/div>\n  <\/div>\n<\/div>\n\n<h2 id=\"c8-residual\">9. Residual Metal and Incomplete Clearing (CMP)<\/h2>\n<div class=\"jz-defect-block\">\n  <div class=\"jz-defect-header\">\n    <div class=\"jz-defect-icon\">\ud83d\udd17<\/div>\n    <div>\n      <div class=\"jz-defect-title\">Residual Metal \/ Incomplete Clearing<\/div>\n      <div class=\"jz-defect-subtitle\">Applicable to: Cu damascene CMP, W plug CMP, barrier CMP<\/div>\n    <\/div>\n  <\/div>\n  <div class=\"jz-defect-grid\">\n    <div>\n      <div class=\"jz-defect-col-title\">Grundlegende Ursachen<\/div>\n      <p class=\"jz-defect-col-body\">Insufficient polish time; endpoint detection triggering too early (false endpoint on endpoint signal noise); wafer-center removal rate lower than wafer-edge rate (center-slow WIWNU profile) leaving residual metal at the wafer center; incoming film topography higher than the CMP process window (excessive incoming step height).<\/p>\n    <\/div>\n    <div>\n      <div class=\"jz-defect-col-title\">Detection<\/div>\n      <p class=\"jz-defect-col-body\">Sheet resistance mapping (4-point probe): residual conducting metal shows low sheet resistance in cleared regions. Optical inspection: metallic residue has characteristic bright appearance. KLA inspection: metal &#8220;bridges&#8221; between features detected as shorts in electrical test.<\/p>\n    <\/div>\n    <div>\n      <div class=\"jz-defect-col-title\">Corrective Actions<\/div>\n      <p class=\"jz-defect-col-body\">Extend polish time or increase over-polish percentage. Recalibrate endpoint detection algorithm to avoid false triggers. Profile carrier zone pressures to correct center-slow WIWNU \u2014 typically increase center zone pressure. Verify incoming film thickness and topography before CMP; if incoming step height exceeds the planarization length of the pad\/slurry system, a pre-planarization step (spin-on glass or additional CVD) may be required.<\/p>\n    <\/div>\n  <\/div>\n<\/div>\n\n<h2 id=\"c8-summary\">10. Quick-Reference Troubleshooting Table<\/h2>\n<div class=\"jz-table-wrap\">\n  <table class=\"jz-table\">\n    <thead><tr><th>Defect<\/th><th>Top Root Cause<\/th><th>First Corrective Action<\/th><th>Relevant Process<\/th><\/tr><\/thead>\n    <tbody>\n      <tr><td>Macro-scratch<\/td><td>LPC in slurry \/ pad debris<\/td><td>Point-of-use 0.2 \u00b5m filtration; bare wafer qualification run<\/td><td>CMP<\/td><\/tr>\n      <tr><td>Micro-scratch<\/td><td>Slurry agglomeration \/ glazed pad<\/td><td>Check slurry shelf life; increase conditioner aggressiveness<\/td><td>CMP<\/td><\/tr>\n      <tr><td>Residual coarse scratches<\/td><td>Grit step skipped<\/td><td>Return to previous grit; verify scratch removal under raking light<\/td><td>Industrial polish<\/td><\/tr>\n      <tr><td>Dishing<\/td><td>Over-polish time; high Cu removal rate<\/td><td>Improve endpoint detection; reduce step-2 down-force<\/td><td>Cu\/W CMP<\/td><\/tr>\n      <tr><td>Erosion<\/td><td>Pattern density variation<\/td><td>Harder pad; dummy fill; slurry selectivity optimization<\/td><td>Cu\/STI CMP<\/td><\/tr>\n      <tr><td>Delamination<\/td><td>Excessive shear on low-k film<\/td><td>Reduce pressure; use compliant pad; check cap layer adhesion<\/td><td>Low-k CMP<\/td><\/tr>\n      <tr><td>Orange peel<\/td><td>Coarse grain structure<\/td><td>Anneal; step back to coarser grit<\/td><td>Industrial SS\/steel<\/td><\/tr>\n      <tr><td>Embedded abrasive<\/td><td>Hard abrasive in soft metal<\/td><td>Follow with electropolishing; switch to colloidal slurry<\/td><td>Industrial \/ CMP<\/td><\/tr>\n      <tr><td>Edge roll-off<\/td><td>Pad compliance at wafer edge<\/td><td>Increase retaining ring force; adjust edge zone pressure<\/td><td>CMP<\/td><\/tr>\n      <tr><td>Residual metal<\/td><td>Short polish time \/ false endpoint<\/td><td>Extend over-polish; recalibrate endpoint algorithm<\/td><td>Cu\/W CMP<\/td><\/tr>\n      <tr><td>Heat tint (SS)<\/td><td>Excessive friction heat<\/td><td>Add coolant; replace worn belts; reduce contact pressure<\/td><td>Industrial SS<\/td><\/tr>\n    <\/tbody>\n  <\/table>\n<\/div>\n\n<div class=\"jz-callout teal\">\n  <div class=\"jz-callout-title\">Proactive Defect Prevention: Consumable Monitoring Program<\/div>\n  <p>The most cost-effective defect reduction strategy in CMP is a proactive consumable monitoring program \u2014 tracking slurry LPC, D99 particle size, pH, and oxidizer concentration on every incoming lot before fab release, combined with pad-life endpoint tracking via in-situ friction monitoring. JEEZ provides full lot characterization data with every shipment, enabling customers to implement incoming inspection protocols without requiring in-house particle analysis infrastructure. <a href=\"https:\/\/jeez-semicon.com\/de\/blog\/Mechanical-Polishing-Services:-What-to-Look-For-in-a-Supplier\/\" target=\"_blank\" rel=\"noopener\">Learn more about what to require from a CMP consumable supplier.<\/a><\/p>\n<\/div>\n\n<hr class=\"jz-divider\">\n\n<h2 id=\"c8-faq\">11. H\u00e4ufig gestellte Fragen<\/h2>\n<div itemscope itemtype=\"https:\/\/schema.org\/FAQPage\">\n  <div class=\"jz-faq-item\" itemscope itemprop=\"mainEntity\" itemtype=\"https:\/\/schema.org\/Question\">\n    <div class=\"jz-faq-q\" itemprop=\"name\">How do I distinguish a slurry-induced scratch from a pad-induced scratch in CMP?<\/div>\n    <div itemscope itemprop=\"acceptedAnswer\" itemtype=\"https:\/\/schema.org\/Answer\">\n      <p class=\"jz-faq-a\" itemprop=\"text\">Slurry-induced scratches (from LPC) typically appear as randomly distributed, isolated long scratches across the wafer surface, often with a &#8220;comet tail&#8221; morphology when examined under SEM. Pad-induced scratches (from pad debris or conditioner shedding) tend to appear in arcing or radial patterns that follow the pad rotation direction, and may cluster at specific wafer radii corresponding to tool kinematics. Running a bare silicon wafer through the same process conditions without slurry \u2014 replacing with DI water \u2014 and comparing scratch patterns can help isolate whether the tool hardware is generating the defects independently of slurry quality.<\/p>\n    <\/div>\n  <\/div>\n  <div class=\"jz-faq-item\" itemscope itemprop=\"mainEntity\" itemtype=\"https:\/\/schema.org\/Question\">\n    <div class=\"jz-faq-q\" itemprop=\"name\">What is an acceptable dishing specification for Cu interconnect at advanced nodes?<\/div>\n    <div itemscope itemprop=\"acceptedAnswer\" itemtype=\"https:\/\/schema.org\/Answer\">\n      <p class=\"jz-faq-a\" itemprop=\"text\">Dishing specifications depend on the metal line width and device technology node. For advanced-node Cu interconnect (metal 1 and metal 2 at 3 nm class nodes), dishing at a 50 \u00b5m wide Cu feature is typically specified at \u2264 15\u201325 nm. For wider features used in power distribution (up to 100 \u00b5m), dishing \u2264 30\u201340 nm is typical. These specifications are driven by downstream lithography focus budget constraints and resistance uniformity requirements. As nodes scale, the acceptable dishing budget shrinks because the absolute metal height variation must remain below a smaller fraction of the total film thickness.<\/p>\n    <\/div>\n  <\/div>\n  <div class=\"jz-faq-item\" itemscope itemprop=\"mainEntity\" itemtype=\"https:\/\/schema.org\/Question\">\n    <div class=\"jz-faq-q\" itemprop=\"name\">Can an orange peel surface on stainless steel be corrected by additional polishing?<\/div>\n    <div itemscope itemprop=\"acceptedAnswer\" itemtype=\"https:\/\/schema.org\/Answer\">\n      <p class=\"jz-faq-a\" itemprop=\"text\">In most cases, no \u2014 not by fine polishing alone. Orange peel is a manifestation of the underlying grain structure, which polishing cannot change. Attempting to eliminate orange peel by continuing to polish with finer grit typically results in a shinier but still dimpled surface where the grain-scale topography remains visible. The correct remedy is to step back to a coarser grit that cuts at a scale comparable to the grain size, re-establishing a uniform scratch texture, and then re-progressing through the grit sequence. For severe cases where grain size is fundamentally incompatible with the required finish, annealing the workpiece before re-polishing is necessary.<\/p>\n    <\/div>\n  <\/div>\n<\/div>\n\n<hr class=\"jz-divider\">\n\n<h3>Related Technical Articles<\/h3>\n<div class=\"jz-related\">\n  <a class=\"jz-related-card\" href=\"https:\/\/jeez-semicon.com\/de\/blog\/What-Is-Mechanical-Polishing-a-complete-technical-guide-for-semiconductor-manufacturing\/\" target=\"_blank\" rel=\"noopener\">\n    <div class=\"jz-related-icon\">\ud83d\udcd8<\/div>\n    <div class=\"jz-related-title\">Complete Mechanical Polishing Guide<\/div>\n    <div class=\"jz-related-desc\">Full reference \u2014 principles, CMP process, materials, standards, and all industry applications.<\/div>\n  <\/a>\n  <a class=\"jz-related-card\" href=\"https:\/\/jeez-semicon.com\/de\/blog\/Chemical-Mechanical-Polishing-(CMP):-Semiconductor-Applications\/\" target=\"_blank\" rel=\"noopener\">\n    <div class=\"jz-related-icon\">\ud83d\udca1<\/div>\n    <div class=\"jz-related-title\">CMP Semiconductor Applications<\/div>\n    <div class=\"jz-related-desc\">STI, W, Cu damascene CMP \u2014 process control and endpoint detection in depth.<\/div>\n  <\/a>\n  <a class=\"jz-related-card\" href=\"https:\/\/jeez-semicon.com\/de\/blog\/Mechanical-Polishing-of-Stainless-Steel:-Process-&\/#038;-Standards\" target=\"_blank\" rel=\"noopener\">\n    <div class=\"jz-related-icon\">\ud83d\udd29<\/div>\n    <div class=\"jz-related-title\">Stainless Steel Polishing<\/div>\n    <div class=\"jz-related-desc\">Grit sequences, work hardening, and defect prevention specific to SS polishing.<\/div>\n  <\/a>\n  <a class=\"jz-related-card\" href=\"https:\/\/jeez-semicon.com\/de\/blog\/Mechanical-Polishing-Services:-What-to-Look-For-in-a-Supplier\/\" target=\"_blank\" rel=\"noopener\">\n    <div class=\"jz-related-icon\">\ud83c\udfed<\/div>\n    <div class=\"jz-related-title\">Supplier Evaluation Guide<\/div>\n    <div class=\"jz-related-desc\">How to select CMP consumable suppliers with the quality controls to prevent defects.<\/div>\n  <\/a>\n<\/div>\n\n<div class=\"jz-brand\">\n  <div class=\"jz-brand-logo\">JEEZ<\/div>\n  <div class=\"jz-brand-text\">Published by the applications engineering team at <strong>Jizhi Electronic Technology Co., Ltd. (JEEZ)<\/strong> \u2014 manufacturer of CMP slurries, polishing pads, absorption films, and dicing blades for the semiconductor industry. Last reviewed: May 2026.<\/div>\n<\/div>\n\n<div class=\"jz-cta\">\n  <h2>Reduce CMP Defects with JEEZ Precision Consumables<\/h2>\n  <p>JEEZ CMP slurries, polishing pads, and backing films are supplied with full lot characterization data \u2014 enabling incoming inspection protocols that prevent defect excursions before they reach production wafers.<\/p>\n  <div class=\"jz-cta-btns\">\n    <a class=\"jz-btn primary\" href=\"https:\/\/jeez-semicon.com\/de\/contact\/\" target=\"_blank\" rel=\"noopener\">Request a Sample<\/a>\n    <a class=\"jz-btn outline\" href=\"https:\/\/jeez-semicon.com\/de\/contact\/\" target=\"_blank\" rel=\"noopener\">Talk to an Engineer<\/a>\n  <\/div>\n<\/div>\n\n<\/article>","protected":false},"excerpt":{"rendered":"<p>Process Engineering \u2014 Defect Reference A comprehensive troubleshooting reference for process engineers \u2014 covering macro-scratches, micro-scratches, dishing, erosion, delamination, orange peel, embedded abrasive, and edge roll-off in both industrial mechanical  &#8230;<\/p>","protected":false},"author":1,"featured_media":2183,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[9,59],"tags":[],"class_list":["post-2181","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-blog","category-industry"],"acf":[],"_links":{"self":[{"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/posts\/2181","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/comments?post=2181"}],"version-history":[{"count":5,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/posts\/2181\/revisions"}],"predecessor-version":[{"id":2203,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/posts\/2181\/revisions\/2203"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/media\/2183"}],"wp:attachment":[{"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/media?parent=2181"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/categories?post=2181"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/tags?post=2181"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}