{"id":2281,"date":"2026-06-09T15:53:30","date_gmt":"2026-06-09T07:53:30","guid":{"rendered":"https:\/\/jeez-semicon.com\/?p=2281"},"modified":"2026-06-09T15:53:30","modified_gmt":"2026-06-09T07:53:30","slug":"silicon-wafer-polishing-process-step-by-step-from-lapping-to-final-polish","status":"publish","type":"post","link":"https:\/\/jeez-semicon.com\/de\/blog\/silicon-wafer-polishing-process-step-by-step-from-lapping-to-final-polish\/","title":{"rendered":"Silicon Wafer Polishing Process: Step-by-Step from Lapping to Final Polish"},"content":{"rendered":"<style>\n@import url('https:\/\/fonts.googleapis.com\/css2?family=Sora:wght@400;500;600;700;800&family=IBM+Plex+Sans:ital,wght@0,300;0,400;0,500;0,600;1,400&display=swap');\n.jeez-pillar*,.jeez-pillar*::before,.jeez-pillar*::after{box-sizing:border-box;margin:0;padding:0}\n.jeez-pillar{font-family:'IBM Plex Sans',-apple-system,BlinkMacSystemFont,sans-serif;font-size:17px;line-height:1.78;color:#1C2B3A;max-width:900px;margin:0 auto;padding:0 0 3rem}\n.jeez-pillar h2,.jeez-pillar h3,.jeez-pillar h4{font-family:'Sora',-apple-system,sans-serif;line-height:1.25}\n.jeez-pillar h2{font-size:1.85rem;font-weight:700;color:#07193A;margin:3rem 0 1.1rem;padding-bottom:.65rem;border-bottom:3px solid #1553A0}\n.jeez-pillar h3{font-size:1.2rem;font-weight:600;color:#1553A0;margin:2rem 0 .75rem}\n.jeez-pillar p{margin-bottom:1.3rem}.jeez-pillar p:last-child{margin-bottom:0}\n.jeez-pillar ul,.jeez-pillar ol{padding-left:1.5rem;margin-bottom:1.3rem}\n.jeez-pillar li{margin-bottom:.5rem}\n.jeez-pillar strong{font-weight:600;color:#07193A}\n.jeez-pillar a{color:#1553A0;text-decoration:none;border-bottom:1px solid rgba(21,83,160,.35);transition:color .18s,border-color .18s}\n.jeez-pillar a:hover{color:#007B6E;border-bottom-color:#007B6E}\n.jp-back{display:inline-flex;align-items:center;gap:.5rem;font-family:'Sora',sans-serif;font-size:.82rem;font-weight:600;color:#1553A0;background:#EEF4FF;border:1px solid #C5D6F5;border-radius:6px;padding:.4rem .9rem;text-decoration:none;border-bottom:none;margin-bottom:1.5rem;transition:background .18s}\n.jp-back:hover{background:#1553A0;color:#fff}\n.jp-hero{background:linear-gradient(135deg,#071B40 0%,#1553A0 55%,#0086A0 100%);color:#fff;padding:3rem 2.75rem 2.75rem;border-radius:14px;margin-bottom:2.5rem;position:relative;overflow:hidden}\n.jp-hero::before{content:'';position:absolute;top:-50px;right:-50px;width:240px;height:240px;border:48px solid rgba(255,255,255,.06);border-radius:50%;pointer-events:none}\n.jp-hero::after{content:'';position:absolute;bottom:-70px;right:80px;width:320px;height:320px;border:48px solid rgba(255,255,255,.04);border-radius:50%;pointer-events:none}\n.jp-hero-eyebrow{font-family:'Sora',sans-serif;font-size:.72rem;font-weight:600;letter-spacing:.18em;text-transform:uppercase;color:rgba(255,255,255,.6);margin-bottom:.85rem}\n.jp-hero h1{font-family:'Sora',sans-serif;font-size:2.1rem;font-weight:800;line-height:1.15;color:#fff;margin-bottom:1.1rem}\n.jp-hero-lead{font-size:1rem;color:rgba(255,255,255,.85);max-width:660px;line-height:1.72;margin-bottom:1.5rem}\n.jp-hero-meta{display:flex;gap:1.75rem;flex-wrap:wrap;font-size:.8rem;color:rgba(255,255,255,.55);font-family:'Sora',sans-serif}\n.jp-toc{background:#EEF4FF;border:1px solid #C5D6F5;border-left:5px solid #1553A0;border-radius:0 10px 10px 0;padding:1.6rem 2rem 1.6rem 1.75rem;margin:0 0 2.75rem}\n.jp-toc-title{font-family:'Sora',sans-serif;font-size:.78rem;font-weight:700;letter-spacing:.14em;text-transform:uppercase;color:#07193A;margin-bottom:1rem}\n.jp-toc ol{column-count:2;column-gap:2.5rem;margin:0;padding-left:1.25rem}\n.jp-toc li{margin-bottom:.45rem;break-inside:avoid;font-size:.88rem}\n.jp-toc a{color:#1553A0;border-bottom:none;font-weight:400;line-height:1.5}\n.jp-toc a:hover{text-decoration:underline;color:#007B6E}\n@media(max-width:620px){.jp-toc ol{column-count:1}}\n.jp-stats{display:grid;grid-template-columns:repeat(auto-fit,minmax(170px,1fr));gap:1rem;margin:1.75rem 0}\n.jp-stat{background:#07193A;color:#fff;border-radius:10px;padding:1.35rem 1.25rem;text-align:center}\n.jp-stat-value{font-family:'Sora',sans-serif;font-size:1.9rem;font-weight:700;color:#6DB8FF;display:block;line-height:1;margin-bottom:.45rem}\n.jp-stat-label{font-size:.78rem;color:rgba(255,255,255,.65);line-height:1.45}\n.jp-callout{padding:1.2rem 1.5rem;border-radius:0 10px 10px 0;border-left:4px solid #1553A0;background:#EEF4FF;margin:1.75rem 0;font-size:.93rem;line-height:1.7}\n.jp-callout.teal{background:#E0F5F1;border-color:#007B6E}\n.jp-callout.amber{background:#FFF8E6;border-color:#D97706}\n.jp-callout.slate{background:#F1F5F9;border-color:#475569}\n.jp-steps{list-style:none;padding:0;margin:1.5rem 0;counter-reset:jp-step}\n.jp-steps li{counter-increment:jp-step;position:relative;padding:1.1rem 1.25rem 1.1rem 3.75rem;background:#F7FAFD;border:1px solid #E2EAF4;border-radius:10px;margin-bottom:.85rem}\n.jp-steps li::before{content:counter(jp-step);position:absolute;left:1rem;top:50%;transform:translateY(-50%);width:30px;height:30px;background:#1553A0;color:#fff;border-radius:50%;display:flex;align-items:center;justify-content:center;font-size:.8rem;font-weight:700;font-family:'Sora',sans-serif}\n.jp-steps li strong{display:block;font-family:'Sora',sans-serif;font-size:.95rem;color:#07193A;margin-bottom:.35rem}\n.jp-compare{display:grid;grid-template-columns:1fr 1fr;gap:1.1rem;margin:1.5rem 0}\n@media(max-width:600px){.jp-compare{grid-template-columns:1fr}}\n.jp-compare-box{background:#F7FAFD;border:1px solid #E2EAF4;border-top:4px solid #1553A0;border-radius:0 0 10px 10px;padding:1.25rem}\n.jp-compare-box:nth-child(2){border-top-color:#007B6E}\n.jp-compare-box h4{font-family:'Sora',sans-serif;font-size:.95rem;font-weight:700;color:#07193A;margin-bottom:.85rem}\n.jp-compare-box ul{padding-left:1.15rem;margin:0}\n.jp-compare-box li{font-size:.875rem;color:#334155;margin-bottom:.45rem}\n.jp-table-wrap{overflow-x:auto;margin:1.75rem 0;border-radius:10px;border:1px solid #E2EAF4;box-shadow:0 1px 4px rgba(21,83,160,.06)}\n.jp-table{width:100%;border-collapse:collapse;font-size:.865rem;background:#fff}\n.jp-table thead th{background:#07193A;color:#fff;padding:11px 15px;text-align:left;font-family:'Sora',sans-serif;font-weight:600;font-size:.77rem;letter-spacing:.05em;text-transform:uppercase;white-space:nowrap}\n.jp-table td{padding:10px 15px;border-bottom:1px solid #EEF2F8;vertical-align:top;line-height:1.55}\n.jp-table tr:last-child td{border-bottom:none}\n.jp-table tbody tr:nth-child(even) td{background:#F7FAFD}\n.jp-readmore{display:inline-flex;align-items:center;gap:7px;font-family:'Sora',sans-serif;font-size:.86rem;font-weight:600;color:#1553A0;border:none!important;text-decoration:none;padding:.55rem 1.1rem;background:#EEF4FF;border-radius:6px;margin-top:.75rem;transition:background .18s,color .18s}\n.jp-readmore:hover{background:#1553A0;color:#fff!important}\n.jp-readmore::after{content:'\u2192'}\n.jp-hr{border:none;border-top:1px solid #E2EAF4;margin:2.75rem 0}\n.jp-related{background:#F7FAFD;border:1px solid #E2EAF4;border-radius:12px;padding:1.75rem 2rem;margin:2.5rem 0}\n.jp-related-title{font-family:'Sora',sans-serif;font-size:.78rem;font-weight:700;letter-spacing:.14em;text-transform:uppercase;color:#07193A;margin-bottom:1.1rem}\n.jp-related-links{display:flex;flex-direction:column;gap:.6rem}\n.jp-rl{display:flex;align-items:flex-start;gap:.75rem;padding:.7rem .9rem;background:#fff;border:1px solid #E2EAF4;border-radius:8px;text-decoration:none;border-bottom:none;color:#1C2B3A;transition:border-color .18s,box-shadow .18s}\n.jp-rl:hover{border-color:#1553A0;box-shadow:0 2px 8px rgba(21,83,160,.1)}\n.jp-rl-icon{font-size:1.1rem;flex-shrink:0;margin-top:1px}\n.jp-rl strong{display:block;font-family:'Sora',sans-serif;font-size:.88rem;font-weight:600;color:#07193A;margin-bottom:2px}\n.jp-rl span{font-size:.8rem;color:#5A6A7A}\n.jp-faq{margin:1.5rem 0}\n.jp-faq-item{border:1px solid #E2EAF4;border-radius:10px;margin-bottom:.75rem;overflow:hidden}\n.jp-faq-q{padding:1.05rem 1.35rem;font-family:'Sora',sans-serif;font-size:.93rem;font-weight:600;color:#07193A;background:#F7FAFD;cursor:pointer;display:flex;justify-content:space-between;align-items:center;user-select:none;gap:1rem;transition:background .15s}\n.jp-faq-q:hover{background:#EEF4FF}\n.jp-faq-icon{flex-shrink:0;width:24px;height:24px;background:#1553A0;color:#fff;border-radius:50%;display:flex;align-items:center;justify-content:center;font-size:1.1rem;line-height:1;transition:transform .2s,background .2s}\n.jp-faq-q.jp-open .jp-faq-icon{transform:rotate(45deg);background:#007B6E}\n.jp-faq-a{display:none;padding:1.1rem 1.35rem;font-size:.91rem;line-height:1.75;color:#2D3F50;background:#fff;border-top:1px solid #E2EAF4}\n.jp-faq-a.jp-open{display:block}\n.jp-cta{background:linear-gradient(135deg,#071B40,#1553A0 70%,#006DAB);color:#fff;padding:2.75rem 2.5rem;border-radius:14px;text-align:center;margin:3rem 0 0}\n.jp-cta h2{font-family:'Sora',sans-serif;font-size:1.5rem;font-weight:700;color:#fff;border:none;margin:0 0 .85rem;padding:0}\n.jp-cta p{color:rgba(255,255,255,.82);font-size:1rem;max-width:580px;margin:0 auto 1.75rem}\n.jp-cta-btn{display:inline-block;background:#fff;color:#1553A0!important;padding:.85rem 2.25rem;border-radius:7px;font-family:'Sora',sans-serif;font-weight:700;font-size:.95rem;text-decoration:none;border:none!important;transition:background .2s,transform .2s}\n.jp-cta-btn:hover{background:#D4E7FF;transform:translateY(-2px);color:#07193A!important}\n@media(max-width:640px){.jp-hero{padding:2rem 1.5rem}.jp-hero h1{font-size:1.6rem}.jeez-pillar h2{font-size:1.4rem}.jp-cta{padding:2rem 1.5rem}}\n.jeez-pillar [id]{scroll-margin-top:90px}\n<\/style>\n<div class=\"jeez-pillar\">\n<a href=\"https:\/\/jeez-semicon.com\/de\/blog\/The-Complete-Guide-to-Silicon-Wafer-Polishing\/\" target=\"_blank\" class=\"jp-back\">\u2190 Back to: The Complete Guide to Silicon Wafer Polishing<\/a>\n<div class=\"jp-hero\">\n<div class=\"jp-hero-eyebrow\">JEEZ Semiconductor Materials &nbsp;\u00b7&nbsp; Technical Guide &nbsp;\u00b7&nbsp; Updated June 2026<\/div>\n<p class=\"jp-hero-lead\">A detailed technical walkthrough of every stage in the silicon wafer polishing sequence \u2014 lapping, chemical etching, double-side CMP, single-side finish CMP, and process control \u2014 with parameters, quality targets, and inter-stage quality dependencies.<\/p>\n<div class=\"jp-hero-meta\">~2,400 words &nbsp;\u00b7&nbsp; 10-minute read &nbsp;\u00b7&nbsp; Published by JEEZ<\/div>\n<\/div>\n<div class=\"jp-toc\"><div class=\"jp-toc-title\">Inhalts\u00fcbersicht<\/div><ol><li><a href=\"#intro\">Why the Polishing Sequence Matters<\/a><\/li><li><a href=\"#sequence-overview\">Complete Sequence at a Glance<\/a><\/li><li><a href=\"#lapping\">Lapping: Mechanical Flatness Foundation<\/a><\/li><li><a href=\"#etching\">Chemical Etching: Removing Sub-Surface Damage<\/a><\/li><li><a href=\"#dsp\">Double-Side CMP (DSP)<\/a><\/li><li><a href=\"#ssp\">Single-Side Finish CMP (SSP)<\/a><\/li><li><a href=\"#process-control\">Process Control and Key Parameters<\/a><\/li><li><a href=\"#faq\">H\u00e4ufig gestellte Fragen<\/a><\/li><\/ol><\/div>\n\n<section id=\"intro\">\n<h2>Why the Polishing Sequence Is More Than the Sum of Its Steps<\/h2>\n<p>Silicon wafer polishing is a carefully sequenced chain in which each stage prepares the surface for the next \u2014 and in which mistakes propagate forward. Sub-surface crystal damage surviving the etch step will produce haze in CMP. Residual roughness from an under-conditioned DSP pad burdens the finish CMP step with excess material removal and increased defect risk. Understanding the physical purpose of each stage, the parameters that govern it, and the quality handoff criteria between stages is what separates a process engineer from someone who merely operates a tool.<\/p>\n<p>This guide from Jizhi Electronic Technology Co., Ltd. (JEEZ) provides a detailed walkthrough of the complete silicon wafer polishing sequence from lapping through final inspection. It supplements our <a href=\"https:\/\/jeez-semicon.com\/de\/blog\/The-Complete-Guide-to-Silicon-Wafer-Polishing\/\" target=\"_blank\">Complete Guide to Silicon Wafer Polishing<\/a>, which covers the broader CMP landscape in a single reference article.<\/p>\n<\/section>\n<hr class=\"jp-hr\">\n\n<section id=\"sequence-overview\">\n<h2>The Complete Polishing Sequence at a Glance<\/h2>\n<p>The path from a freshly sliced silicon disk to a polished, specification-compliant prime-grade wafer involves up to seven distinct stages. Each is necessary; none may be skipped without sacrificing downstream quality:<\/p>\n<ol class=\"jp-steps\">\n<li><strong>Lapping<\/strong> Mechanically flatten both surfaces; remove bulk of slicing-induced waviness and establish initial TTV below 5 \u03bcm. Removes 30\u201360 \u03bcm per side.<\/li>\n<li><strong>Edge Profiling<\/strong> Round wafer edges to the standardized chamfer profile (SEMI M1) using a diamond grinding wheel; prevents micro-cracking during subsequent handling and polishing.<\/li>\n<li><strong>Chemical Etching<\/strong> Dissolve the sub-surface crystalline damage layer introduced by lapping. Acid etch (HF\/HNO\u2083) removes 10\u201330 \u03bcm isotropically; alkaline etch (KOH) removes the same depth anisotropically along crystal planes.<\/li>\n<li><strong>Double-Side CMP (DSP)<\/strong> Simultaneously polish front and back surfaces to achieve tight global flatness (TTV &lt;1 \u03bcm, bow &lt;40 \u03bcm) and reduce roughness to below 0.5 nm Ra. Removes 10\u201320 \u03bcm per side.<\/li>\n<li><strong>Single-Side Finish CMP (SSP)<\/strong> Final ultra-low-removal-rate polish of the front surface. Removes only 0.5\u20131.5 \u03bcm but achieves Ra &lt;0.1 nm, LPD &lt;30, and haze &lt;0.03 ppm.<\/li>\n<li><strong>Post-CMP Cleaning<\/strong> Multi-step chemical cleaning (SC-1, SC-2, megasonic) removes all slurry residues, organics, and metallic contamination to sub-ppb levels.<\/li>\n<li><strong>Metrology and Final Inspection<\/strong> TTV, SFQR, Ra, LPD, and haze measurements verify compliance with all specification limits before packaging and shipment.<\/li>\n<\/ol>\n<\/section>\n<hr class=\"jp-hr\">\n\n<section id=\"lapping\">\n<h2>Lapping: Mechanical Flatness Foundation<\/h2>\n<p>A rotary lapping machine uses a precision-flat cast iron or ceramic plate rotating at 20\u201360 rpm. The wafer is held in a carrier ring against the plate under 20\u201350 g\/cm\u00b2 load. A free-abrasive slurry of Al\u2082O\u2083 or SiC (3\u201320 \u03bcm grit) in a glycol-water carrier rolls between the plate and wafer in three-body abrasion, plastically fracturing and removing silicon at ~0.5\u20132 \u03bcm\/min per side.<\/p>\n<p>Lapping reduces TTV from the &gt;20 \u03bcm typical of as-sliced wafers to below 3\u20135 \u03bcm, and corrects bow and warp to below 50 \u03bcm. However, the three-body abrasion mechanism leaves a sub-surface damage (SSD) layer 5\u201320 \u03bcm deep of fractured and plastically deformed silicon. This SSD layer must be completely removed by chemical etching before CMP, or crystalline defects will propagate into any epitaxial layers grown on the wafer.<\/p>\n<div class=\"jp-callout slate\">\n<strong>Lapping plate flatness matters.<\/strong> The plate&#8217;s run-out across its radius is transferred directly into every wafer&#8217;s TTV profile. Plates must be periodically re-trued with precision conditioning rings. A plate with more than 2\u20133 \u03bcm of run-out will cap the achievable post-lapping TTV regardless of process conditions.\n<\/div>\n<\/section>\n<hr class=\"jp-hr\">\n\n<section id=\"etching\">\n<h2>Chemical Etching: Removing Sub-Surface Damage<\/h2>\n<p>Wet chemical etching removes the SSD layer from lapping by dissolving silicon without applying mechanical force. Two chemistries are in commercial use, each with distinct surface characteristics:<\/p>\n<div class=\"jp-compare\">\n<div class=\"jp-compare-box\">\n<h4>Acid Etch (HNA)<\/h4>\n<ul>\n<li>HF + HNO\u2083 + CH\u2083COOH, room temperature<\/li>\n<li>Isotropic \u2014 uniform etch rate in all crystal directions<\/li>\n<li>Removes 10\u201330 \u03bcm per side<\/li>\n<li>Produces smooth, bright, rounded surface<\/li>\n<li>Generates NO\u2093 fumes \u2014 requires exhaust scrubbing<\/li>\n<li>Common for 150mm and specialty wafer grades<\/li>\n<\/ul>\n<\/div>\n<div class=\"jp-compare-box\">\n<h4>Alkaline Etch (KOH)<\/h4>\n<ul>\n<li>40\u201360 wt% KOH at 70\u201390\u00b0C<\/li>\n<li>Anisotropic \u2014 {111} planes etch ~100\u00d7 slower than {100}<\/li>\n<li>Removes 10\u201330 \u03bcm per side<\/li>\n<li>Leaves micro-pyramidal surface texture on (100) wafers<\/li>\n<li>Introduces K\u207a contamination \u2192 thorough DI rinse required<\/li>\n<li>Standard for 300mm prime-grade production<\/li>\n<\/ul>\n<\/div>\n<\/div>\n<p>The etch step&#8217;s most critical specification is completeness. An under-etched wafer retains residual crystal damage that manifests as elevated COP density or anomalous removal rate behavior in CMP. Etch depth is monitored by gravimetry (weight loss), with minimum removal set at 3\u00d7 the estimated SSD depth. Over-etching is less harmful but wastes silicon and increases wafer taper risk in the etch bath.<\/p>\n<\/section>\n<hr class=\"jp-hr\">\n\n<section id=\"dsp\">\n<h2>Double-Side CMP (DSP): Stock Removal and Precision Geometry<\/h2>\n<p>In a double-side polishing machine, the wafer rides freely in a thin, precision-machined carrier plate between upper and lower platens, each carrying a polishing pad. Because the wafer floats in the carrier plate&#8217;s hole under uniform pressure from both sides, it polishes simultaneously from top and bottom \u2014 and more importantly, its thicker regions receive higher contact pressure from both pads, driving the self-planarizing geometry correction that defines DSP&#8217;s strength.<\/p>\n<p>Slurry: colloidal silica 80\u2013150 nm D50, 5\u201315 wt%, pH 10.5\u201311.5. Pads: hard polyurethane (Shore D ~65). Applied pressure: 1.5\u20133.5 psi per side. Removal rate: 300\u2013600 nm\/min per side. Total removal: 10\u201320 \u03bcm per side.<\/p>\n<h3>DSP Output Quality Targets (300mm Prime)<\/h3>\n<div class=\"jp-table-wrap\">\n<table class=\"jp-table\">\n<thead><tr><th>Metric<\/th><th>Post-DSP Target<\/th><th>Controlled By<\/th><\/tr><\/thead>\n<tbody>\n<tr><td>TTV<\/td><td>&lt;1.0 \u03bcm<\/td><td>Carrier plate flatness, pad stiffness, pressure uniformity<\/td><\/tr>\n<tr><td>Bogen<\/td><td>&lt;40 \u03bcm<\/td><td>Symmetric removal from both sides; carrier plate geometry<\/td><\/tr>\n<tr><td>Warp<\/td><td>&lt;60 \u03bcm<\/td><td>Same as bow<\/td><\/tr>\n<tr><td>Front\/back Ra<\/td><td>&lt;0.5 nm<\/td><td>Slurry particle size, pad type, pH<\/td><\/tr>\n<tr><td>Haze<\/td><td>&lt;0.5 ppm<\/td><td>Slurry quality, rinse completeness<\/td><\/tr>\n<\/tbody>\n<\/table>\n<\/div>\n<p>For a deep comparison of DSP vs. SSP equipment, process architecture, and application selection, see: <a href=\"https:\/\/jeez-semicon.com\/de\/blog\/Single-Side-vs-Double-Side-Polishing-Which-Is-Right-for-Your-Wafer\/\" target=\"_blank\">Single-Side vs. Double-Side Polishing: Which Is Right for Your Wafer?<\/a>.<\/p>\n<\/section>\n<hr class=\"jp-hr\">\n\n<section id=\"ssp\">\n<h2>Single-Side Finish CMP (SSP): Delivering the Final Surface<\/h2>\n<p>The finish CMP step polishes only the front (device) surface. The wafer is held face-down on the carrier head membrane, which applies a very low, uniform pressure (0.5\u20131.0 psi \/ 3.5\u20137 kPa) against a rotating soft Suba-type pad. Slurry is fine colloidal silica (D50 20\u201350 nm, 0.1\u20132 wt%) or abrasive-free alkaline solution. Removal: 0.5\u20131.5 \u03bcm. Time: 10\u201330 min depending on slurry chemistry and pressure.<\/p>\n<p>Chemical action \u2014 the formation and progressive removal of the silicic acid surface layer \u2014 dominates mechanical abrasion in this regime. The result is progressive smoothing of micro-asperities to below the atomic step level, elimination of haze, and reduction of the LPD count to specification. The SSP step cannot correct SFQR or TTV (removal is too shallow); those parameters are set in the DSP step and preserved here.<\/p>\n<div class=\"jp-callout amber\">\n<strong>Over-polishing during SSP increases roughness.<\/strong> There is a U-shaped relationship between SSP polish time and surface roughness: roughness improves as mechanical damage is removed, but eventually pure alkaline etching begins to roughen crystal facets differently along crystallographic orientations. Timed endpoint control and slurry pH stability are essential to avoiding this regime.\n<\/div>\n<\/section>\n<hr class=\"jp-hr\">\n\n<section id=\"process-control\">\n<h2>Process Control: Key Parameters and Monitoring<\/h2>\n<div class=\"jp-table-wrap\">\n<table class=\"jp-table\">\n<thead><tr><th>Parameter<\/th><th>DSP Range<\/th><th>SSP Range<\/th><th>Effect of Deviation<\/th><\/tr><\/thead>\n<tbody>\n<tr><td>Carrier\/head pressure<\/td><td>1.5\u20133.5 psi<\/td><td>0.5\u20131.0 psi<\/td><td>High: elevated RR, scratch risk; Low: slow RR, possible uniformity issues<\/td><\/tr>\n<tr><td>Platen rotation speed<\/td><td>20\u201340 rpm<\/td><td>30\u201360 rpm<\/td><td>Higher: faster RR; must stay within pad temperature budget<\/td><\/tr>\n<tr><td>Slurry flow rate<\/td><td>200\u2013500 ml\/min<\/td><td>100\u2013250 ml\/min<\/td><td>Too low: starvation, non-uniformity; too high: waste<\/td><\/tr>\n<tr><td>Slurry pH at tool inlet<\/td><td>10.5\u201311.5<\/td><td>9.8\u201310.5<\/td><td>Drift low: RR drop; drift high: haze, COP exposure risk<\/td><\/tr>\n<tr><td>Pad temperature<\/td><td>22\u201332\u00b0C<\/td><td>20\u201328\u00b0C<\/td><td>Higher temp: faster chemical rate; lot-to-lot RR inconsistency if uncontrolled<\/td><\/tr>\n<\/tbody>\n<\/table>\n<\/div>\n<p>Post-CMP cleaning is the step that converts a polished wafer into a shippable substrate. For the full cleaning sequence and its role in final LPD performance, see: <a href=\"https:\/\/jeez-semicon.com\/de\/blog\/Post-CMP-Cleaning-for-Silicon-Wafers-Methods-and-Best-Practices\/\" target=\"_blank\">Post-CMP Cleaning for Silicon Wafers: Methods and Best Practices<\/a>.<\/p>\n<\/section>\n\n\n<div class=\"jp-related\">\n<div class=\"jp-related-title\">Related Articles in This Series<\/div>\n<div class=\"jp-related-links\">\n<a href=\"https:\/\/jeez-semicon.com\/de\/blog\/The-Complete-Guide-to-Silicon-Wafer-Polishing\/\" target=\"_blank\" class=\"jp-rl\"><span class=\"jp-rl-icon\">\ud83d\udcd8<\/span><div><strong>The Complete Guide to Silicon Wafer Polishing<\/strong><span>The full pillar guide \u2014 every dimension of silicon wafer CMP in one place.<\/span><\/div><\/a>\n<a href=\"https:\/\/jeez-semicon.com\/de\/blog\/Single-Side-vs-Double-Side-Polishing-Which-Is-Right-for-Your-Wafer\/\" target=\"_blank\" class=\"jp-rl\"><span class=\"jp-rl-icon\">\u2696\ufe0f<\/span><div><strong>Single-Side vs. Double-Side Polishing: Which Is Right for Your Wafer?<\/strong><span>Compare SSP and DSP equipment, surface outcomes, and application selection.<\/span><\/div><\/a>\n<a href=\"https:\/\/jeez-semicon.com\/de\/blog\/Post-CMP-Cleaning-for-Silicon-Wafers-Methods-and-Best-Practices\/\" target=\"_blank\" class=\"jp-rl\"><span class=\"jp-rl-icon\">\ud83e\uddea<\/span><div><strong>Post-CMP Cleaning for Silicon Wafers: Methods and Best Practices<\/strong><span>SC-1, SC-2, megasonic and Marangoni drying for sub-ppb surface cleanliness.<\/span><\/div><\/a>\n<a href=\"https:\/\/jeez-semicon.com\/de\/blog\/CMP-Slurry-for-Silicon-Wafer-Types-Selection-Best-Practices\/\" target=\"_blank\" class=\"jp-rl\"><span class=\"jp-rl-icon\">\ud83d\udca7<\/span><div><strong>CMP Slurry for Silicon Wafer: Types, Selection &amp; Best Practices<\/strong><span>How to select and optimize slurry for rough and finish polish stages.<\/span><\/div><\/a>\n<\/div><\/div>\n<hr class=\"jp-hr\">\n<section id=\"faq\">\n<h2>H\u00e4ufig gestellte Fragen<\/h2>\n<div class=\"jp-faq\"><div class=\"jp-faq-item\"><div class=\"jp-faq-q\" onclick=\"jeezToggleFaq(this)\">What is the purpose of lapping before CMP in silicon wafer manufacturing?<span class=\"jp-faq-icon\">+<\/span><\/div><div class=\"jp-faq-a\">Lapping establishes the global flatness (TTV) of the wafer after wire-saw slicing, removing 30\u201360 \u03bcm per side to reduce TTV from over 20 \u03bcm to below 5 \u03bcm. Without lapping, the DSP CMP step would need to remove far more material, significantly increasing process time and consumable cost. However, lapping leaves a sub-surface crystal damage layer that must be completely removed by chemical etching before any CMP step.<\/div><\/div>\n<div class=\"jp-faq-item\"><div class=\"jp-faq-q\" onclick=\"jeezToggleFaq(this)\">Why is chemical etching done before CMP rather than just using CMP to remove all damage?<span class=\"jp-faq-icon\">+<\/span><\/div><div class=\"jp-faq-a\">Wet chemical etching removes the sub-surface damage layer from lapping far more efficiently than CMP. Etching dissolves silicon without applying mechanical force, eliminating the fractured crystal layer in minutes. Removing the same depth by CMP would require a much more aggressive, higher-removal-rate slurry incompatible with achieving final surface quality. Chemical etching also prepares a damage-free crystal surface that responds optimally to CMP chemistry.<\/div><\/div>\n<div class=\"jp-faq-item\"><div class=\"jp-faq-q\" onclick=\"jeezToggleFaq(this)\">How much silicon does each CMP stage remove in 300mm wafer production?<span class=\"jp-faq-icon\">+<\/span><\/div><div class=\"jp-faq-a\">Double-side rough CMP (DSP) removes 10\u201320 \u03bcm per side, achieving TTV below 1 \u03bcm. Single-side finish CMP (SSP) removes only 0.5\u20131.5 \u03bcm from the front surface to achieve Ra below 0.1 nm and LPD below 30. Total CMP removal is roughly 20\u201340 \u03bcm from the front surface and 10\u201320 \u03bcm from the back surface across both polishing stages.<\/div><\/div>\n<div class=\"jp-faq-item\"><div class=\"jp-faq-q\" onclick=\"jeezToggleFaq(this)\">What causes SFQR (local site flatness) failure at the wafer polishing stage?<span class=\"jp-faq-icon\">+<\/span><\/div><div class=\"jp-faq-a\">SFQR failures most commonly originate in the DSP step from: carrier plate damage or non-flatness, within-wafer pressure non-uniformity from retaining ring or membrane wear, or systematic removal rate non-uniformity from pad wear patterns. The SSP finish step cannot correct SFQR \u2014 it removes only 0.5\u20131.5 \u03bcm total, insufficient to correct geometric errors. All SFQR control must occur in the DSP step.<\/div><\/div>\n<div class=\"jp-faq-item\"><div class=\"jp-faq-q\" onclick=\"jeezToggleFaq(this)\">What is endpoint detection in silicon wafer CMP and how does it work?<span class=\"jp-faq-icon\">+<\/span><\/div><div class=\"jp-faq-a\">For wafer preparation CMP, endpoint detection primarily refers to monitoring cumulative material removal to stop polishing at the target thickness. Time-based endpoint control is most common: the recipe specifies a polish time calibrated to the desired removal at the measured removal rate. In-situ optical sensors (interferometry through a platen window) or motor current monitors provide real-time removal rate data and can trigger automatic adjustments if the rate drifts outside control limits.<\/div><\/div>\n<\/div>\n<\/section>\n<hr class=\"jp-hr\">\n<div class=\"jp-cta\"><h2>Optimize Your Silicon Wafer Polishing Process with JEEZ<\/h2><p>JEEZ supplies CMP slurries for every silicon wafer polishing stage and provides hands-on process consultation for recipe development, slurry stage-matching, and yield improvement on 200mm and 300mm production platforms.<\/p>\n<a href=\"https:\/\/jeez-semicon.com\/de\/contact\/\" target=\"_blank\" class=\"jp-cta-btn\">Contact JEEZ Technical Team<\/a>\n<\/div>\n<\/div>\n<script type=\"application\/ld+json\">{\"@context\":\"https:\/\/schema.org\",\"@type\":\"FAQPage\",\"mainEntity\":[{\"@type\":\"Question\",\"name\":\"What is the purpose of lapping before CMP in silicon wafer manufacturing?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"Lapping establishes the global flatness (TTV) of the wafer after wire-saw slicing, removing 30\u201360 \u03bcm per side to reduce TTV from over 20 \u03bcm to below 5 \u03bcm. Without lapping, the DSP CMP step would need to remove far more material, significantly increasing process time and consumable cost. However, lapping leaves a sub-surface crystal damage layer that must be completely removed by chemical etching before any CMP step.\"}},{\"@type\":\"Question\",\"name\":\"Why is chemical etching done before CMP rather than just using CMP to remove all damage?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"Wet chemical etching removes the sub-surface damage layer from lapping far more efficiently than CMP. Etching dissolves silicon without applying mechanical force, eliminating the fractured crystal layer in minutes. Removing the same depth by CMP would require a much more aggressive, higher-removal-rate slurry incompatible with achieving final surface quality. Chemical etching also prepares a damage-free crystal surface that responds optimally to CMP chemistry.\"}},{\"@type\":\"Question\",\"name\":\"How much silicon does each CMP stage remove in 300mm wafer production?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"Double-side rough CMP (DSP) removes 10\u201320 \u03bcm per side, achieving TTV below 1 \u03bcm. Single-side finish CMP (SSP) removes only 0.5\u20131.5 \u03bcm from the front surface to achieve Ra below 0.1 nm and LPD below 30. Total CMP removal is roughly 20\u201340 \u03bcm from the front surface and 10\u201320 \u03bcm from the back surface across both polishing stages.\"}},{\"@type\":\"Question\",\"name\":\"What causes SFQR (local site flatness) failure at the wafer polishing stage?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"SFQR failures most commonly originate in the DSP step from: carrier plate damage or non-flatness, within-wafer pressure non-uniformity from retaining ring or membrane wear, or systematic removal rate non-uniformity from pad wear patterns. The SSP finish step cannot correct SFQR \u2014 it removes only 0.5\u20131.5 \u03bcm total, insufficient to correct geometric errors. All SFQR control must occur in the DSP step.\"}},{\"@type\":\"Question\",\"name\":\"What is endpoint detection in silicon wafer CMP and how does it work?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"For wafer preparation CMP, endpoint detection primarily refers to monitoring cumulative material removal to stop polishing at the target thickness. Time-based endpoint control is most common: the recipe specifies a polish time calibrated to the desired removal at the measured removal rate. In-situ optical sensors (interferometry through a platen window) or motor current monitors provide real-time removal rate data and can trigger automatic adjustments if the rate drifts outside control limits.\"}}]}<\/script>\n<script>\nfunction jeezToggleFaq(el){\n  var a=el.nextElementSibling,o=a.classList.contains('jp-open');\n  document.querySelectorAll('.jp-faq-a').forEach(function(x){x.classList.remove('jp-open')});\n  document.querySelectorAll('.jp-faq-q').forEach(function(x){x.classList.remove('jp-open')});\n  if(!o){a.classList.add('jp-open');el.classList.add('jp-open');}\n}\n<\/script>","protected":false},"excerpt":{"rendered":"<p>\u2190 Back to: The Complete Guide to Silicon Wafer Polishing JEEZ Semiconductor Materials &nbsp;\u00b7&nbsp; Technical Guide &nbsp;\u00b7&nbsp; Updated June 2026 A detailed technical walkthrough of every stage in the silicon  &#8230;<\/p>","protected":false},"author":1,"featured_media":2283,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[9,59],"tags":[],"class_list":["post-2281","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-blog","category-industry"],"acf":[],"_links":{"self":[{"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/posts\/2281","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/comments?post=2281"}],"version-history":[{"count":2,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/posts\/2281\/revisions"}],"predecessor-version":[{"id":2284,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/posts\/2281\/revisions\/2284"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/media\/2283"}],"wp:attachment":[{"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/media?parent=2281"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/categories?post=2281"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/tags?post=2281"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}