{"id":2386,"date":"2026-06-24T10:15:18","date_gmt":"2026-06-24T02:15:18","guid":{"rendered":"https:\/\/jeez-semicon.com\/?p=2386"},"modified":"2026-06-24T10:15:18","modified_gmt":"2026-06-24T02:15:18","slug":"cmp-polishing-pads-types-structure-role-in-wafer-planarization","status":"publish","type":"post","link":"https:\/\/jeez-semicon.com\/de\/blog\/cmp-polishing-pads-types-structure-role-in-wafer-planarization\/","title":{"rendered":"CMP Polishing Pads: Types, Structure &amp; Role in Wafer Planarization"},"content":{"rendered":"<!-- JEEZ | Cluster 05 | CMP Polishing Pads: Types, Structure & Role in Wafer Planarization -->\n<link rel=\"preconnect\" href=\"https:\/\/fonts.googleapis.com\">\n<link rel=\"preconnect\" href=\"https:\/\/fonts.gstatic.com\" crossorigin>\n<link href=\"https:\/\/fonts.googleapis.com\/css2?family=Syne:wght@600;700;800&#038;family=Inter:ital,wght@0,400;0,500;0,600;1,400&#038;display=swap\" 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h3{font-family:'Syne',sans-serif;color:#fff;font-size:1.4rem;font-weight:800;margin:0 0 10px;position:relative}\n.jeez-pl .jz-cta-box p{color:rgba(255,255,255,.74);max-width:520px;margin:0 auto 26px;font-size:14.5px;position:relative}\n.jeez-pl .jz-btn{display:inline-block;background:var(--jz-teal);color:#fff;font-size:14.5px;font-weight:700;padding:13px 36px;border-radius:8px;text-decoration:none;transition:background .15s,transform .1s}\n.jeez-pl .jz-btn:hover{background:var(--jz-teal-dark);color:#fff;text-decoration:none;transform:translateY(-2px)}\n.jeez-pl .jz-faq-list{margin-top:18px}\n.jeez-pl .jz-faq-item{border:1px solid var(--jz-border);border-radius:var(--jz-radius);margin-bottom:12px;overflow:hidden}\n.jeez-pl .jz-faq-q{background:var(--jz-bg);padding:15px 20px;font-weight:600;font-size:14.5px;color:var(--jz-navy);border-left:4px solid var(--jz-teal);line-height:1.4}\n.jeez-pl .jz-faq-a{padding:14px 20px 16px;font-size:14px;color:var(--jz-text);line-height:1.74;border-top:1px solid var(--jz-border)}\n@media(max-width:680px){.jeez-pl .jz-hero{padding:28px 22px}.jeez-pl .jz-toc ol{columns:1}.jeez-pl .jz-grid-2{grid-template-columns:1fr}.jeez-pl .jz-cta-box{padding:32px 22px}.jeez-pl h2{font-size:1.3rem}}\n<\/style>\n\n<div class=\"jeez-pl\">\n\n<a class=\"jz-back-link\" href=\"https:\/\/jeez-semicon.com\/de\/blog\/Planarization-in-Semiconductor-Manufacturing-Complete-Guide\/\" target=\"_blank\" rel=\"noopener noreferrer\">\u2190 Back to Complete Planarization Guide<\/a>\n\n<div class=\"jz-hero\">\n  <span class=\"jz-hero-eyebrow\">CMP Consumables \u2014 Polishing Pads<\/span>\n  <p class=\"jz-hero-lead\">The CMP polishing pad is the mechanical foundation of the planarization process. Its hardness, porosity, groove geometry, and surface texture directly determine how uniformly material is removed across the wafer \u2014 and how long the process can maintain that performance before the pad needs replacement. This guide covers pad materials, two-layer and fixed-abrasive designs, groove pattern engineering, conditioning theory, pad lifetime management, and selection criteria for each major CMP application.<\/p>\n  <div class=\"jz-hero-meta\">\n    <span>Updated: <strong>June 2026<\/strong><\/span>\n    <span class=\"jz-pipe\">|<\/span>\n    <span>By <strong>JEEZ Technical Team<\/strong><\/span>\n  <\/div>\n<\/div>\n\n<nav class=\"jz-toc\" aria-label=\"Inhalts\u00fcbersicht\">\n  <span class=\"jz-toc-label\">Inhalts\u00fcbersicht<\/span>\n  <ol>\n    <li><a href=\"#pad-role\">The Role of the Polishing Pad in CMP<\/a><\/li>\n    <li><a href=\"#pad-materials\">Pad Materials and Manufacturing<\/a><\/li>\n    <li><a href=\"#hard-vs-soft\">Hard vs. Soft Pads: The Fundamental Trade-off<\/a><\/li>\n    <li><a href=\"#two-layer\">Two-Layer Stacked Pad Design<\/a><\/li>\n    <li><a href=\"#groove-patterns\">Groove Patterns and Slurry Transport<\/a><\/li>\n    <li><a href=\"#conditioning\">Pad Conditioning: Theory and Practice<\/a><\/li>\n    <li><a href=\"#pad-wear\">Pad Wear, Lifetime, and End-of-Life<\/a><\/li>\n    <li><a href=\"#fixed-abrasive\">Fixed Abrasive Pads<\/a><\/li>\n    <li><a href=\"#selection\">Pad Selection Guide by Application<\/a><\/li>\n    <li><a href=\"#jeez-pads\">JEEZ CMP Polishing Pads<\/a><\/li>\n    <li><a href=\"#faq\">H\u00e4ufig gestellte Fragen<\/a><\/li>\n  <\/ol>\n<\/nav>\n\n\n<section id=\"pad-role\">\n  <h2><span class=\"jz-sn\">01<\/span>The Role of the Polishing Pad in CMP<\/h2>\n  <p>The polishing pad performs three simultaneous functions in the CMP process: it distributes the abrasive slurry across the wafer\u2013pad interface; it applies the controlled contact pressure that drives material removal via Preston&#8217;s equation (MRR = K<sub>p<\/sub> \u00d7 P \u00d7 V); and it provides the mechanical compliance that allows the pad to conform to wafer-scale bow while maintaining local contact with surface features at the micro-scale. No other consumable in the CMP process has as complex or as multi-functional a role.<\/p>\n  <p>The pad properties interact with the slurry chemistry in ways that make the two consumables inseparable from a process performance perspective. Changing the pad hardness, groove pattern, or conditioning protocol changes the effective slurry delivery rate to the interface, the local contact pressure distribution, and the removal rate uniformity \u2014 even if the slurry composition is unchanged. For this reason, pad and slurry qualification are always performed together in new process development.<\/p>\n\n  <div class=\"jz-callout gold\">\n    <span class=\"jz-callout-tag\">Key Insight<\/span>\n    <p>A pad that is too soft conforms to the underlying surface topography \u2014 removing material uniformly from both elevated and recessed areas \u2014 and loses the self-leveling behavior that makes CMP capable of global planarization. A pad that is too hard does not conform to wafer-scale bow, creating non-uniform contact pressure and poor WIWNU. The optimal pad hardness is the minimum necessary to achieve global planarization while still accommodating wafer bow.<\/p>\n  <\/div>\n<\/section>\n\n\n<section id=\"pad-materials\">\n  <h2><span class=\"jz-sn\">02<\/span>Pad Materials and Manufacturing<\/h2>\n  <p>The overwhelming majority of production CMP pads are manufactured from polyurethane \u2014 a polymer family that offers an exceptionally wide range of tunable mechanical properties (from Shore A 20 to Shore D 80), excellent chemical resistance to CMP slurry chemistries (acids, bases, peroxides, chelating agents), and the ability to be engineered with controlled porosity through foaming processes.<\/p>\n\n  <h3>Polyurethane Foam CMP Pads<\/h3>\n  <p>CMP polishing pads are manufactured by casting polyurethane foam in large-format blocks, then precision-slicing the blocks into discs of controlled thickness. The foaming process introduces micro-pores (10\u201350 \u00b5m diameter) distributed throughout the polyurethane matrix. These micropores serve two critical functions:<\/p>\n  <ul>\n    <li><strong>Slurry storage and transport:<\/strong> The open-cell micropores act as local reservoirs that absorb and hold slurry at the pad surface, continuously supplying fresh abrasive and chemical agent to the polishing interface as the pad rotates across the wafer.<\/li>\n    <li><strong>Mechanical compliance modulation:<\/strong> By controlling the micropore volume fraction (typically 30\u201360% by volume) and cell size distribution, the pad manufacturer can tune the effective elastic modulus of the pad surface layer independently of the bulk polyurethane chemistry.<\/li>\n  <\/ul>\n  <p>After slicing, pads are precision-machined to the target thickness (typically 1.5\u20133.5 mm for the top layer) and groove patterns are machined into the surface by CNC cutting. The back surface receives a pressure-sensitive adhesive layer for attachment to the platen.<\/p>\n\n  <h3>Pad Hardness and Shore D Scale<\/h3>\n  <p>CMP pad hardness is measured on the Shore D durometer scale. Hard pads used for global planarization (ILD CMP, STI CMP) typically have Shore D values of 55\u201365. Soft pads used for buffing steps or ultra-low-k applications have Shore D values of 25\u201345. The Shore D measurement is taken on the bulk pad material; the effective hardness at the polishing interface is modified by the micropore structure and the groove geometry, making the macroscopic Shore D only a starting approximation of the pad&#8217;s actual mechanical behavior at the wafer surface.<\/p>\n<\/section>\n\n\n<section id=\"hard-vs-soft\">\n  <h2><span class=\"jz-sn\">03<\/span>Hard vs. Soft Pads: The Fundamental Trade-off<\/h2>\n\n  <div class=\"jz-table-wrap\">\n    <table>\n      <thead>\n        <tr><th>Eigentum<\/th><th>Hard Pad (Shore D 55\u201365)<\/th><th>Soft Pad (Shore D 25\u201345)<\/th><\/tr>\n      <\/thead>\n      <tbody>\n        <tr><td>Global planarization capability<\/td><td>Excellent \u2014 maintains contact primarily with elevated features<\/td><td>Poor \u2014 conforms to topography, removes uniformly from all heights<\/td><\/tr>\n        <tr><td>WIWNU performance<\/td><td>&lt;1% (with multi-zone carrier head)<\/td><td>3\u20138% (topography-following)<\/td><\/tr>\n        <tr><td>Surface defect (scratch) risk<\/td><td>Higher (harder contact)<\/td><td>Lower (compliant contact)<\/td><\/tr>\n        <tr><td>Dishing risk<\/td><td>Higher at high pressure<\/td><td>Lower (conforms to feature)<\/td><\/tr>\n        <tr><td>Wafer bow compensation<\/td><td>Poor alone (requires soft sublayer)<\/td><td>Gut<\/td><\/tr>\n        <tr><td>Typical applications<\/td><td>ILD CMP, STI CMP, W CMP (global planarization modules)<\/td><td>Cu buff, ULK CMP, final planarization, hybrid bonding prep<\/td><\/tr>\n        <tr><td>Use in 2-layer stack?<\/td><td>Top layer<\/td><td>Bottom sublayer (or standalone for buff)<\/td><\/tr>\n      <\/tbody>\n    <\/table>\n  <\/div>\n  <p>The fundamental physics dictates that only a pad hard enough to bridge across surface recesses \u2014 maintaining preferential contact with elevated features \u2014 can deliver global planarization. A soft pad, which deforms and fills in around individual features, polishes them at approximately the same rate as the surrounding field, preserving rather than correcting the local topography.<\/p>\n<\/section>\n\n\n<section id=\"two-layer\">\n  <h2><span class=\"jz-sn\">04<\/span>Two-Layer Stacked Pad Design<\/h2>\n  <p>The two-layer stacked pad is the production standard for all critical global planarization CMP applications \u2014 ILD, STI, W plug, and copper bulk removal. It resolves the apparent contradiction between needing a hard pad for global planarization and a compliant pad for wafer-scale bow accommodation, by separating these two functions into two distinct layers:<\/p>\n\n  <h4>Hard Top Layer (Polishing Layer)<\/h4>\n  <p>The top layer \u2014 directly contacting the wafer surface \u2014 is a hard microporous polyurethane foam (Shore D 55\u201365, typical thickness 1.5\u20132.5 mm). Its rigidity ensures that only the highest surface features on the wafer make significant contact with the pad, producing the differential contact pressure that drives global planarization. Groove patterns are machined into its upper surface. The micropores open at the surface provide slurry storage and transport.<\/p>\n\n  <h4>Soft Sublayer (Compliance Layer)<\/h4>\n  <p>The sublayer \u2014 bonded to the bottom of the hard top layer and to the platen surface \u2014 is a soft, compressible foam or felt (Shore A 20\u201340, thickness 0.8\u20131.5 mm). It provides mechanical compliance that allows the two-layer pad assembly to conform to the global bow and warp of a 300 mm silicon wafer (typically \u00b130\u201380 \u00b5m bow) without creating edge-roll-off effects or center-heavy contact pressure profiles. The sublayer also damps mechanical vibrations from the platen drive that could create periodic polishing non-uniformity (&#8220;chatter marks&#8221;) on the wafer surface.<\/p>\n\n  <div class=\"jz-callout blue\">\n    <span class=\"jz-callout-tag\">Two-Layer Advantages<\/span>\n    <p>The two-layer design delivers: global planarization from the hard top layer + wafer bow accommodation from the soft sublayer + long pad life (hard polyurethane wears slowly) + stable process performance over many wafer polishing runs. The pad stack is mounted to the platen as a single assembly and replaced together when the top layer reaches end-of-life criteria.<\/p>\n  <\/div>\n<\/section>\n\n\n<section id=\"groove-patterns\">\n  <h2><span class=\"jz-sn\">05<\/span>Groove Patterns and Slurry Transport<\/h2>\n  <p>The groove pattern machined into the top surface of a CMP pad is one of the most important determinants of slurry distribution uniformity across the wafer. Without grooves, the pad surface would create a hydrodynamic boundary layer that prevents fresh slurry from reaching the center of the wafer at production rotation speeds, producing severe center-to-edge removal rate non-uniformity (center starvation). Grooves provide channels through which slurry can flow across the pad surface driven by centrifugal force and pressure differentials, continuously refreshing the slurry film at every point of the wafer\u2013pad contact area.<\/p>\n\n  <h3>Common Groove Pattern Designs<\/h3>\n\n  <div class=\"jz-grid-2\">\n    <div class=\"jz-card\">\n      <h4>Concentric Ring Grooves<\/h4>\n      <p>Circular grooves concentric with the pad center. Simple, symmetric design. Provides good radial slurry distribution. Limitation: does not provide circumferential slurry transport, creating potential &#8220;dry patches&#8221; between rings at high speeds. Used in legacy and legacy-generation CMP applications.<\/p>\n    <\/div>\n    <div class=\"jz-card\">\n      <h4>X-Y Grid (Perforated) Grooves<\/h4>\n      <p>A square grid of intersecting horizontal and vertical grooves that divides the pad surface into individual &#8220;islands&#8221; of active polishing area. The grid ensures slurry access to every point on the pad from multiple directions. Standard for high-uniformity applications including Cu CMP and STI CMP. Grid pitch (spacing between groove centerlines) and groove width\/depth are key design parameters.<\/p>\n    <\/div>\n    <div class=\"jz-card\">\n      <h4>Spiral Grooves<\/h4>\n      <p>Archimedean spiral grooves extending from the pad center to the edge. Provide inherently superior slurry distribution due to the curved channel geometry that actively pumps slurry centrifugally from center to edge during pad rotation. Used in advanced copper CMP applications where within-wafer uniformity targets are most demanding.<\/p>\n    <\/div>\n    <div class=\"jz-card\">\n      <h4>Hybrid \/ Asymmetric Patterns<\/h4>\n      <p>Combinations of radial, concentric, and grid elements optimized for specific slurry rheology and rotation speed combinations. Custom-engineered by pad manufacturers for specific CMP applications or tool platforms. The trend in advanced node pad design is toward proprietary hybrid groove patterns optimized for specific applications through computational fluid dynamics (CFD) modeling of slurry transport.<\/p>\n    <\/div>\n  <\/div>\n\n  <p>Groove dimensions \u2014 width (typically 0.5\u20131.5 mm), depth (0.4\u20131.2 mm), and pitch (spacing 1.5\u20135 mm) \u2014 are optimized for specific slurry viscosities, rotation speeds, and flow rates. Deeper grooves hold more slurry but reduce the available pad contact area; shallower grooves maximize contact area but may starve the interface at high rotation speeds.<\/p>\n<\/section>\n\n\n<section id=\"conditioning\">\n  <h2><span class=\"jz-sn\">06<\/span>Pad Conditioning: Theory and Practice<\/h2>\n  <p>Pad conditioning is one of the most critical and often underappreciated aspects of CMP process control. Without continuous conditioning, CMP performance would drift irreversibly over each pad&#8217;s lifetime as the polishing surface degrades \u2014 and pad-to-pad process reproducibility would be impossible to achieve.<\/p>\n\n  <h3>The Pad Glazing Mechanism<\/h3>\n  <p>During CMP, the mechanical interaction between the wafer surface and pad asperities, combined with slurry particle and film debris accumulation, progressively degrades the pad surface. Polishing by-products (abraded film material, reacted chemical compounds) fill the pad micropores. The surface asperities \u2014 the micro-scale protrusions that make the critical contact with the wafer \u2014 are flattened and rounded by repeated mechanical contact. The net result is &#8220;pad glazing&#8221;: the polishing surface becomes smooth, dense, and poorly wetting \u2014 completely unable to transport slurry effectively or maintain contact pressure at feature apexes. A glazed pad shows 50\u201390% reduction in MRR compared to a freshly conditioned pad, and severely degraded WIWNU.<\/p>\n\n  <h3>Diamond Conditioning Disk Operation<\/h3>\n  <p>The conditioning disk \u2014 a stainless steel or titanium disc (4\u20136 inch diameter) with CVD-deposited synthetic diamond crystals (300\u2013500 \u00b5m average protrusion height) distributed across its lower surface \u2014 is pressed against the rotating pad surface with controlled force (typically 1\u20138 lbs) while the disk sweeps back and forth across the pad radius. The diamond crystals abrade the top surface of the pad, removing the glazed layer and re-exposing the fresh open-pore microstructure below. The reconstituted surface has a defined population of sharp asperities that efficiently contact the wafer and transport slurry \u2014 restoring the pad to its specification MRR and WIWNU performance.<\/p>\n\n  <h3>In-Situ vs. Ex-Situ-Konditionierung<\/h3>\n  <ul>\n    <li><strong>In-situ conditioning:<\/strong> The conditioning disk operates simultaneously with wafer polishing \u2014 while the wafer is on the pad. Maintains nearly constant pad state throughout the polishing run. Requires careful optimization of conditioning force and sweep rate to avoid pad wear that is faster than the desired pad lifetime. Standard for processes where run-to-run MRR stability is the top priority.<\/li>\n    <li><strong>Ex-situ-Konditionierung:<\/strong> The conditioning disk operates between wafers (no wafer on pad). Allows independent optimization of conditioning parameters without the constraint of not damaging the wafer. Results in some MRR drift between successive wafer polishing runs. Often used in combination with in-situ conditioning.<\/li>\n  <\/ul>\n\n  <h3>Conditioning Parameters and Their Effects<\/h3>\n  <div class=\"jz-table-wrap\">\n    <table>\n      <thead>\n        <tr><th>Conditioning Parameter<\/th><th>Higher Value Effect<\/th><th>Lower Value Effect<\/th><\/tr>\n      <\/thead>\n      <tbody>\n        <tr><td>Conditioning disk force (lbs)<\/td><td>Faster pad surface refresh; higher pad wear rate; potentially rougher pad texture<\/td><td>Slower pad wear; risk of glazing if too low; more stable pad properties<\/td><\/tr>\n        <tr><td>Conditioning sweep speed (mm\/s)<\/td><td>More uniform conditioning across pad radius; lower dwell time per zone<\/td><td>Higher dwell time; may create center-heavy conditioning and pad texture gradient<\/td><\/tr>\n        <tr><td>Conditioning disk speed (rpm)<\/td><td>Higher diamond coverage per sweep; more uniform diamond wear<\/td><td>Lower coverage; risk of ring patterns on pad surface<\/td><\/tr>\n        <tr><td>Conditioning duty cycle (%)<\/td><td>Maintains fresher pad state; higher pad wear rate; more slurry dilution<\/td><td>Lower pad consumption; allows some glazing between conditioning intervals<\/td><\/tr>\n      <\/tbody>\n    <\/table>\n  <\/div>\n<\/section>\n\n\n<section id=\"pad-wear\">\n  <h2><span class=\"jz-sn\">07<\/span>Pad Wear, Lifetime, and End-of-Life Criteria<\/h2>\n  <p>Polishing pads wear continuously during CMP \u2014 both from the mechanical interaction with the wafer surface and from the abrasion of the conditioning disk. The thickness of the top layer decreases over the pad&#8217;s useful life, and when the grooves become too shallow (groove depth depleted) or the pad surface properties change sufficiently to cause systematic WIWNU degradation, the pad reaches end-of-life and must be replaced.<\/p>\n\n  <h3>Pad Lifetime Drivers<\/h3>\n  <ul>\n    <li><strong>Conditioning aggressiveness:<\/strong> The conditioning disk removes material from the pad surface with each sweep. Higher conditioning force and duty cycle accelerate pad wear. The pad wear rate must be balanced against the need to maintain fresh surface properties.<\/li>\n    <li><strong>Polishing process:<\/strong> Hard film polishing (tungsten, SiC) causes faster mechanical pad wear than soft film polishing (copper buff). High-pressure recipes accelerate wear relative to low-pressure gentle-buff applications.<\/li>\n    <li><strong>Pad material:<\/strong> Higher-durometer polyurethane pads wear more slowly but may require more aggressive conditioning to maintain surface texture.<\/li>\n  <\/ul>\n\n  <h3>End-of-Life Indicators<\/h3>\n  <p>Pad end-of-life is typically determined by monitoring: (1) pad thickness (laser profilometry or contact gauge), with replacement when the top layer reaches a minimum groove depth threshold (typically when groove depth falls below 60% of initial specification); (2) systematic WIWNU drift that cannot be corrected by conditioning parameter adjustment; or (3) fixed-usage lifetime (total polished wafer count or total polishing time) established during pad qualification. Some advanced fabs implement real-time pad surface health monitoring using in-situ optical profilometry or acoustic emission sensors to detect pad degradation before it impacts wafer yield.<\/p>\n<\/section>\n\n\n<section id=\"fixed-abrasive\">\n  <h2><span class=\"jz-sn\">08<\/span>Fixed Abrasive Pads<\/h2>\n  <p>Fixed abrasive pads represent an alternative pad architecture where the abrasive particles \u2014 typically CeO\u2082 or Al\u2082O\u2083 \u2014 are permanently embedded in the pad matrix in a controlled, uniform distribution, rather than being delivered as a separate slurry. These pads are used in conjunction with a slurry-free or minimal-chemistry liquid (an &#8220;enabling fluid&#8221;) that provides the chemical component of CMP without the abrasive particles.<\/p>\n  <p>The primary advantage of fixed abrasive pads is dramatically reduced particle defect density: because the abrasive particles are fixed in the matrix, they cannot form large agglomerates that would scratch the wafer surface. This makes fixed abrasive pads the preferred choice for: post-STI silicon surface finishing (where scratch-free silicon is required before gate oxide growth); advanced copper CMP buff steps; and hybrid bonding surface preparation (where Ra &lt; 0.3 nm and zero scratches are mandatory for void-free bond formation).<\/p>\n  <p>The limitation of fixed abrasive pads is their lower MRR compared to free-abrasive slurry (abrasive replenishment is limited by the fixed particle density in the pad matrix), faster pad wear rate (abrasive particles are consumed with each use), and higher unit cost. They are therefore used selectively for applications where defect performance, not throughput, is the primary optimization target.<\/p>\n<\/section>\n\n\n<section id=\"selection\">\n  <h2><span class=\"jz-sn\">09<\/span>Pad Selection Guide by CMP Application<\/h2>\n  <div class=\"jz-table-wrap\">\n    <table>\n      <thead>\n        <tr><th>CMP Application<\/th><th>Recommended Pad Type<\/th><th>H\u00e4rte (Shore D)<\/th><th>Rillenmuster<\/th><th>Key Selection Criteria<\/th><\/tr>\n      <\/thead>\n      <tbody>\n        <tr><td><strong>Oxide ILD CMP<\/strong><\/td><td>Two-layer: hard top + soft sub<\/td><td>55\u201365 (top)<\/td><td>Concentric or X-Y grid<\/td><td>Global planarization, WIWNU &lt;2%, low oxide loss rate<\/td><\/tr>\n        <tr><td><strong>STI CMP<\/strong><\/td><td>Two-layer: hard top + soft sub<\/td><td>55\u201362 (top)<\/td><td>X-Y grid or spiral<\/td><td>Global planarity, compatible with ceria slurry, low nitride loss<\/td><\/tr>\n        <tr><td><strong>Wolfram CMP<\/strong><\/td><td>Two-layer: hard top + soft sub<\/td><td>58\u201365 (top)<\/td><td>X-Y grid<\/td><td>Acid resistance (pH 2\u20134), plug dishing control, high MRR<\/td><\/tr>\n        <tr><td><strong>Cu CMP Step 1<\/strong><\/td><td>Two-layer: hard top + soft sub<\/td><td>52\u201360 (top)<\/td><td>Spiral or X-Y grid<\/td><td>Cu MRR, barrier selectivity, low dishing<\/td><\/tr>\n        <tr><td><strong>Cu CMP Barrier\/Buff<\/strong><\/td><td>Single soft or fixed abrasive<\/td><td>30\u201345<\/td><td>Fine grid or smooth<\/td><td>Low scratching, low dishing, barrier clearance, Ra &lt;0.5 nm<\/td><\/tr>\n        <tr><td><strong>Hybrid Bonding Prep<\/strong><\/td><td>Fixed abrasive or ultra-soft<\/td><td>25\u201340<\/td><td>Fine grid or smooth<\/td><td>Ra &lt;0.3 nm, zero scratches, Cu step &lt;2 nm<\/td><\/tr>\n        <tr><td><strong>SiC CMP<\/strong><\/td><td>Hard pad + specialized chemistry<\/td><td>60\u201370<\/td><td>X-Y grid<\/td><td>Chemical resistance to Fenton chemistry, sustained MRR<\/td><\/tr>\n      <\/tbody>\n    <\/table>\n  <\/div>\n\n  <a class=\"jz-more\" href=\"https:\/\/jeez-semicon.com\/de\/blog\/CMP-Slurry-for-Semiconductor-Planarization-Chemistry-Types-Selection\/\" target=\"_blank\" rel=\"noopener noreferrer\">\n    <span>Related: CMP Slurry for Semiconductor Planarization \u2014 Chemistry, Types &amp; Selection<\/span>\n    <span class=\"jz-more-arrow\">\u2192<\/span>\n  <\/a>\n<\/section>\n\n\n<section id=\"jeez-pads\">\n  <h2><span class=\"jz-sn\">10<\/span>JEEZ CMP Polishing Pads<\/h2>\n  <p>JEEZ (Jizhi Electronic Technology Co., Ltd.) manufactures CMP polishing pads engineered for the full spectrum of semiconductor planarization applications. As a direct manufacturer, JEEZ produces pads in both single-layer and two-layer stacked configurations, covering oxide ILD, STI, tungsten plug, and copper CMP applications. All JEEZ pads are manufactured from high-purity polyurethane foam with controlled micropore structure, precision-machined groove patterns (X-Y grid, concentric, and spiral variants), and pressure-sensitive adhesive for platen mounting.<\/p>\n  <p>JEEZ pad products are validated for chemical compatibility with the full range of JEEZ CMP slurry products, and process qualification data \u2014 including MRR, WIWNU, conditioning protocol recommendations, and pad lifetime benchmarks \u2014 is available from JEEZ application engineering teams for major CMP tool platforms. JEEZ also supplies <strong>absorption and backing films<\/strong> for carrier head assemblies, completing the full consumable package for CMP tool operation.<\/p>\n<\/section>\n\n\n<div class=\"jz-cta-box\">\n  <h3>Get Technical Specifications for JEEZ CMP Polishing Pads<\/h3>\n  <p>Contact JEEZ to request pad datasheets, conditioning protocol recommendations, or to discuss pad qualification for your specific CMP module and tool platform.<\/p>\n  <a class=\"jz-btn\" href=\"https:\/\/jeez-semicon.com\/de\/contact\/\" target=\"_blank\" rel=\"noopener noreferrer\">Contact JEEZ \u2192<\/a>\n<\/div>\n\n\n<section id=\"faq\">\n  <h2><span class=\"jz-sn\">FAQ<\/span>H\u00e4ufig gestellte Fragen<\/h2>\n  <div class=\"jz-faq-list\">\n    <div class=\"jz-faq-item\">\n      <div class=\"jz-faq-q\">What material is used for CMP polishing pads?<\/div>\n      <div class=\"jz-faq-a\">The vast majority of production CMP polishing pads are manufactured from polyurethane foam. Polyurethane is chosen for its wide range of tunable mechanical hardness (Shore D 25\u201370), chemical resistance to CMP slurry chemistries (acids, bases, H\u2082O\u2082, chelating agents), and controllable micropore structure. The micropores (10\u201350 \u00b5m diameter) serve dual functions: they store and transport slurry to the polishing interface, and they allow the effective pad hardness to be tuned by controlling the foam density and cell size distribution.<\/div>\n    <\/div>\n    <div class=\"jz-faq-item\">\n      <div class=\"jz-faq-q\">What is the difference between a hard CMP pad and a soft CMP pad?<\/div>\n      <div class=\"jz-faq-a\">Hard pads (Shore D 55\u201365) maintain contact primarily with elevated surface features \u2014 providing the differential contact pressure that enables global planarization. They are used for ILD, STI, and tungsten CMP where achieving WIWNU &lt;1\u20132% is the priority. Soft pads (Shore D 25\u201345) conform to surface topography and polish more uniformly across all feature heights \u2014 sacrificing global planarization capability for lower scratch rates and reduced dishing. They are used for copper buff, ULK dielectric CMP, and hybrid bonding surface preparation. The two-layer pad design combines both: a hard top layer for planarization + a soft sublayer for wafer bow compliance.<\/div>\n    <\/div>\n    <div class=\"jz-faq-item\">\n      <div class=\"jz-faq-q\">Why is pad conditioning necessary in CMP?<\/div>\n      <div class=\"jz-faq-a\">Pad conditioning is necessary because the pad surface degrades rapidly during polishing \u2014 the micropores fill with polishing debris, and the surface asperities that make contact with the wafer are mechanically flattened and rounded. This &#8220;glazing&#8221; causes the MRR to drop by 50\u201390% and WIWNU to worsen dramatically. A diamond conditioning disk abrades the pad surface between (or during) polishing runs, removing the degraded top layer and re-exposing fresh open-pore structure and sharp asperities. Without conditioning, consistent CMP performance over multiple wafers is impossible.<\/div>\n    <\/div>\n    <div class=\"jz-faq-item\">\n      <div class=\"jz-faq-q\">When should a CMP pad be replaced?<\/div>\n      <div class=\"jz-faq-a\">CMP pad replacement is triggered by: (1) groove depth depletion \u2014 when grooves wear below ~60% of their original depth (monitored by pad profilometry), slurry distribution uniformity degrades; (2) systematic WIWNU drift \u2014 when post-CMP uniformity measurements show a trend that cannot be corrected by conditioning adjustment, indicating fundamental pad property change; or (3) reaching the qualified wafer count or process time limit established during pad qualification. Some fabs use real-time in-situ pad health monitoring (acoustic emission, optical profilometry) to optimize pad replacement timing without using fixed-lifetime limits.<\/div>\n    <\/div>\n    <div class=\"jz-faq-item\">\n      <div class=\"jz-faq-q\">What are fixed abrasive pads and when are they used?<\/div>\n      <div class=\"jz-faq-a\">Fixed abrasive pads embed CeO\u2082 or Al\u2082O\u2083 abrasive particles permanently in the pad matrix, used with a slurry-free chemical liquid rather than conventional abrasive slurry. They deliver dramatically lower particle defect density than free-abrasive systems because the fixed particles cannot agglomerate into large clusters that cause scratching. Fixed abrasive pads are used in applications where surface defect performance is the primary concern: post-STI silicon finishing, copper CMP buff steps, and \u2014 most critically \u2014 hybrid bonding surface preparation, where Ra &lt;0.3 nm and zero scratches are required for void-free Cu-to-Cu and oxide-to-oxide direct bonding.<\/div>\n    <\/div>\n  <\/div>\n<\/section>\n\n<\/div>\n\n<script type=\"application\/ld+json\">\n{\n  \"@context\": \"https:\/\/schema.org\",\n  \"@type\": \"FAQPage\",\n  \"mainEntity\": [\n    {\"@type\":\"Question\",\"name\":\"What material is used for CMP polishing pads?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"The vast majority of production CMP polishing pads are made from polyurethane foam, chosen for its tunable hardness (Shore D 25\u201370), chemical resistance to CMP slurries, and controllable micropore structure. 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Its hardness, porosity, groove geometry, and surface  &#8230;<\/p>","protected":false},"author":1,"featured_media":2388,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[9,59],"tags":[],"class_list":["post-2386","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-blog","category-industry"],"acf":[],"_links":{"self":[{"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/posts\/2386","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/comments?post=2386"}],"version-history":[{"count":2,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/posts\/2386\/revisions"}],"predecessor-version":[{"id":2389,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/posts\/2386\/revisions\/2389"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/media\/2388"}],"wp:attachment":[{"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/media?parent=2386"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/categories?post=2386"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/tags?post=2386"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}