{"id":2402,"date":"2026-06-24T10:15:37","date_gmt":"2026-06-24T02:15:37","guid":{"rendered":"https:\/\/jeez-semicon.com\/?p=2402"},"modified":"2026-06-24T10:15:37","modified_gmt":"2026-06-24T02:15:37","slug":"post-cmp-cleaning-planarization-metrology-ensuring-surface-quality","status":"publish","type":"post","link":"https:\/\/jeez-semicon.com\/de\/blog\/post-cmp-cleaning-planarization-metrology-ensuring-surface-quality\/","title":{"rendered":"Post-CMP Cleaning &amp; Planarization Metrology: Ensuring Surface Quality"},"content":{"rendered":"<!-- JEEZ | Cluster 09 | Post-CMP Cleaning & Planarization Metrology: Ensuring Surface Quality -->\n<link rel=\"preconnect\" href=\"https:\/\/fonts.googleapis.com\">\n<link rel=\"preconnect\" href=\"https:\/\/fonts.gstatic.com\" crossorigin>\n<link href=\"https:\/\/fonts.googleapis.com\/css2?family=Syne:wght@600;700;800&#038;family=Inter:ital,wght@0,400;0,500;0,600;1,400&#038;display=swap\" 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48px;text-align:center;margin:50px 0;position:relative;overflow:hidden}\n.jeez-pl .jz-cta-box::before{content:'';position:absolute;left:-70px;bottom:-70px;width:230px;height:230px;border-radius:50%;background:radial-gradient(circle,rgba(13,148,136,.16) 0%,transparent 70%)}\n.jeez-pl .jz-cta-box h3{font-family:'Syne',sans-serif;color:#fff;font-size:1.4rem;font-weight:800;margin:0 0 10px;position:relative}\n.jeez-pl .jz-cta-box p{color:rgba(255,255,255,.74);max-width:520px;margin:0 auto 26px;font-size:14.5px;position:relative}\n.jeez-pl .jz-btn{display:inline-block;background:var(--jz-teal);color:#fff;font-size:14.5px;font-weight:700;padding:13px 36px;border-radius:8px;text-decoration:none;transition:background .15s,transform .1s}\n.jeez-pl .jz-btn:hover{background:var(--jz-teal-dark);color:#fff;text-decoration:none;transform:translateY(-2px)}\n.jeez-pl .jz-faq-list{margin-top:18px}\n.jeez-pl .jz-faq-item{border:1px solid var(--jz-border);border-radius:var(--jz-radius);margin-bottom:12px;overflow:hidden}\n.jeez-pl .jz-faq-q{background:var(--jz-bg);padding:15px 20px;font-weight:600;font-size:14.5px;color:var(--jz-navy);border-left:4px solid var(--jz-teal);line-height:1.4}\n.jeez-pl .jz-faq-a{padding:14px 20px 16px;font-size:14px;color:var(--jz-text);line-height:1.74;border-top:1px solid var(--jz-border)}\n@media(max-width:680px){.jeez-pl .jz-hero{padding:28px 22px}.jeez-pl .jz-toc ol{columns:1}.jeez-pl .jz-grid-2{grid-template-columns:1fr}.jeez-pl .jz-cta-box{padding:32px 22px}.jeez-pl h2{font-size:1.3rem}}\n<\/style>\n\n<div class=\"jeez-pl\">\n\n<a class=\"jz-back-link\" href=\"https:\/\/jeez-semicon.com\/de\/blog\/Planarization-in-Semiconductor-Manufacturing-Complete-Guide\/\" target=\"_blank\" rel=\"noopener noreferrer\">\u2190 Back to Complete Planarization Guide<\/a>\n\n<div class=\"jz-hero\">\n  <span class=\"jz-hero-eyebrow\">CMP Quality Assurance<\/span>\n  <p class=\"jz-hero-lead\">The CMP process itself is only half of the planarization module. What follows \u2014 post-CMP cleaning and metrology \u2014 determines whether the wafer achieves the surface cleanliness, roughness, and thickness uniformity required for the next process step. This guide provides a comprehensive technical reference for post-CMP cleaning chemistry and techniques, all key planarization metrology parameters, endpoint detection methods, and the run-to-run control systems that tie them together.<\/p>\n  <div class=\"jz-hero-meta\">\n    <span>Updated: <strong>June 2026<\/strong><\/span>\n    <span class=\"jz-pipe\">|<\/span>\n    <span>By <strong>JEEZ Technical Team<\/strong><\/span>\n  <\/div>\n<\/div>\n\n<nav class=\"jz-toc\" aria-label=\"Inhalts\u00fcbersicht\">\n  <span class=\"jz-toc-label\">Inhalts\u00fcbersicht<\/span>\n  <ol>\n    <li><a href=\"#why-cleaning\">Why Post-CMP Cleaning Is Non-Negotiable<\/a><\/li>\n    <li><a href=\"#contamination-types\">Contamination Types After CMP<\/a><\/li>\n    <li><a href=\"#pva-brush\">PVA Brush Scrubbing<\/a><\/li>\n    <li><a href=\"#megasonic\">Megasonic Cleaning<\/a><\/li>\n    <li><a href=\"#chemical-cleaning\">Wet Chemical Cleaning<\/a><\/li>\n    <li><a href=\"#cleaning-by-app\">Cleaning Chemistry by CMP Application<\/a><\/li>\n    <li><a href=\"#roughness-metrics\">Surface Roughness Metrics: Ra, Rq, Rz<\/a><\/li>\n    <li><a href=\"#uniformity-metrics\">Uniformity Metrics: WIWNU and TTV<\/a><\/li>\n    <li><a href=\"#metrology-tools\">Metrology Tools and Techniques<\/a><\/li>\n    <li><a href=\"#epd\">Endpoint Detection In Depth<\/a><\/li>\n    <li><a href=\"#r2r-control\">Run-to-Run Process Control<\/a><\/li>\n    <li><a href=\"#specs-by-app\">Quality Specifications by Application<\/a><\/li>\n    <li><a href=\"#faq\">H\u00e4ufig gestellte Fragen<\/a><\/li>\n  <\/ol>\n<\/nav>\n\n\n<section id=\"why-cleaning\">\n  <h2><span class=\"jz-sn\">01<\/span>Why Post-CMP Cleaning Is Non-Negotiable<\/h2>\n  <p>CMP inherently contaminates the wafer surface it is polishing. The polishing process introduces: nano-scale abrasive particles from the slurry that adhere electrostatically and physically to the wafer surface; metallic ions dissolved from the polished film and from slurry chemical components that deposit as trace metal contamination; and organic residues from surfactants, chelating agents, corrosion inhibitors (BTA), and pad decomposition products. If these contaminants are not removed before the next process step, they cause yield loss through several mechanisms.<\/p>\n\n  <div class=\"jz-callout gold\">\n    <span class=\"jz-callout-tag\">Contamination Consequences<\/span>\n    <p>Slurry particles remaining on the wafer surface after CMP can: block via etch into the dielectric (causing open circuits); cause bridging shorts between adjacent metal lines; nucleate void formation during subsequent CVD; or act as particle seeds that damage photolithography optics during the next exposure step. Even a single particle &gt;100 nm at a critical location can cause a chip failure.<\/p>\n  <\/div>\n\n  <p>Post-CMP cleaning is therefore not a cosmetic step \u2014 it is a yield-critical process step with its own specifications, process controls, and metrology requirements. In a leading-edge fab, the post-CMP cleaning module is validated with the same rigor as the polishing step itself. The cleaner must remove particles, metal contamination, and organic residues to well-defined specifications before the wafer is allowed to proceed to the next deposition, etch, or lithography step.<\/p>\n<\/section>\n\n\n<section id=\"contamination-types\">\n  <h2><span class=\"jz-sn\">02<\/span>Contamination Types After CMP<\/h2>\n\n  <div class=\"jz-grid-2\">\n    <div class=\"jz-card\">\n      <h4>Slurry Particle Residues<\/h4>\n      <p>Nano-scale abrasive particles (SiO\u2082, CeO\u2082, Al\u2082O\u2083, 20\u2013200 nm) that adhere to the wafer surface by van der Waals and electrostatic forces. CeO\u2082 and Al\u2082O\u2083 particles are harder to remove than SiO\u2082 due to higher surface charge and stronger adhesion. Particles in recessed features (narrow trenches, via openings) are inaccessible to brush contact and require megasonic energy for dislodgement.<\/p>\n    <\/div>\n    <div class=\"jz-card\">\n      <h4>Metallic Ion Contamination<\/h4>\n      <p>Transition metal ions (Cu\u00b2\u207a, Fe\u00b3\u207a, Ce\u00b3\u207a\/Ce\u2074\u207a, Al\u00b3\u207a, K\u207a) dissolved from polished films and slurry chemical components adsorb onto the wafer surface and dielectric films. Copper is particularly problematic \u2014 it is a fast diffuser in SiO\u2082 and Si, and even at concentrations below 10\u00b9\u2070 atoms\/cm\u00b2 can cause gate oxide integrity degradation and minority carrier lifetime reduction. Iron from Fenton-chemistry SiC CMP is monitored at similar stringency.<\/p>\n    <\/div>\n    <div class=\"jz-card\">\n      <h4>Organic Residues<\/h4>\n      <p>Surfactants, benzotriazole (BTA) corrosion inhibitor, glycine and citrate chelating agents, and pad decomposition fragments remain on the wafer surface after polishing. BTA, in particular, forms a stable Cu\u2013BTA complex on copper surfaces that is water-insoluble and resists simple DIW rinsing. Organic residues at the dielectric\u2013metal interface degrade adhesion and can outgas during subsequent CVD at elevated temperatures, causing void formation in deposited films.<\/p>\n    <\/div>\n    <div class=\"jz-card\">\n      <h4>Mechanical Damage Residues<\/h4>\n      <p>Polishing-induced surface micro-scratches leave material displaced from the scratch path accumulated at the scratch terminus (&#8220;pileup&#8221;). Scratch pileup material is poorly adherent and must be removed by cleaning to prevent it from becoming a mobile particle during subsequent processing. In ULK dielectric CMP, mechanically damaged porous material at the polished surface may also require chemical cleaning to remove before the surface can be reliably sealed by subsequent barrier metal deposition.<\/p>\n    <\/div>\n  <\/div>\n<\/section>\n\n\n<section id=\"pva-brush\">\n  <h2><span class=\"jz-sn\">03<\/span>PVA Brush Scrubbing<\/h2>\n  <p>Polyvinyl alcohol (PVA) brush scrubbing is the primary mechanical particle removal step in post-CMP cleaning. PVA brushes are cylindrical sponge rollers (diameter 30\u201360 mm, length matching the wafer diameter) manufactured from cross-linked PVA polymer with a controlled open-cell foam structure. The PVA material is hydrophilic, soft (Shore A ~5\u201315), chemically resistant to CMP cleaning chemistries, and can be precision-machined to have a defined surface texture (nodular or smooth) that controls the contact mechanics at the brush\u2013wafer interface.<\/p>\n\n  <h3>Scrubbing Mechanism<\/h3>\n  <p>During PVA brush scrubbing, the rotating brush roller contacts the wafer surface (front side) with the brush center axis parallel to the wafer plane and perpendicular to the wafer translation direction. The brush compression (contact force) is precisely controlled \u2014 typically 0.05\u20130.5 N\/cm\u00b2 \u2014 to ensure sufficient mechanical contact for particle dislodgement without abrading or scratching the wafer surface. A chemical solution (DIW, dilute NH\u2084OH, citric acid, or HF depending on the application) is delivered through the brush interior and flows to the brush surface, providing both the liquid medium for particle dislodgement (hydrodynamic lift) and the chemical component for surface passivation or metal dissolution.<\/p>\n\n  <h3>Dual-Brush Modules<\/h3>\n  <p>Production post-CMP cleaners use dual-brush modules that clean both the front (device) side and back side of the wafer simultaneously \u2014 two counter-rotating brush rollers above and below the wafer while the wafer translates between them. Back-side cleaning is critical to remove particles that were deposited on the wafer back-side during CMP (from the carrier head membrane or the pad) and that would otherwise contaminate the chuck in subsequent process tools, creating back-side particle problems that are difficult to diagnose and control.<\/p>\n\n  <h3>PVA Brush Chemistry: Application-Specific<\/h3>\n  <div class=\"jz-table-wrap\">\n    <table>\n      <thead>\n        <tr><th>CMP Module<\/th><th>Brush Cleaning Chemistry<\/th><th>Concentration<\/th><th>Target Contamination<\/th><\/tr>\n      <\/thead>\n      <tbody>\n        <tr><td>Oxide \/ STI CMP<\/td><td>DIW or dilute NH\u2084OH<\/td><td>0.01\u20130.1% NH\u2084OH<\/td><td>SiO\u2082 \/ CeO\u2082 particles<\/td><\/tr>\n        <tr><td>Wolfram CMP<\/td><td>Dilute NH\u2084OH + citric acid<\/td><td>0.1% NH\u2084OH, 0.1\u20131% citric acid<\/td><td>Al\u2082O\u2083 particles, Fe, Al ions<\/td><\/tr>\n        <tr><td>Kupfer CMP<\/td><td>Dilute citric acid or ammonium citrate<\/td><td>0.1\u20131% citric acid, pH 4\u20135<\/td><td>SiO\u2082 particles, Cu\u00b2\u207a ions, BTA<\/td><\/tr>\n        <tr><td>SiC CMP<\/td><td>Dilute HCl or HNO\u2083 + DIW<\/td><td>0.1\u20131% HCl<\/td><td>Fe ions (Fenton), Ce\/Mn particles<\/td><\/tr>\n      <\/tbody>\n    <\/table>\n  <\/div>\n<\/section>\n\n\n<section id=\"megasonic\">\n  <h2><span class=\"jz-sn\">04<\/span>Megasonic Cleaning<\/h2>\n  <p>Megasonic cleaning applies high-frequency acoustic waves (850 kHz to 2 MHz) to a liquid bath or to a flowing liquid film over the wafer surface. At these frequencies, the acoustic field generates intense pressure fluctuations that create microstreaming currents near the wafer surface and, at sufficient power levels, transient acoustic cavitation \u2014 the rapid formation and collapse of microscopic bubbles in the liquid that produces highly localized mechanical impulses. The microstreaming and cavitation energy dislodges particles from the wafer surface without requiring direct mechanical contact, making megasonic cleaning particularly valuable for removing particles from recessed features (narrow trenches, via openings) that PVA brushes cannot reach.<\/p>\n\n  <h3>Megasonic Frequency Selection<\/h3>\n  <p>Frequency selection is a critical process parameter. Lower frequencies (850 kHz) generate stronger cavitation events (larger bubble collapse impulses) that more effectively remove strongly adherent particles but risk mechanical damage to fragile surface structures \u2014 particularly problematic for ULK porous dielectric films, which can be damaged by strong cavitation events. Higher frequencies (1.5\u20132 MHz) produce gentler microstreaming with minimal cavitation, providing safer cleaning for fragile film stacks at the cost of reduced cleaning efficiency for strongly adherent large particles. Most leading-edge fabs use 1\u20132 MHz megasonic cleaning for post-CMP applications, accepting some reduction in large particle removal efficiency in exchange for damage-free processing of fragile dielectric films.<\/p>\n\n  <h3>Megasonic Cleaning Chemistry<\/h3>\n  <p>Megasonic cleaning is performed in a chemical bath or under a flowing chemical film. The most common chemistries are:<\/p>\n  <ul>\n    <li><strong>SC1 (Standard Clean 1):<\/strong> NH\u2084OH : H\u2082O\u2082 : H\u2082O = 1:1:5, at 45\u201365\u00b0C. The combined alkaline chemistry and mild oxidizing action removes organic contamination and many particle types while slightly etching the SiO\u2082 surface (removing a thin contaminated surface layer). Standard for oxide and STI post-CMP cleaning.<\/li>\n    <li><strong>Dilute HF:<\/strong> 0.05\u20130.5% HF in DIW. Removes native oxide from silicon surfaces and disrupts the electrostatic adhesion of particles on SiO\u2082 surfaces by making the silicon surface hydrophobic. Used selectively where Si surface preparation is needed before gate oxide growth.<\/li>\n    <li><strong>DIW (Ultra-pure deionized water):<\/strong> 18.2 M\u03a9\u00b7cm resistivity DIW used as a final rinse medium. The megasonic energy applied to DIW provides particle removal through microstreaming alone, without chemical contribution \u2014 useful as a damage-safe final cleaning step after chemical baths.<\/li>\n  <\/ul>\n<\/section>\n\n\n<section id=\"chemical-cleaning\">\n  <h2><span class=\"jz-sn\">05<\/span>Wet Chemical Cleaning<\/h2>\n  <p>Sequential wet chemical cleaning baths address different contamination types that mechanical brush scrubbing and megasonic energy cannot fully remove:<\/p>\n\n  <div class=\"jz-steps\">\n    <div class=\"jz-step\">\n      <div class=\"jz-step-num\">1<\/div>\n      <div class=\"jz-step-body\">\n        <h4>SC1 \u2014 Particle and Organic Removal<\/h4>\n        <p>NH\u2084OH : H\u2082O\u2082 : H\u2082O (1:1:5 to 1:2:10) at 65\u201375\u00b0C for 5\u201310 minutes. The alkaline-oxidizing mixture lifts particles by oxidizing the wafer surface and creating electrostatic repulsion between the oxidized surface and abrasive particles (both negatively charged at pH &gt;9). Simultaneously removes organic surface films by oxidative degradation. Followed by a hot DIW overflow rinse (75\u00b0C, 10 min) to remove SC1 residues and displaced particles before they re-adhere.<\/p>\n      <\/div>\n    <\/div>\n    <div class=\"jz-step\">\n      <div class=\"jz-step-num\">2<\/div>\n      <div class=\"jz-step-body\">\n        <h4>SC2 \u2014 Metallic Contamination Removal<\/h4>\n        <p>HCl : H\u2082O\u2082 : H\u2082O (1:1:6) at 65\u201375\u00b0C for 5\u201310 minutes. The acidic-oxidizing mixture dissolves metallic surface contamination by converting metal ions to soluble chloride complexes and removing them into solution. Effective for: alkali metals (Na\u207a, K\u207a), alkaline earth metals (Ca\u00b2\u207a, Mg\u00b2\u207a), and transition metals (Fe\u00b3\u207a, Al\u00b3\u207a, Cr\u00b3\u207a). Not used for copper-containing surfaces (Cu\u00b2\u207a dissolved by SC2 but HCl can attack Cu metal). Followed by a DIW cascade rinse.<\/p>\n      <\/div>\n    <\/div>\n    <div class=\"jz-step\">\n      <div class=\"jz-step-num\">3<\/div>\n      <div class=\"jz-step-body\">\n        <h4>Dilute Citric Acid \u2014 Copper CMP Specific<\/h4>\n        <p>0.1\u20131% citric acid (pH 4\u20135) replaces SC2 for copper CMP post-clean applications where HCl would attack exposed copper surfaces. Citric acid forms stable Cu\u2013citrate complexes that keep dissolved copper in solution without re-deposition, while the mild acid pH also assists BTA complex dissolution from the copper surface. Does not attack copper metal at low concentrations, making it compatible with exposed copper damascene surfaces after CMP.<\/p>\n      <\/div>\n    <\/div>\n    <div class=\"jz-step\">\n      <div class=\"jz-step-num\">4<\/div>\n      <div class=\"jz-step-body\">\n        <h4>Final DIW Rinse and Spin-Dry<\/h4>\n        <p>Ultra-pure DIW (18.2 M\u03a9\u00b7cm) cascade or overflow rinse to dilute and remove all chemical residues from the wafer surface. Followed by N\u2082-assisted centrifugal spin-dry (2,000\u20134,000 rpm) that removes water from the wafer surface without leaving watermarks. IPA (isopropyl alcohol) vapor drying (Marangoni drying) is used for hydrophobic surfaces where water beading creates drying marks that look like particle contamination on surface inspection.<\/p>\n      <\/div>\n    <\/div>\n  <\/div>\n<\/section>\n\n\n<section id=\"cleaning-by-app\">\n  <h2><span class=\"jz-sn\">06<\/span>Cleaning Chemistry by CMP Application<\/h2>\n  <div class=\"jz-table-wrap\">\n    <table>\n      <thead>\n        <tr><th>CMP Module<\/th><th>Step 1 Chemistry<\/th><th>Step 2 Chemistry<\/th><th>Final<\/th><th>Key Concern<\/th><\/tr>\n      <\/thead>\n      <tbody>\n        <tr><td><strong>Oxide\/STI CMP<\/strong><\/td><td>PVA brush + dilute NH\u2084OH<\/td><td>Megasonic SC1<\/td><td>DIW rinse + spin-dry<\/td><td>CeO\u2082\/SiO\u2082 particle removal<\/td><\/tr>\n        <tr><td><strong>Wolfram CMP<\/strong><\/td><td>PVA brush + citric acid<\/td><td>SC1 megasonic<\/td><td>SC2 + DIW + dry<\/td><td>Al\u2082O\u2083 particles, Fe\u00b3\u207a, K\u207a ions<\/td><\/tr>\n        <tr><td><strong>Cu CMP (Step 1+2)<\/strong><\/td><td>PVA brush + citric acid \/ ammonium citrate<\/td><td>Megasonic DIW or SC1<\/td><td>DIW + Marangoni dry<\/td><td>SiO\u2082 particles, Cu\u00b2\u207a ions, BTA residue<\/td><\/tr>\n        <tr><td><strong>ULK ILD CMP<\/strong><\/td><td>PVA brush + low-force, dilute NH\u2084OH<\/td><td>Low-power megasonic (1.5\u20132 MHz)<\/td><td>DIW + gentle spin-dry<\/td><td>Dielectric damage; delamination risk<\/td><\/tr>\n        <tr><td><strong>SiC CMP<\/strong><\/td><td>PVA brush + dilute HCl<\/td><td>SC2 (metal removal)<\/td><td>DIW + dry; TXRF check for Fe<\/td><td>Fe contamination from Fenton chemistry<\/td><\/tr>\n      <\/tbody>\n    <\/table>\n  <\/div>\n\n  <a class=\"jz-more\" href=\"https:\/\/jeez-semicon.com\/de\/blog\/CMP-Process-Steps-How-Chemical-Mechanical-Planarization-Works\/\" target=\"_blank\" rel=\"noopener noreferrer\">\n    <span>Related: CMP Process Steps \u2014 How Chemical Mechanical Planarization Works<\/span>\n    <span class=\"jz-more-arrow\">\u2192<\/span>\n  <\/a>\n<\/section>\n\n\n<section id=\"roughness-metrics\">\n  <h2><span class=\"jz-sn\">07<\/span>Surface Roughness Metrics: Ra, Rq, and Rz<\/h2>\n  <p>Post-CMP surface roughness is the most fundamental quality metric for the polished surface. Three complementary parameters are used to fully characterize the surface texture, each sensitive to different aspects of the height distribution:<\/p>\n\n  <div class=\"jz-metric\">\n    <div class=\"jz-metric-sym\">Ra<\/div>\n    <div class=\"jz-metric-body\">\n      <h4>Arithmetic Average Roughness (Ra)<\/h4>\n      <p><strong>Definition:<\/strong> The arithmetic mean of the absolute height deviations from the mean surface plane, measured over a defined scan length L: Ra = (1\/L) \u222b|z(x)| dx. Ra is the most commonly specified CMP roughness metric \u2014 it provides a single-number summary of average surface texture. <strong>Typical CMP specifications:<\/strong> Ra &lt;0.5 nm for advanced logic ILD CMP; Ra &lt;0.3 nm for copper CMP final buff; Ra &lt;0.2 nm for SiC epi-ready substrates; Ra &lt;0.3 nm for hybrid bonding surface preparation. <strong>Limitation:<\/strong> Ra is insensitive to rare high-amplitude events (occasional deep scratches or high spikes), which may be more damaging to device yield than the average surface texture implies.<\/p>\n    <\/div>\n  <\/div>\n\n  <div class=\"jz-metric\">\n    <div class=\"jz-metric-sym\">Rq<\/div>\n    <div class=\"jz-metric-body\">\n      <h4>Root Mean Square Roughness (Rq or RMS)<\/h4>\n      <p><strong>Definition:<\/strong> The root mean square of the height deviation from the mean surface: Rq = \u221a[(1\/L) \u222bz(x)\u00b2 dx]. Rq is always \u2265 Ra (for a Gaussian height distribution, Rq \u2248 1.25 \u00d7 Ra). Because squaring the height values amplifies high-amplitude excursions, Rq is more sensitive than Ra to the presence of occasional deep scratches or high spikes in the surface profile. <strong>Use in CMP:<\/strong> Rq is specified alongside Ra for applications where rare high events are particularly damaging \u2014 for example, gate oxide growth on a polished silicon surface, where a single surface spike can create a localized field enhancement leading to early oxide breakdown.<\/p>\n    <\/div>\n  <\/div>\n\n  <div class=\"jz-metric\">\n    <div class=\"jz-metric-sym\">Rz<\/div>\n    <div class=\"jz-metric-body\">\n      <h4>Maximum Height (Rz \u2014 Peak-to-Valley)<\/h4>\n      <p><strong>Definition:<\/strong> The vertical distance between the highest peak and the deepest valley in the measurement area (ISO 4287 definition: average of maximum peak-to-valley height over five consecutive sampling lengths). Rz directly captures the worst-case surface feature height in the measurement area. <strong>Use in CMP:<\/strong> Rz is particularly relevant for applications where worst-case topography is more critical than average texture \u2014 for example, the maximum step height at a copper-to-dielectric boundary, or the maximum scratch depth on a freshly polished wafer. Rz values are typically 6\u201310\u00d7 Ra for a CMP-polished surface with a near-Gaussian height distribution.<\/p>\n    <\/div>\n  <\/div>\n<\/section>\n\n\n<section id=\"uniformity-metrics\">\n  <h2><span class=\"jz-sn\">08<\/span>Uniformity Metrics: WIWNU and TTV<\/h2>\n\n  <h3>Within-Wafer Non-Uniformity (WIWNU)<\/h3>\n  <p>WIWNU is the primary process control metric for CMP film thickness uniformity across the 300 mm wafer. It is defined as the standard deviation (1\u03c3) of the film thickness measurements across a defined grid of measurement sites (typically 49, 81, or 121 sites on a 300 mm wafer, excluding a 3\u20135 mm edge exclusion zone), expressed as a percentage of the mean film thickness:<\/p>\n  <p style=\"text-align:center;font-style:italic;font-weight:500;margin:14px 0\">WIWNU (%) = (\u03c3 \/ \u03bc) \u00d7 100<\/p>\n  <p>where \u03c3 is the standard deviation of the thickness measurements and \u03bc is the mean thickness across all measurement sites. A WIWNU of 1% on a 300 nm remaining film means the standard deviation of thickness is 3 nm \u2014 individual sites may vary by \u00b16\u20139 nm (\u00b12\u20133\u03c3) from the mean. WIWNU is the primary feedback metric for run-to-run (R2R) control systems that adjust the CMP polishing recipe for the next lot based on the current lot&#8217;s measured WIWNU map.<\/p>\n\n  <h3>Total Thickness Variation (TTV)<\/h3>\n  <p>TTV is the total range of film thickness across the wafer \u2014 the difference between the maximum and minimum thickness measurement at any site on the wafer (within the edge exclusion zone). TTV = T<sub>max<\/sub> \u2212 T<sub>min<\/sub>. While WIWNU characterizes the statistical spread of thickness values, TTV captures the worst-case variation \u2014 useful for identifying systematic edge effects, center-heavy or edge-heavy removal profiles that may be within WIWNU specification on average but create a worst-case thickness outlier that exceeds the per-site specification.<\/p>\n\n  <h3>Die-Level Planarity<\/h3>\n  <p>Beyond wafer-level WIWNU and TTV, some advanced applications require characterization of planarity at the die level \u2014 within-die uniformity (WIDNU) that captures thickness variation across a single chip area (typically 10\u201330 mm\u00b2). Within-die variation is driven by pattern density effects during CMP (the &#8220;loading effect&#8221; \u2014 isolated features vs. dense arrays are planarized at different rates) and is the metric most directly linked to transistor performance uniformity within a single chip.<\/p>\n<\/section>\n\n\n<section id=\"metrology-tools\">\n  <h2><span class=\"jz-sn\">09<\/span>Metrology Tools and Techniques<\/h2>\n  <div class=\"jz-table-wrap\">\n    <table>\n      <thead>\n        <tr><th>Technique<\/th><th>Measured Parameter<\/th><th>Spatial Resolution<\/th><th>Throughput<\/th><th>CMP Application<\/th><\/tr>\n      <\/thead>\n      <tbody>\n        <tr><td><strong>Spectroscopic Reflectometry<\/strong><\/td><td>Film thickness, WIWNU, TTV<\/td><td>~50 \u00b5m spot size<\/td><td>High (&lt;30 s\/wafer)<\/td><td>Oxide, STI, ILD CMP \u2014 primary in-line thickness metrology<\/td><\/tr>\n        <tr><td><strong>Spectroscopic Ellipsometry<\/strong><\/td><td>Film thickness + optical constants<\/td><td>~30\u2013100 \u00b5m<\/td><td>Medium (1\u20135 min\/wafer for multi-point)<\/td><td>ULK dielectric, gate oxide post-CMP characterization<\/td><\/tr>\n        <tr><td><strong>Four-Point Probe (4PP)<\/strong><\/td><td>Sheet resistance (metal film thickness proxy)<\/td><td>~1 mm<\/td><td>Hoch<\/td><td>Copper CMP, tungsten CMP \u2014 in-line sheet Rs uniformity<\/td><\/tr>\n        <tr><td><strong>Atomic Force Microscopy (AFM)<\/strong><\/td><td>Ra, Rq, Rz, surface topography<\/td><td>&lt;1 nm lateral<\/td><td>Low (5\u201330 min\/site)<\/td><td>All CMP modules \u2014 standard for Ra\/Rq specification verification<\/td><\/tr>\n        <tr><td><strong>Optical Surface Inspection<\/strong><\/td><td>Particle and scratch defect density and location<\/td><td>0.1\u20130.5 \u00b5m (dark-field)<\/td><td>High (&lt;3 min\/wafer)<\/td><td>All CMP modules \u2014 mandatory post-clean particle inspection<\/td><\/tr>\n        <tr><td><strong>TXRF (Total Reflection XRF)<\/strong><\/td><td>Surface metal contamination (&gt;10\u2078 atoms\/cm\u00b2)<\/td><td>~1 cm\u00b2 spot<\/td><td>Low (5\u201330 min\/site)<\/td><td>Copper CMP (Cu contamination), SiC CMP (Fe from Fenton)<\/td><\/tr>\n        <tr><td><strong>Cross-Section TEM\/SEM<\/strong><\/td><td>Subsurface damage, dishing depth, scratch depth<\/td><td>&lt;1 nm<\/td><td>Very low (destructive)<\/td><td>Qualification and failure analysis; not in-line<\/td><\/tr>\n      <\/tbody>\n    <\/table>\n  <\/div>\n<\/section>\n\n\n<section id=\"epd\">\n  <h2><span class=\"jz-sn\">10<\/span>Endpoint Detection In Depth<\/h2>\n  <p>Endpoint detection (EPD) is the in-situ capability that allows the CMP tool to stop polishing automatically when the target film thickness or stop layer condition is reached \u2014 without relying on a fixed polishing time. EPD is essential for achieving consistent post-CMP film thickness across wafers and lots despite normal process variation in incoming film thickness, slurry MRR fluctuation, and pad wear.<\/p>\n\n  <h3>Optical Interferometric EPD<\/h3>\n  <p>A laser or broadband light source passes through a transparent platen window and through the rotating pad onto the wafer surface. The reflected signal undergoes optical interference between reflections from the polished film top surface and the underlying interface. As the film thins during polishing, the interference fringe pattern oscillates with a period equal to one half-wavelength of optical path length change. The EPD algorithm counts fringes (each fringe corresponds to a known thickness change) and triggers polish stop when the target count is reached, or detects a signal transition (discontinuity in the oscillation pattern) that corresponds to arrival at the stop layer interface.<\/p>\n  <p>Optical EPD works optimally when: the polished film is optically transparent (or semi-transparent) at the laser wavelength; the film-to-substrate optical contrast is sufficient for detectable interference; and the polishing MRR is stable enough that the fringe-to-thickness calibration remains accurate throughout the run. For metal film CMP (copper, tungsten), where optical penetration is limited to 10\u201320 nm, broadband spectroscopic analysis of the reflectance spectrum replaces single-wavelength interferometry.<\/p>\n\n  <h3>Motor Current \/ Friction EPD<\/h3>\n  <p>The friction coefficient between the polishing pad and the wafer surface changes when the polishing transitions from one film to another \u2014 each material has a different tribological interaction with the pad and slurry combination. This friction change manifests as a change in the motor torque required to maintain the target rotational speed, detectable as a change in the motor current draw of the platen drive or carrier head drive. Motor current EPD is particularly effective for:<\/p>\n  <ul>\n    <li>STI CMP: The friction increase when polishing stops on Si\u2083N\u2084 vs. SiO\u2082 produces a clear motor current step that reliably signals the endpoint.<\/li>\n    <li>Tungsten CMP: The transition from W (low friction with alumina slurry) to TiN\/TiW barrier (higher friction) to SiO\u2082 PMD produces sequential friction steps detectable in the motor current signal.<\/li>\n  <\/ul>\n  <p>Motor current EPD is less accurate than optical EPD for precise thickness targets because the friction transition may be gradual rather than abrupt, and it varies with pattern density across the wafer \u2014 dense metal pattern areas reach the stop layer before sparse areas, creating a first-endpoint \/ last-endpoint distribution across the wafer diameter rather than a single clean endpoint signal.<\/p>\n\n  <h3>Eddy Current EPD for Metal Films<\/h3>\n  <p>An electromagnetic coil embedded in the platen induces eddy currents in electrically conductive films on the wafer surface. The amplitude of the eddy current response is proportional to the metal film&#8217;s conductance (thickness \u00d7 conductivity). As copper or tungsten is removed during CMP, the eddy current signal decreases in a manner that is directly, quantitatively related to the remaining film thickness \u2014 with sub-nm precision achievable in well-calibrated systems. Eddy current EPD provides a continuous, absolute thickness measurement during metal CMP without requiring optical access and without sensitivity to slurry opacity or pad material optical properties. It is the standard EPD method for copper CMP Step 1 (bulk copper removal) at leading-edge logic fabs.<\/p>\n<\/section>\n\n\n<section id=\"r2r-control\">\n  <h2><span class=\"jz-sn\">11<\/span>Run-to-Run Process Control (R2R)<\/h2>\n  <p>Run-to-Run (R2R) process control is the feed-forward\/feedback control architecture that adjusts the CMP polishing recipe for each successive wafer or lot based on measured process outcomes (post-CMP film thickness maps) and incoming wafer state (pre-CMP film thickness maps). Without R2R control, CMP performance would drift over time as consumables age \u2014 the pad glazes progressively, the slurry concentration fluctuates, and the tool components wear \u2014 causing systematic offsets in post-CMP film thickness that accumulate into out-of-specification results.<\/p>\n\n  <h3>R2R Control Loop Architecture<\/h3>\n  <div class=\"jz-steps\">\n    <div class=\"jz-step\">\n      <div class=\"jz-step-num\">1<\/div>\n      <div class=\"jz-step-body\">\n        <h4>Pre-CMP Measurement (Feed-Forward)<\/h4>\n        <p>The incoming film thickness distribution is measured by reflectometry at 49\u2013121 sites. The R2R controller calculates the required removal depth at each radial zone of the multi-zone carrier head to achieve the target post-CMP thickness profile, accounting for the known incoming thickness non-uniformity.<\/p>\n      <\/div>\n    <\/div>\n    <div class=\"jz-step\">\n      <div class=\"jz-step-num\">2<\/div>\n      <div class=\"jz-step-body\">\n        <h4>Recipe Adjustment<\/h4>\n        <p>The R2R controller updates the polishing recipe parameters \u2014 primary polish time, per-zone carrier head pressure profile, over-polish time \u2014 to achieve the target post-CMP profile given the current incoming film map and the current model of CMP tool behavior (removal rate vs. pressure curves, uniformity response functions).<\/p>\n      <\/div>\n    <\/div>\n    <div class=\"jz-step\">\n      <div class=\"jz-step-num\">3<\/div>\n      <div class=\"jz-step-body\">\n        <h4>Post-CMP Measurement (Feedback)<\/h4>\n        <p>Post-CMP film thickness is measured at the same site grid. The actual post-CMP thickness map is compared to the target. Any systematic offset or pattern in the residual error \u2014 center-high, edge-high, quadrant asymmetry \u2014 is used to update the R2R model&#8217;s prediction of the tool&#8217;s removal rate response function for the next lot.<\/p>\n      <\/div>\n    <\/div>\n    <div class=\"jz-step\">\n      <div class=\"jz-step-num\">4<\/div>\n      <div class=\"jz-step-body\">\n        <h4>Model Update and Convergence<\/h4>\n        <p>The R2R controller uses an exponentially weighted moving average (EWMA) filter \u2014 or a more sophisticated model-based control algorithm \u2014 to update the CMP model parameters continuously. The EWMA weight (\u03bb, typically 0.2\u20130.5) determines how quickly the model tracks real changes in tool behavior vs. how aggressively it filters random noise in individual lot measurements.<\/p>\n      <\/div>\n    <\/div>\n  <\/div>\n<\/section>\n\n\n<section id=\"specs-by-app\">\n  <h2><span class=\"jz-sn\">12<\/span>Quality Specifications by CMP Application<\/h2>\n  <div class=\"jz-table-wrap\">\n    <table>\n      <thead>\n        <tr><th>CMP Application<\/th><th>WIWNU Target<\/th><th>Surface Roughness (Ra)<\/th><th>Particle Spec (\u22650.1 \u00b5m)<\/th><th>Metal Contamination<\/th><\/tr>\n      <\/thead>\n      <tbody>\n        <tr><td><strong>Oxide ILD CMP<\/strong><\/td><td>&lt;2%<\/td><td>&lt;0.5 nm<\/td><td>&lt;0.05 \/cm\u00b2<\/td><td>&lt;5\u00d710\u00b9\u2070 atoms\/cm\u00b2 (Cu)<\/td><\/tr>\n        <tr><td><strong>STI CMP<\/strong><\/td><td>&lt;1.5%<\/td><td>&lt;0.5 nm<\/td><td>&lt;0.05 \/cm\u00b2<\/td><td>&lt;5\u00d710\u00b9\u2070 atoms\/cm\u00b2 (metals)<\/td><\/tr>\n        <tr><td><strong>Wolfram CMP<\/strong><\/td><td>&lt;2%<\/td><td>&lt;1 nm<\/td><td>&lt;0.1 \/cm\u00b2<\/td><td>&lt;1\u00d710\u00b9\u2070 atoms\/cm\u00b2 (metals)<\/td><\/tr>\n        <tr><td><strong>Cu CMP (Step 1+2)<\/strong><\/td><td>&lt;1.5%<\/td><td>&lt;0.5 nm<\/td><td>&lt;0.05 \/cm\u00b2<\/td><td>&lt;1\u00d710\u00b9\u2070 atoms\/cm\u00b2 (Cu)<\/td><\/tr>\n        <tr><td><strong>Cu CMP Buff \/ Hybrid Bonding<\/strong><\/td><td>&lt;1%<\/td><td><strong>&lt;0,3 nm<\/strong><\/td><td>&lt;0.01 \/cm\u00b2<\/td><td>&lt;5\u00d710\u2079 atoms\/cm\u00b2 (Cu)<\/td><\/tr>\n        <tr><td><strong>SiC Epi-Ready Polish<\/strong><\/td><td>&lt;1% (TTV &lt;5 \u00b5m)<\/td><td><strong>&lt;0.2 nm<\/strong><\/td><td>&lt;0.1 \/cm\u00b2 (\u22650.5 \u00b5m)<\/td><td>&lt;1\u00d710\u00b9\u2070 atoms\/cm\u00b2 (Fe, Ni)<\/td><\/tr>\n      <\/tbody>\n    <\/table>\n  <\/div>\n<\/section>\n\n\n<div class=\"jz-cta-box\">\n  <h3>Complete CMP Consumables from JEEZ<\/h3>\n  <p>JEEZ manufactures CMP polishing slurries, polishing pads, and absorption films that are engineered for the cleanliness, uniformity, and surface finish specifications your process demands. Contact our technical team to discuss your post-CMP quality requirements and consumable selection.<\/p>\n  <a class=\"jz-btn\" href=\"https:\/\/jeez-semicon.com\/de\/contact\/\" target=\"_blank\" rel=\"noopener noreferrer\">Contact JEEZ Technical Team \u2192<\/a>\n<\/div>\n\n\n<section id=\"faq\">\n  <h2><span class=\"jz-sn\">FAQ<\/span>H\u00e4ufig gestellte Fragen<\/h2>\n  <div class=\"jz-faq-list\">\n    <div class=\"jz-faq-item\">\n      <div class=\"jz-faq-q\">Why is post-CMP cleaning necessary and what does it remove?<\/div>\n      <div class=\"jz-faq-a\">Post-CMP cleaning is mandatory because the polishing process leaves three types of contamination on the wafer surface: (1) slurry abrasive particle residues (SiO\u2082, CeO\u2082, Al\u2082O\u2083) that adhere by van der Waals and electrostatic forces; (2) metallic ion contamination (Cu\u00b2\u207a, Fe\u00b3\u207a, Ce\u00b3\u207a, Al\u00b3\u207a) dissolved from polished films and slurry components that can cause gate oxide degradation, carrier lifetime reduction, or inter-line leakage; and (3) organic residues (surfactants, BTA, chelating agents) that degrade adhesion and can outgas during subsequent CVD. If these contaminants are not removed, they cause yield loss in subsequent process steps through particle-induced opens and shorts, metallic trap formation in dielectrics, and adhesion failures.<\/div>\n    <\/div>\n    <div class=\"jz-faq-item\">\n      <div class=\"jz-faq-q\">What is the difference between Ra, Rq, and Rz in CMP metrology?<\/div>\n      <div class=\"jz-faq-a\">All three are surface roughness metrics measured by AFM. Ra (arithmetic average roughness) is the mean absolute height deviation from the surface mean \u2014 the most common CMP specification metric. Rq (root mean square roughness) is more sensitive to high-amplitude excursions (deep scratches, high spikes) because squaring the height values amplifies outliers \u2014 for a CMP surface, Rq \u2248 1.25 \u00d7 Ra. Rz (maximum peak-to-valley height, averaged over five sampling lengths) captures the worst-case surface height variation in the measurement area \u2014 directly relevant for applications like gate oxide growth or hybrid bonding where single extreme events determine device performance or yield, not just the average texture.<\/div>\n    <\/div>\n    <div class=\"jz-faq-item\">\n      <div class=\"jz-faq-q\">What is WIWNU and what causes it in CMP?<\/div>\n      <div class=\"jz-faq-a\">Within-Wafer Non-Uniformity (WIWNU) is the standard deviation of post-CMP film thickness across the 300 mm wafer, expressed as a percentage of the mean thickness. It is caused by: radial variation in contact pressure across the wafer (center-heavy or edge-heavy polishing profile); non-uniform slurry distribution (center starvation at high rotation speeds if slurry flow is too low); pattern density effects (dense vs. sparse chip areas polished at different rates due to local contact pressure differences); and pad texture variations across the pad radius from non-uniform conditioning. WIWNU is controlled through multi-zone carrier head pressure adjustment, slurry flow rate optimization, pad conditioning uniformity, and run-to-run feedback control.<\/div>\n    <\/div>\n    <div class=\"jz-faq-item\">\n      <div class=\"jz-faq-q\">How does run-to-run process control improve CMP consistency?<\/div>\n      <div class=\"jz-faq-a\">R2R control closes the loop between measured CMP process outcomes and recipe adjustments for the next wafer or lot. Before each CMP run, the incoming film thickness map (measured by reflectometry) is fed forward to the R2R controller, which adjusts the per-zone carrier head pressure profile and polishing time to compensate for the measured incoming thickness variation. After each run, the post-CMP thickness map is fed back \u2014 the controller compares actual to target and uses the residual error to update its model of the CMP tool&#8217;s removal rate behavior. This continuous adaptation compensates for consumable aging (pad wear, slurry concentration drift) that would otherwise cause systematic post-CMP thickness offset to build over time.<\/div>\n    <\/div>\n    <div class=\"jz-faq-item\">\n      <div class=\"jz-faq-q\">What is the difference between optical and eddy current endpoint detection in CMP?<\/div>\n      <div class=\"jz-faq-a\">Optical endpoint detection uses laser light directed through the platen and pad onto the wafer surface. Interference fringes from reflections at the film-substrate interface change as the film thins, allowing direct thickness tracking. It works well for dielectric and semi-transparent metal films. Eddy current endpoint detection uses an electromagnetic coil to induce currents in conductive metal films \u2014 the signal amplitude is proportional to metal conductance (thickness \u00d7 conductivity), providing a continuous absolute thickness measurement for copper and tungsten CMP. Eddy current EPD is preferred for bulk copper CMP because it provides quantitative thickness tracking throughout the polishing run without requiring optical transparency, and is unaffected by slurry opacity or pad optical properties.<\/div>\n    <\/div>\n  <\/div>\n<\/section>\n\n<\/div>\n\n<script type=\"application\/ld+json\">\n{\n  \"@context\": \"https:\/\/schema.org\",\n  \"@type\": \"FAQPage\",\n  \"mainEntity\": [\n    {\"@type\":\"Question\",\"name\":\"Why is post-CMP cleaning necessary and what does it remove?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"Post-CMP cleaning removes three contamination types: (1) slurry abrasive particle residues (SiO2, CeO2, Al2O3); (2) metallic ion contamination (Cu2+, Fe3+, Ce3+) that cause gate oxide degradation and carrier lifetime reduction; and (3) organic residues (surfactants, BTA, chelating agents) that degrade adhesion. Without cleaning, these cause yield loss through particle-induced opens\/shorts, metallic trap formation, and adhesion failures.\"}},\n    {\"@type\":\"Question\",\"name\":\"What is the difference between Ra, Rq, and Rz in CMP metrology?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"Ra (arithmetic average roughness) is the mean absolute height deviation \u2014 the primary CMP specification metric. Rq (RMS roughness) amplifies high-amplitude outliers (Rq \u2248 1.25\u00d7Ra for CMP surfaces). Rz (peak-to-valley height, averaged over 5 sampling lengths) captures worst-case surface variation \u2014 relevant for gate oxide and hybrid bonding applications.\"}},\n    {\"@type\":\"Question\",\"name\":\"What is WIWNU and what causes it in CMP?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"WIWNU (Within-Wafer Non-Uniformity) is the standard deviation of post-CMP film thickness across the 300 mm wafer, as % of mean thickness. Caused by: radial contact pressure variation; non-uniform slurry distribution; pattern density effects; and pad texture gradients. Controlled through multi-zone carrier head pressure, slurry flow optimization, and run-to-run feedback control.\"}},\n    {\"@type\":\"Question\",\"name\":\"What is the difference between optical and eddy current endpoint detection?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"Optical EPD uses laser light interference fringes from the film-substrate interface to track thickness \u2014 works for dielectric and semi-transparent films. Eddy current EPD uses electromagnetic induction to measure metal film conductance continuously \u2014 preferred for copper CMP as it provides quantitative absolute thickness tracking unaffected by slurry opacity or pad optical properties.\"}}\n  ]\n}\n<\/script>","protected":false},"excerpt":{"rendered":"<p>\u2190 Back to Complete Planarization Guide CMP Quality Assurance The CMP process itself is only half of the planarization module. What follows \u2014 post-CMP cleaning and metrology \u2014 determines whether  &#8230;<\/p>","protected":false},"author":1,"featured_media":2404,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[9,59],"tags":[],"class_list":["post-2402","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-blog","category-industry"],"acf":[],"_links":{"self":[{"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/posts\/2402","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/comments?post=2402"}],"version-history":[{"count":2,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/posts\/2402\/revisions"}],"predecessor-version":[{"id":2405,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/posts\/2402\/revisions\/2405"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/media\/2404"}],"wp:attachment":[{"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/media?parent=2402"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/categories?post=2402"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/jeez-semicon.com\/de\/wp-json\/wp\/v2\/tags?post=2402"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}