{"id":1770,"date":"2026-04-07T15:55:08","date_gmt":"2026-04-07T07:55:08","guid":{"rendered":"https:\/\/jeez-semicon.com\/?p=1770"},"modified":"2026-04-07T16:28:59","modified_gmt":"2026-04-07T08:28:59","slug":"sic-cmp-polishing-pads-for-third-generation-semiconductors","status":"publish","type":"post","link":"https:\/\/jeez-semicon.com\/es\/blog\/sic-cmp-polishing-pads-for-third-generation-semiconductors\/","title":{"rendered":"SiC CMP Polishing Pads for Third-Generation Semiconductors"},"content":{"rendered":"<!-- ============================================================\n     CLUSTER 5 \u2014 SiC CMP Polishing Pads for Third-Generation Semiconductors\n     Jizhi Electronic Technology Co., Ltd.\n     jeez-semicon.com  |  April 2026\n     Paste into WordPress Gutenberg \u2192 Custom HTML block\n     URL: \/blog\/SiC-CMP-Polishing-Pads-for-Third-Generation-Semiconductors\n     ============================================================ -->\n\n<style>\n@import url('https:\/\/fonts.googleapis.com\/css2?family=Sora:wght@300;400;500;600;700&family=IBM+Plex+Mono:wght@400;500&display=swap');\n\n:root{\n  --c-surface:#ffffff;\n  --c-border:#e2e6ef;\n  --c-primary:#0b3d91;\n  --c-primary-dark:#072d6e;\n  --c-accent:#0090d4;\n  --c-accent-light:#e6f5fd;\n  --c-gold:#c8910a;\n  --c-gold-light:#fdf5e0;\n  --c-text:#1a1f2e;\n  --c-muted:#5a6278;\n  --c-tag-bg:#c8d9f5;\n  --c-tag-text:#0a2057;\n  --c-tag-border:#8aaee0;\n  --radius:10px;\n  --radius-lg:16px;\n  --shadow-card:0 2px 12px rgba(11,61,145,.07);\n  --shadow-hover:0 6px 28px rgba(11,61,145,.13);\n  --font-body:'Sora',sans-serif;\n  --font-mono:'IBM Plex Mono',monospace;\n  --max-w:860px;\n}\n\n.jz-art *{box-sizing:border-box;margin:0;padding:0}\n.jz-art{font-family:var(--font-body);color:var(--c-text);background:transparent;line-height:1.75;font-size:16px;max-width:var(--max-w);margin:0 auto}\n.jz-art a{color:var(--c-accent);text-decoration:none;transition:color .2s}\n.jz-art a:hover{color:var(--c-primary);text-decoration:underline}\n\n\/* Hero *\/\n.jz-hero{background:linear-gradient(135deg,#072d6e 0%,#0b3d91 45%,#0a5db5 100%);border-radius:var(--radius-lg);padding:52px 48px 48px;margin-bottom:40px;position:relative;overflow:hidden}\n.jz-hero::before{content:'';position:absolute;right:-60px;top:-60px;width:340px;height:340px;background:rgba(0,144,212,.18);border-radius:50%}\n.jz-hero::after{content:'';position:absolute;right:80px;bottom:-80px;width:200px;height:200px;background:rgba(0,144,212,.10);border-radius:50%}\n.jz-hero-kicker{font-family:var(--font-mono);font-size:12px;letter-spacing:.12em;text-transform:uppercase;color:rgba(255,255,255,.75);margin-bottom:14px}\n.jz-hero h1{font-size:clamp(24px,4vw,38px);font-weight:700;color:#fff;line-height:1.22;margin-bottom:18px;position:relative;z-index:1}\n.jz-hero-lead{font-size:17px;color:rgba(255,255,255,.90);line-height:1.72;max-width:620px;position:relative;z-index:1;margin-bottom:28px}\n.jz-hero-meta{display:flex;flex-wrap:wrap;gap:20px;font-size:13px;color:rgba(255,255,255,.90);position:relative;z-index:1}\n.jz-hero-meta span{display:flex;align-items:center;gap:6px}\n\n\/* Tags *\/\n.jz-tags{display:flex;flex-wrap:wrap;gap:8px;margin-bottom:36px}\n.jz-tag{background:var(--c-tag-bg);color:var(--c-tag-text);font-size:12px;font-weight:700;padding:4px 14px;border-radius:20px;border:1px solid var(--c-tag-border);letter-spacing:.01em}\n\n\/* Back link *\/\n.jz-back{display:inline-flex;align-items:center;gap:7px;font-size:13px;font-family:var(--font-mono);color:var(--c-muted);margin-bottom:28px;padding:8px 14px;background:var(--c-surface);border:1px solid var(--c-border);border-radius:6px;text-decoration:none;transition:border-color .2s,color .2s}\n.jz-back:hover{border-color:var(--c-accent);color:var(--c-accent);text-decoration:none}\n.jz-back::before{content:'\u2190';font-size:13px}\n\n\/* TOC *\/\n.jz-toc{background:var(--c-surface);border:1px solid var(--c-border);border-left:4px solid var(--c-primary);border-radius:var(--radius);padding:28px 32px;margin-bottom:44px;box-shadow:var(--shadow-card)}\n.jz-toc-title{font-size:14px;font-weight:600;text-transform:uppercase;letter-spacing:.08em;color:var(--c-primary);margin-bottom:16px;font-family:var(--font-mono)}\n.jz-toc ol{padding-left:20px;display:grid;grid-template-columns:1fr 1fr;gap:4px 32px}\n.jz-toc ol li{font-size:14px;line-height:1.65;color:var(--c-muted)}\n.jz-toc ol li a{color:var(--c-primary);font-weight:500}\n.jz-toc ol li a:hover{color:var(--c-accent)}\n@media(max-width:620px){.jz-toc ol{grid-template-columns:1fr}}\n\n\/* Headings *\/\n.jz-art h2{font-size:clamp(20px,3vw,26px);font-weight:700;color:var(--c-primary-dark);line-height:1.3;margin:52px 0 16px;padding-top:8px;border-top:2px solid var(--c-border)}\n.jz-art h3{font-size:18px;font-weight:600;color:var(--c-text);margin:28px 0 10px}\n.jz-art h4{font-size:16px;font-weight:600;color:var(--c-primary);margin:20px 0 8px}\n.jz-art p{margin-bottom:18px;color:#1e2435}\n.jz-art ul,.jz-art ol{margin-bottom:18px;padding-left:22px;color:#1e2435}\n.jz-art li{margin-bottom:7px;line-height:1.7}\n\n\/* Callouts *\/\n.jz-callout{border-radius:var(--radius);padding:20px 24px;margin:28px 0;display:flex;gap:16px;align-items:flex-start}\n.jz-callout-icon{font-size:22px;flex-shrink:0;margin-top:1px}\n.jz-callout-body{flex:1;font-size:15px;line-height:1.65;color:#1e2435}\n.jz-callout-body strong{display:block;font-weight:600;margin-bottom:4px;font-size:14px;color:#1a1f2e}\n.jz-callout.info{background:#e8f4fd;border-left:4px solid var(--c-accent)}\n.jz-callout.tip{background:var(--c-gold-light);border-left:4px solid var(--c-gold)}\n.jz-callout.warn{background:#fff4e5;border-left:4px solid #e07b00}\n.jz-callout.success{background:#eaf5ee;border-left:4px solid #2e9e55}\n.jz-callout.cta{background:linear-gradient(135deg,#e8f4fd,#edf1fb);border-left:4px solid var(--c-primary)}\n\n\/* Tables *\/\n.jz-table-wrap{overflow-x:auto;margin:28px 0;border-radius:var(--radius);box-shadow:var(--shadow-card)}\n.jz-table{width:100%;border-collapse:collapse;font-size:14px;background:var(--c-surface)}\n.jz-table thead th{background:var(--c-primary);color:#fff;font-weight:600;padding:12px 16px;text-align:left;font-size:13px;letter-spacing:.03em}\n.jz-table tbody tr:nth-child(even){background:#f3f6fc}\n.jz-table tbody td{padding:11px 16px;border-bottom:1px solid var(--c-border);color:#1e2435;vertical-align:top;line-height:1.6}\n.jz-table tbody tr:hover td{background:#eaf0fb}\n.jz-table .win{color:#1a6e35;font-weight:600}\n.jz-table .mid{color:#7a5c00;font-weight:500}\n.jz-table .lose{color:#963a00;font-weight:500}\n\n\/* Cards *\/\n.jz-card-grid{display:grid;grid-template-columns:repeat(auto-fit,minmax(210px,1fr));gap:20px;margin:28px 0}\n.jz-card{background:var(--c-surface);border:1px solid var(--c-border);border-radius:var(--radius);padding:22px 20px;box-shadow:var(--shadow-card);transition:transform .22s,box-shadow .22s}\n.jz-card:hover{transform:translateY(-3px);box-shadow:var(--shadow-hover)}\n.jz-card-icon{font-size:26px;margin-bottom:12px}\n.jz-card h4{font-size:15px;font-weight:600;color:var(--c-primary-dark);margin-bottom:8px}\n.jz-card p{font-size:14px;color:var(--c-muted);line-height:1.6;margin-bottom:0}\n\n\/* Steps *\/\n.jz-steps{counter-reset:step;display:flex;flex-direction:column;gap:0;margin:28px 0}\n.jz-step{display:flex;gap:20px;padding:22px 0;border-bottom:1px solid var(--c-border)}\n.jz-step:last-child{border-bottom:none}\n.jz-step-num{flex-shrink:0;width:40px;height:40px;background:var(--c-primary);color:#fff;border-radius:50%;display:flex;align-items:center;justify-content:center;font-weight:700;font-size:15px;margin-top:2px}\n.jz-step-body h4{font-size:16px;font-weight:600;color:#1a1f2e;margin-bottom:7px}\n.jz-step-body p{font-size:15px;color:#3a4255;margin-bottom:0;line-height:1.7}\n\n\/* Two-col *\/\n.jz-two-col{display:grid;grid-template-columns:1fr 1fr;gap:24px;margin:28px 0}\n@media(max-width:600px){.jz-two-col{grid-template-columns:1fr}}\n.jz-col-box{background:var(--c-surface);border:1px solid var(--c-border);border-radius:var(--radius);padding:22px 20px;box-shadow:var(--shadow-card)}\n.jz-col-box h4{font-size:15px;font-weight:600;margin-bottom:10px;color:var(--c-primary-dark)}\n.jz-col-box ul{padding-left:18px}\n.jz-col-box ul li{font-size:14px;color:#3a4255;margin-bottom:7px;line-height:1.6}\n\n\/* Hardness comparison bar \u2014 new component *\/\n.jz-hardness-chart{margin:28px 0;background:var(--c-surface);border:1px solid var(--c-border);border-radius:var(--radius);padding:24px 28px;box-shadow:var(--shadow-card)}\n.jz-hardness-title{font-size:13px;font-weight:600;font-family:var(--font-mono);color:var(--c-primary);margin-bottom:18px;text-transform:uppercase;letter-spacing:.06em}\n.jz-hardness-row{display:flex;align-items:center;gap:14px;margin-bottom:14px}\n.jz-hardness-row:last-child{margin-bottom:0}\n.jz-hardness-label{font-size:13px;color:#1e2435;font-weight:500;width:120px;flex-shrink:0}\n.jz-hardness-track{flex:1;background:#edf1f7;border-radius:6px;height:14px;position:relative;overflow:visible}\n.jz-hardness-bar{height:14px;border-radius:6px;position:relative}\n.jz-hardness-val{font-size:12px;font-family:var(--font-mono);color:#1e2435;font-weight:600;margin-left:8px;white-space:nowrap}\n\n\/* Process challenge cards \u2014 accent border top *\/\n.jz-challenge-grid{display:grid;grid-template-columns:repeat(auto-fit,minmax(220px,1fr));gap:18px;margin:28px 0}\n.jz-challenge-card{background:var(--c-surface);border:1px solid var(--c-border);border-top:3px solid var(--c-primary);border-radius:var(--radius);padding:20px;box-shadow:var(--shadow-card)}\n.jz-challenge-card.warn{border-top-color:#e07b00}\n.jz-challenge-card.danger{border-top-color:#c0392b}\n.jz-challenge-card.info{border-top-color:var(--c-accent)}\n.jz-challenge-card.success{border-top-color:#2e9e55}\n.jz-challenge-icon{font-size:24px;margin-bottom:10px}\n.jz-challenge-title{font-size:14px;font-weight:700;color:#1a1f2e;margin-bottom:7px}\n.jz-challenge-desc{font-size:13px;color:#3a4255;line-height:1.6}\n\n\/* Stats *\/\n.jz-stats{display:grid;grid-template-columns:repeat(auto-fit,minmax(148px,1fr));gap:16px;margin:28px 0}\n.jz-stat{background:var(--c-surface);border:1px solid var(--c-border);border-radius:var(--radius);padding:18px 16px;text-align:center;box-shadow:var(--shadow-card)}\n.jz-stat-num{font-size:26px;font-weight:700;color:var(--c-primary);font-family:var(--font-mono);line-height:1}\n.jz-stat-label{font-size:12px;color:var(--c-muted);margin-top:6px;line-height:1.4}\n\n\/* Trust bar *\/\n.jz-trust{background:#f0f4ff;border-radius:var(--radius);padding:20px 24px;display:flex;align-items:center;gap:18px;margin:40px 0;border:1px solid #d0daee}\n.jz-trust-badge{background:var(--c-primary);color:#fff;border-radius:8px;padding:10px 14px;font-size:12px;font-weight:700;text-align:center;line-height:1.3;flex-shrink:0;font-family:var(--font-mono)}\n.jz-trust-text{font-size:14px;color:#3a4255;line-height:1.65}\n.jz-trust-text strong{color:var(--c-text)}\n\n\/* Link chip *\/\n.jz-link-chip{display:inline-flex;align-items:center;gap:5px;background:var(--c-accent-light);color:var(--c-accent);font-size:13px;font-weight:500;padding:3px 11px 3px 8px;border-radius:20px;border:1px solid #b3ddf5;text-decoration:none;transition:background .2s,color .2s}\n.jz-link-chip:hover{background:var(--c-accent);color:#fff;text-decoration:none}\n.jz-link-chip::before{content:'\u2192';font-size:11px}\n\n\/* Related *\/\n.jz-related{background:var(--c-surface);border:1px solid var(--c-border);border-radius:var(--radius-lg);padding:32px 32px 28px;margin:48px 0 32px;box-shadow:var(--shadow-card)}\n.jz-related-title{font-size:14px;font-weight:600;text-transform:uppercase;letter-spacing:.08em;color:var(--c-primary);margin-bottom:20px;font-family:var(--font-mono)}\n.jz-related-grid{display:grid;grid-template-columns:repeat(auto-fill,minmax(230px,1fr));gap:14px}\n.jz-related-item{background:#f3f6fc;border-radius:8px;padding:14px 16px;border:1px solid var(--c-border);transition:background .2s,box-shadow .2s}\n.jz-related-item:hover{background:var(--c-accent-light);box-shadow:var(--shadow-card)}\n.jz-related-item a{font-size:14px;font-weight:500;color:var(--c-primary);text-decoration:none;line-height:1.45;display:block}\n.jz-related-item a:hover{color:var(--c-accent);text-decoration:none}\n.jz-related-cat{font-size:11px;font-family:var(--font-mono);color:var(--c-muted);margin-bottom:5px;letter-spacing:.05em}\n\n\/* CTA *\/\n.jz-cta-banner{background:linear-gradient(135deg,#072d6e 0%,#0b3d91 60%,#0a5db5 100%);border-radius:var(--radius-lg);padding:44px 40px;text-align:center;margin:48px 0;position:relative;overflow:hidden}\n.jz-cta-banner::before{content:'';position:absolute;left:-40px;top:-40px;width:220px;height:220px;background:rgba(0,144,212,.15);border-radius:50%}\n.jz-cta-banner h2{color:#fff;font-size:clamp(20px,3vw,28px);margin-bottom:12px;border:none;padding-top:0;position:relative;z-index:1}\n.jz-cta-banner p{color:rgba(255,255,255,.90);font-size:16px;margin-bottom:28px;position:relative;z-index:1}\n.jz-btn{display:inline-block;padding:13px 32px;border-radius:8px;font-weight:600;font-size:15px;text-decoration:none;transition:transform .2s,box-shadow .2s}\n.jz-btn:hover{transform:translateY(-2px);text-decoration:none}\n.jz-btn-white{background:#fff;color:var(--c-primary)}\n.jz-btn-white:hover{box-shadow:0 4px 20px rgba(0,0,0,.18);color:var(--c-primary)}\n.jz-btn-outline{background:transparent;color:#fff;border:2px solid rgba(255,255,255,.6);margin-left:12px}\n.jz-btn-outline:hover{background:rgba(255,255,255,.12);color:#fff}\n\n\/* FAQ *\/\n.jz-faq{margin:28px 0}\n.jz-faq-item{border:1px solid var(--c-border);border-radius:var(--radius);margin-bottom:12px;overflow:hidden;background:var(--c-surface)}\n.jz-faq-q{padding:16px 20px;font-weight:600;font-size:15px;color:var(--c-primary-dark);display:flex;justify-content:space-between;align-items:center}\n.jz-faq-q::after{content:'+';font-size:20px;font-weight:300;color:var(--c-accent);flex-shrink:0}\n.jz-faq-a{padding:0 20px 16px;font-size:15px;color:#3a4255;line-height:1.75}\n\n@media(max-width:640px){\n  .jz-hero{padding:36px 24px 32px}\n  .jz-cta-banner{padding:32px 22px}\n  .jz-related{padding:24px 18px}\n  .jz-btn-outline{margin-left:0;margin-top:10px;display:inline-block}\n}\n<\/style>\n\n<div class=\"jz-art\">\n\n<!-- Back to Pillar -->\n<a class=\"jz-back\" href=\"https:\/\/jeez-semicon.com\/es\/blog\/CMP-Polishing-Pads-The-Complete-Guide\/\" target=\"_blank\">Back to CMP Polishing Pads: The Complete Guide<\/a>\n\n<!-- Hero -->\n<div class=\"jz-hero\">\n  <div class=\"jz-hero-kicker\">Jizhi Electronic Technology \u2014 Applications Series<\/div>\n  <p class=\"jz-hero-lead\">A complete technical guide to CMP polishing pads for silicon carbide, gallium nitride, and other third-generation semiconductor materials \u2014 covering material challenges, pad requirements, slurry compatibility, process recipes, and supplier selection for power device fabs and research labs.<\/p>\n  <div class=\"jz-hero-meta\">\n    <span>\ud83d\udcc5 April 2026<\/span>\n    <span>\u23f1 16 min read<\/span>\n    <span>\ud83c\udfed Jizhi Electronic Technology Co., Ltd.<\/span>\n  <\/div>\n<\/div>\n\n<!-- Tags -->\n<div class=\"jz-tags\">\n  <span class=\"jz-tag\">SiC CMP Pad<\/span>\n  <span class=\"jz-tag\">Silicon Carbide Polishing<\/span>\n  <span class=\"jz-tag\">GaN CMP<\/span>\n  <span class=\"jz-tag\">Third-Generation Semiconductors<\/span>\n  <span class=\"jz-tag\">Power Device<\/span>\n  <span class=\"jz-tag\">SiC Wafer<\/span>\n  <span class=\"jz-tag\">Wide Bandgap<\/span>\n  <span class=\"jz-tag\">EV Semiconductor<\/span>\n<\/div>\n\n<!-- Trust bar -->\n<div class=\"jz-trust\">\n  <div class=\"jz-trust-badge\">SiC<br>Specialist<\/div>\n  <div class=\"jz-trust-text\">\n    <strong>Written by Jizhi Electronic Technology Co., Ltd.<\/strong> \u2014 developer and manufacturer of specialty CMP polishing pads for SiC and GaN substrates. Our SiC pad series is in active production supply to power device fabs and research institutions as of April 2026. All process data in this article is drawn from our in-house characterization laboratory.\n  <\/div>\n<\/div>\n\n<!-- TOC -->\n<div class=\"jz-toc\">\n  <div class=\"jz-toc-title\">\ud83d\udccb Table of Contents<\/div>\n  <ol>\n    <li><a href=\"#why-sic\">Why SiC Is Different: The Challenge in Numbers<\/a><\/li>\n    <li><a href=\"#material-properties\">SiC and GaN Material Properties vs. Silicon<\/a><\/li>\n    <li><a href=\"#cmp-challenges\">The Four Core CMP Challenges for SiC<\/a><\/li>\n    <li><a href=\"#pad-requirements\">Pad Requirements: What SiC CMP Demands<\/a><\/li>\n    <li><a href=\"#pad-types\">Pad Types Used in SiC CMP<\/a><\/li>\n    <li><a href=\"#slurry-pad-interaction\">Slurry-Pad Interaction for SiC<\/a><\/li>\n    <li><a href=\"#process-stages\">SiC Wafer Polishing: Three Process Stages<\/a><\/li>\n    <li><a href=\"#gan\">GaN CMP: Similarities and Differences<\/a><\/li>\n    <li><a href=\"#jizhi-sic\">Jizhi SiC Pad Series<\/a><\/li>\n    <li><a href=\"#faq\">FAQ<\/a><\/li>\n  <\/ol>\n<\/div>\n\n<!-- Intro -->\n<p>Silicon carbide (SiC) and gallium nitride (GaN) are the materials defining the next era of power electronics. SiC-based power MOSFETs and Schottky diodes are displacing silicon IGBTs in electric vehicle (EV) inverters, industrial motor drives, solar inverters, and EV fast-charging stations \u2014 enabling systems to operate at higher voltages (600\u20131700 V), higher temperatures (up to 200\u00b0C junction temperature), and higher switching frequencies than silicon can sustain. The global SiC power device market was valued at approximately USD 3.8 billion in 2025 and is projected to exceed USD 12 billion by 2030.<\/p>\n\n<p>Behind every SiC power device is a substrate polishing process of extraordinary difficulty. SiC&#8217;s extreme hardness and chemical inertness make conventional silicon CMP processes nearly useless \u2014 achieving the atomically smooth, defect-free surfaces required for epitaxial growth and device fabrication demands specialized CMP polishing pads, purpose-formulated slurries, and optimized process recipes that differ fundamentally from anything used in silicon IC manufacturing.<\/p>\n\n<p>This guide provides the complete technical picture of SiC CMP polishing pads: what makes SiC so challenging, what properties a pad must have to address those challenges, and how to select and qualify the right pad for your process. For an overview of the broader CMP pad landscape, see: <a class=\"jz-link-chip\" href=\"https:\/\/jeez-semicon.com\/es\/blog\/CMP-Polishing-Pads-The-Complete-Guide\/\" target=\"_blank\">CMP Polishing Pads: The Complete Guide<\/a>.<\/p>\n\n<div class=\"jz-stats\">\n  <div class=\"jz-stat\"><div class=\"jz-stat-num\">9.5<\/div><div class=\"jz-stat-label\">Mohs hardness of 4H-SiC \u2014 second only to diamond (10)<\/div><\/div>\n  <div class=\"jz-stat\"><div class=\"jz-stat-num\">&lt;0.5 nm<\/div><div class=\"jz-stat-label\">Ra surface roughness target for SiC epitaxial-ready substrate<\/div><\/div>\n  <div class=\"jz-stat\"><div class=\"jz-stat-num\">500+<\/div><div class=\"jz-stat-label\">\u00c5\/min removal rate achievable with optimized SiC-specific pad + slurry<\/div><\/div>\n  <div class=\"jz-stat\"><div class=\"jz-stat-num\">3.26<\/div><div class=\"jz-stat-label\">g\/cm\u00b3 density of 4H-SiC \u2014 40% denser than silicon (2.33 g\/cm\u00b3)<\/div><\/div>\n<\/div>\n\n<!-- \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 SECTION 1 \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 -->\n<h2 id=\"why-sic\">1. Why SiC Is Different: The Challenge in Numbers<\/h2>\n\n<p>To appreciate why SiC CMP is so much harder than silicon CMP, it helps to compare the key material properties side by side. The differences are not incremental \u2014 they are transformative, requiring an entirely different approach to pad and process design.<\/p>\n\n<div class=\"jz-hardness-chart\">\n  <div class=\"jz-hardness-title\">Mohs Hardness Comparison \u2014 Substrate Materials<\/div>\n  <div class=\"jz-hardness-row\">\n    <span class=\"jz-hardness-label\">Diamond<\/span>\n    <div class=\"jz-hardness-track\"><div class=\"jz-hardness-bar\" style=\"width:100%;background:#1a1f2e\"><\/div><\/div>\n    <span class=\"jz-hardness-val\">10.0<\/span>\n  <\/div>\n  <div class=\"jz-hardness-row\">\n    <span class=\"jz-hardness-label\">4H-SiC<\/span>\n    <div class=\"jz-hardness-track\"><div class=\"jz-hardness-bar\" style=\"width:95%;background:#c0392b\"><\/div><\/div>\n    <span class=\"jz-hardness-val\">9.5<\/span>\n  <\/div>\n  <div class=\"jz-hardness-row\">\n    <span class=\"jz-hardness-label\">Sapphire (Al\u2082O\u2083)<\/span>\n    <div class=\"jz-hardness-track\"><div class=\"jz-hardness-bar\" style=\"width:90%;background:#e07b00\"><\/div><\/div>\n    <span class=\"jz-hardness-val\">9.0<\/span>\n  <\/div>\n  <div class=\"jz-hardness-row\">\n    <span class=\"jz-hardness-label\">GaN<\/span>\n    <div class=\"jz-hardness-track\"><div class=\"jz-hardness-bar\" style=\"width:90%;background:#e07b00\"><\/div><\/div>\n    <span class=\"jz-hardness-val\">~9.0<\/span>\n  <\/div>\n  <div class=\"jz-hardness-row\">\n    <span class=\"jz-hardness-label\">SiO\u2082 (quartz)<\/span>\n    <div class=\"jz-hardness-track\"><div class=\"jz-hardness-bar\" style=\"width:70%;background:#c8910a\"><\/div><\/div>\n    <span class=\"jz-hardness-val\">7.0<\/span>\n  <\/div>\n  <div class=\"jz-hardness-row\">\n    <span class=\"jz-hardness-label\">Silicio (Si)<\/span>\n    <div class=\"jz-hardness-track\"><div class=\"jz-hardness-bar\" style=\"width:65%;background:#0b3d91\"><\/div><\/div>\n    <span class=\"jz-hardness-val\">6.5<\/span>\n  <\/div>\n  <div class=\"jz-hardness-row\">\n    <span class=\"jz-hardness-label\">Standard PU CMP pad<\/span>\n    <div class=\"jz-hardness-track\"><div class=\"jz-hardness-bar\" style=\"width:30%;background:#2e9e55\"><\/div><\/div>\n    <span class=\"jz-hardness-val\">~3.0<\/span>\n  <\/div>\n<\/div>\n\n<p>The hardness gap between SiC (9.5) and a conventional polyurethane CMP pad (Mohs ~3) is enormous. Standard oxide CMP works because the pad and abrasive (silica, Mohs 7) are harder than the chemically softened SiO\u2082 surface \u2014 the chemistry creates a softer reaction layer that can be mechanically abraded. On SiC, forming an equivalently soft passivation layer requires far more aggressive chemistry, and even then the bulk SiC beneath that layer resists abrasion from any particle softer than itself.<\/p>\n\n<!-- \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 SECTION 2 \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 -->\n<h2 id=\"material-properties\">2. SiC and GaN Material Properties vs. Silicon<\/h2>\n\n<div class=\"jz-table-wrap\">\n  <table class=\"jz-table\">\n    <thead>\n      <tr>\n        <th>Propiedad<\/th>\n        <th>Silicio (Si)<\/th>\n        <th>4H-SiC<\/th>\n        <th>GaN<\/th>\n        <th>CMP Implication<\/th>\n      <\/tr>\n    <\/thead>\n    <tbody>\n      <tr>\n        <td><strong>Mohs hardness<\/strong><\/td>\n        <td>6.5<\/td>\n        <td class=\"lose\">9.5<\/td>\n        <td class=\"lose\">~9.0<\/td>\n        <td>Requires diamond or specialty hard abrasives; conventional slurry ineffective<\/td>\n      <\/tr>\n      <tr>\n        <td><strong>Young&#8217;s modulus (GPa)<\/strong><\/td>\n        <td>130\u2013185<\/td>\n        <td class=\"lose\">390\u2013476<\/td>\n        <td class=\"lose\">~295<\/td>\n        <td>Extreme stiffness means brittle fracture rather than plastic deformation during abrasion<\/td>\n      <\/tr>\n      <tr>\n        <td><strong>Chemical inertness<\/strong><\/td>\n        <td>Moderado<\/td>\n        <td class=\"lose\">Muy alta<\/td>\n        <td class=\"lose\">Alta<\/td>\n        <td>Passivation layer forms very slowly; strong oxidizers required at high concentration<\/td>\n      <\/tr>\n      <tr>\n        <td><strong>Thermal conductivity (W\/m\u00b7K)<\/strong><\/td>\n        <td>150<\/td>\n        <td class=\"win\">490<\/td>\n        <td class=\"win\">230<\/td>\n        <td>High conductivity draws heat away from polishing zone \u2014 partially mitigates thermal pad damage<\/td>\n      <\/tr>\n      <tr>\n        <td><strong>Band gap (eV)<\/strong><\/td>\n        <td>1.12<\/td>\n        <td class=\"win\">3.26<\/td>\n        <td class=\"win\">3.39<\/td>\n        <td>Wide bandgap = high device value; surface defect tolerance is much lower than Si<\/td>\n      <\/tr>\n      <tr>\n        <td><strong>Oxidation rate (relative)<\/strong><\/td>\n        <td>1.0\u00d7<\/td>\n        <td class=\"lose\">~0.01\u00d7<\/td>\n        <td class=\"lose\">~0.05\u00d7<\/td>\n        <td>Chemical passivation rate 20\u2013100\u00d7 slower than Si; limits achievable MRR with standard chemistry<\/td>\n      <\/tr>\n    <\/tbody>\n  <\/table>\n<\/div>\n\n<!-- \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 SECTION 3 \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 -->\n<h2 id=\"cmp-challenges\">3. The Four Core CMP Challenges for SiC<\/h2>\n\n<div class=\"jz-challenge-grid\">\n  <div class=\"jz-challenge-card danger\">\n    <div class=\"jz-challenge-icon\">\ud83e\udea8<\/div>\n    <div class=\"jz-challenge-title\">Challenge 1 \u2014 Extreme Hardness<\/div>\n    <div class=\"jz-challenge-desc\">At Mohs 9.5, SiC cannot be plastically deformed by conventional abrasive particles (silica Mohs 7, ceria Mohs 6). Only diamond (Mohs 10) and boron carbide (Mohs 9.5) are hard enough to abrade SiC mechanically. This mandates diamond-containing slurries or fixed-abrasive pad systems, both of which introduce significant sub-surface damage risk.<\/div>\n  <\/div>\n  <div class=\"jz-challenge-card warn\">\n    <div class=\"jz-challenge-icon\">\ud83e\uddea<\/div>\n    <div class=\"jz-challenge-title\">Challenge 2 \u2014 Chemical Inertness<\/div>\n    <div class=\"jz-challenge-desc\">SiC oxidizes at a rate approximately 100\u00d7 slower than silicon under equivalent conditions. The chemical component of CMP \u2014 which softens the surface to enable efficient mechanical removal \u2014 is dramatically throttled. Achieving commercially viable removal rates requires highly oxidizing slurry chemistry (KMnO\u2084, H\u2082O\u2082 at high concentration, or Fenton reagents) that must remain compatible with the pad material.<\/div>\n  <\/div>\n  <div class=\"jz-challenge-card info\">\n    <div class=\"jz-challenge-icon\">\ud83d\udd2c<\/div>\n    <div class=\"jz-challenge-title\">Challenge 3 \u2014 Sub-Surface Damage<\/div>\n    <div class=\"jz-challenge-desc\">The same abrasive aggression needed to remove SiC at acceptable rates also risks introducing sub-surface crystal damage \u2014 dislocations, stacking faults, and micro-cracks \u2014 that extend 50\u2013500 nm below the polished surface. In the active device region of a SiC power MOSFET (channel thickness ~10\u201350 nm), sub-surface damage directly degrades threshold voltage stability, breakdown voltage, and long-term reliability.<\/div>\n  <\/div>\n  <div class=\"jz-challenge-card success\">\n    <div class=\"jz-challenge-icon\">\u26a1<\/div>\n    <div class=\"jz-challenge-title\">Challenge 4 \u2014 Material Removal Rate<\/div>\n    <div class=\"jz-challenge-desc\">With conventional oxide CMP slurry and a standard polyurethane pad, SiC removal rates are typically 20\u201350 \u00c5\/min \u2014 commercially unacceptable for production wafer processing. Achieving the 300\u20131,000 \u00c5\/min rates needed for economically viable SiC substrate preparation and CMP-ready surface delivery requires a precisely matched pad-slurry system.<\/div>\n  <\/div>\n<\/div>\n\n<!-- \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 SECTION 4 \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 -->\n<h2 id=\"pad-requirements\">4. Pad Requirements: What SiC CMP Demands from a Polishing Pad<\/h2>\n\n<p>The four challenges above translate directly into pad specification requirements that differ significantly from those for silicon CMP. Understanding these requirements is the foundation of intelligent SiC pad selection.<\/p>\n\n<div class=\"jz-card-grid\">\n  <div class=\"jz-card\">\n    <div class=\"jz-card-icon\">\ud83d\udcaa<\/div>\n    <h4>High Hardness &amp; Wear Resistance<\/h4>\n    <p>The pad must withstand continuous contact with both SiC (Mohs 9.5) and diamond or boron carbide abrasives in the slurry. Conventional PU pads abrade rapidly under these conditions. Shore D 60\u201370 with reinforced polymer matrix is the minimum specification. Pad lifetime on SiC is typically 3\u20135\u00d7 shorter than on silicon oxide.<\/p>\n  <\/div>\n  <div class=\"jz-card\">\n    <div class=\"jz-card-icon\">\ud83e\uddea<\/div>\n    <h4>Chemical Resistance to Strong Oxidizers<\/h4>\n    <p>SiC slurries use KMnO\u2084 (0.5\u20133 wt%), H\u2082O\u2082 (5\u201330 wt%), or Fenton-type reagents \u2014 far more aggressive than the H\u2082O\u2082 concentrations used in Cu CMP. The pad polymer must maintain mechanical integrity under these conditions. Polycarbonate-backbone PU or polysiloxane-modified matrices are preferred over standard polyether-PU.<\/p>\n  <\/div>\n  <div class=\"jz-card\">\n    <div class=\"jz-card-icon\">\ud83c\udf21\ufe0f<\/div>\n    <h4>High Thermal Stability (Tg &gt; 110\u00b0C)<\/h4>\n    <p>SiC polishing generates significantly more frictional heat than silicon CMP due to the higher forces required and the lower removal rate (more contact time per unit volume removed). Pad surface temperatures of 70\u201390\u00b0C are common. A glass transition temperature well above 110\u00b0C is essential to prevent thermal softening and MRR drift.<\/p>\n  <\/div>\n  <div class=\"jz-card\">\n    <div class=\"jz-card-icon\">\ud83c\udfaf<\/div>\n    <h4>Controlled Compliance for Damage Management<\/h4>\n    <p>For device-layer SiC CMP (final polishing step), the pad must be compliant enough to minimize peak contact stress \u2014 reducing the depth of sub-surface damage \u2014 while still transmitting sufficient force to maintain acceptable removal rates. This demands precise hardness control in the Shore D 50\u201360 range for final-step pads.<\/p>\n  <\/div>\n  <div class=\"jz-card\">\n    <div class=\"jz-card-icon\">\ud83d\udd29<\/div>\n    <h4>Groove Design for Aggressive Slurry<\/h4>\n    <p>Diamond-containing slurries tend to agglomerate under stagnant conditions. Groove design for SiC pads must prioritize slurry refreshment rate and particle resuspension \u2014 typically requiring wider, deeper grooves than standard oxide CMP pads, with radial or spiral patterns that maximize centrifugal slurry transport.<\/p>\n  <\/div>\n  <div class=\"jz-card\">\n    <div class=\"jz-card-icon\">\ud83d\udcd0<\/div>\n    <h4>Dimensional Stability Under High Down-Force<\/h4>\n    <p>SiC CMP uses higher down-force pressures than silicon (typically 3\u20138 psi, versus 1\u20134 psi for oxide). The pad must maintain its groove geometry and thickness under sustained high load without permanent deformation \u2014 requiring high elastic recovery (&gt;80%) and low creep under sustained load.<\/p>\n  <\/div>\n<\/div>\n\n<!-- \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 SECTION 5 \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 -->\n<h2 id=\"pad-types\">5. Pad Types Used in SiC CMP: A Practical Comparison<\/h2>\n\n<p>Three distinct pad approaches are used in SiC CMP, each making different trade-offs between removal rate, damage depth, and process controllability. The optimal choice depends on which stage of wafer preparation is being performed. For background on pad types in general, see: <a class=\"jz-link-chip\" href=\"https:\/\/jeez-semicon.com\/es\/blog\/CMP-Pad-Materials-Polyurethane-vs-Other-Options\/\" target=\"_blank\">CMP Pad Materials: Polyurethane vs Other Options<\/a>.<\/p>\n\n<div class=\"jz-table-wrap\">\n  <table class=\"jz-table\">\n    <thead>\n      <tr>\n        <th>Pad Type<\/th>\n        <th>MRR on SiC<\/th>\n        <th>Sub-Surface Damage<\/th>\n        <th>Best Process Stage<\/th>\n        <th>Key Limitation<\/th>\n      <\/tr>\n    <\/thead>\n    <tbody>\n      <tr>\n        <td><strong>Fixed-abrasive diamond pad<\/strong><\/td>\n        <td class=\"win\">1,000\u20135,000 \u00c5\/min<\/td>\n        <td class=\"lose\">Deep (200\u2013500 nm)<\/td>\n        <td>Coarse lapping \/ stock removal \u2014 not for device-layer CMP<\/td>\n        <td>Severe sub-surface damage requires subsequent damage-removal steps<\/td>\n      <\/tr>\n      <tr>\n        <td><strong>Specialty hard PU + diamond slurry<\/strong><\/td>\n        <td class=\"win\">300\u20131,200 \u00c5\/min<\/td>\n        <td class=\"mid\">Moderate (50\u2013200 nm)<\/td>\n        <td>Intermediate polishing \u2014 damage reduction after coarse lapping<\/td>\n        <td>Diamond slurry cost; requires strict particle size control to avoid scratch defects<\/td>\n      <\/tr>\n      <tr>\n        <td><strong>Specialty hard PU + oxidizing slurry (ceria\/KMnO\u2084)<\/strong><\/td>\n        <td class=\"mid\">100\u2013600 \u00c5\/min<\/td>\n        <td class=\"win\">Shallow (&lt;20 nm)<\/td>\n        <td>Final CMP \u2014 epitaxial-ready surface preparation<\/td>\n        <td>Lower MRR demands longer process time; strong oxidizer management required<\/td>\n      <\/tr>\n      <tr>\n        <td><strong>Standard oxide CMP pad (unmodified)<\/strong><\/td>\n        <td class=\"lose\">20\u201350 \u00c5\/min<\/td>\n        <td class=\"win\">Minimal<\/td>\n        <td>Not commercially viable for SiC production<\/td>\n        <td>Insufficient MRR for production throughput regardless of slurry optimization<\/td>\n      <\/tr>\n    <\/tbody>\n  <\/table>\n<\/div>\n\n<div class=\"jz-callout warn\">\n  <div class=\"jz-callout-icon\">\u26a0\ufe0f<\/div>\n  <div class=\"jz-callout-body\">\n    <strong>Never Use Standard IC CMP Pads for Device-Layer SiC<\/strong>\n    A common mistake in labs and small fabs transitioning to SiC is applying standard oxide CMP pads (IC1000-equivalent) with standard slurry to SiC substrates. The result is negligible removal rate and rapid pad glazing \u2014 the SiC surface abrades the soft pad rather than the reverse. Beyond wasting pad consumables, this approach fails to achieve the surface roughness and damage-depth targets needed for epitaxial growth, leading to defective epi layers and failed devices.\n  <\/div>\n<\/div>\n\n<!-- \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 SECTION 6 \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 -->\n<h2 id=\"slurry-pad-interaction\">6. Slurry-Pad Interaction for SiC: Getting the Chemistry Right<\/h2>\n\n<p>In SiC CMP, the slurry-pad combination is even more tightly coupled than in silicon CMP, because the chemical passivation mechanism is slower and more chemistry-dependent. The pad must be formulated to survive and function efficiently in the aggressive chemical environments that SiC polishing demands.<\/p>\n\n<h3>The SiC Chemical Passivation Mechanism<\/h3>\n<p>The most widely used chemical approach to SiC CMP is oxidation-assisted polishing. Strong oxidizing agents convert the SiC surface to a thin (1\u20133 nm) silicon dioxide (SiO\u2082) and carbon dioxide layer at the polishing interface. This oxide layer is significantly softer than bulk SiC (Mohs 7 vs. 9.5) and can be removed by the same abrasive particles that would struggle to scratch bulk SiC directly. The overall reaction is approximately:<\/p>\n\n<div style=\"background:#f0f4ff;border:1px solid #c8d9f5;border-radius:8px;padding:18px 24px;margin:24px 0;font-family:'IBM Plex Mono',monospace;font-size:14px;color:#1e2435;line-height:1.8\">\n  SiC + 2H\u2082O\u2082 \u2192 SiO\u2082 + CO\u2082 + 2H\u2082O (simplified)<br>\n  SiO\u2082 (soft surface layer) \u2192 mechanically removed by abrasive \u2192 fresh SiC exposed \u2192 cycle repeats\n<\/div>\n\n<h3>Key Oxidizer Systems and Pad Compatibility<\/h3>\n<div class=\"jz-table-wrap\">\n  <table class=\"jz-table\">\n    <thead>\n      <tr>\n        <th>Oxidizer System<\/th>\n        <th>Passivation Rate<\/th>\n        <th>MRR Potential<\/th>\n        <th>Pad Compatibility<\/th>\n        <th>Safety Considerations<\/th>\n      <\/tr>\n    <\/thead>\n    <tbody>\n      <tr>\n        <td><strong>H\u2082O\u2082 (5\u201330 wt%)<\/strong><\/td>\n        <td class=\"mid\">Moderado<\/td>\n        <td class=\"mid\">200\u2013500 \u00c5\/min<\/td>\n        <td class=\"win\">Good with polycarbonate-PU pads<\/td>\n        <td>Decomposition produces O\u2082 \u2014 ventilation required<\/td>\n      <\/tr>\n      <tr>\n        <td><strong>KMnO\u2084 (0.5\u20133 wt%)<\/strong><\/td>\n        <td class=\"win\">Alta<\/td>\n        <td class=\"win\">400\u2013800 \u00c5\/min<\/td>\n        <td class=\"mid\">Requires specialty pad \u2014 attacks standard PU<\/td>\n        <td>Strong oxidizer; MnO\u2082 byproduct can contaminate wafer<\/td>\n      <\/tr>\n      <tr>\n        <td><strong>Fenton reagent (H\u2082O\u2082 + Fe\u00b2\u207a)<\/strong><\/td>\n        <td class=\"win\">Muy alta<\/td>\n        <td class=\"win\">500\u20131,200 \u00c5\/min<\/td>\n        <td class=\"lose\">Attacks most standard PU formulations rapidly<\/td>\n        <td>Fe contamination risk; requires careful post-CMP cleaning<\/td>\n      <\/tr>\n      <tr>\n        <td><strong>Electrochemical (anodic oxidation assist)<\/strong><\/td>\n        <td class=\"win\">Controllable<\/td>\n        <td class=\"win\">300\u2013900 \u00c5\/min<\/td>\n        <td class=\"win\">Compatible with conductive specialty pads<\/td>\n        <td>Requires modified tool with electrodes; higher capital cost<\/td>\n      <\/tr>\n    <\/tbody>\n  <\/table>\n<\/div>\n\n<p>Jizhi Electronic Technology&#8217;s SiC pad series uses a polycarbonate-backbone polyurethane matrix with additional cross-linker content, specifically formulated to resist both H\u2082O\u2082 (up to 20 wt%) and KMnO\u2084 (up to 2 wt%) without measurable hardness loss over a 500-wafer pad lifetime. Our material qualification data, including hardness retention after slurry immersion tests at process temperature, is available on request.<\/p>\n\n<!-- \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 SECTION 7 \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 -->\n<h2 id=\"process-stages\">7. SiC Wafer Polishing: Three Process Stages and the Right Pad for Each<\/h2>\n\n<p>SiC substrate preparation from an as-sliced ingot to an epitaxial-ready surface is a multi-stage process, each stage requiring a different pad type and process recipe. Understanding the full sequence is essential for specifying the right consumables at each step.<\/p>\n\n<div class=\"jz-steps\">\n  <div class=\"jz-step\">\n    <div class=\"jz-step-num\">1<\/div>\n    <div class=\"jz-step-body\">\n      <h4>Stage 1 \u2014 Coarse Lapping (Stock Removal)<\/h4>\n      <p>Removes the subsurface damage layer from wire sawing (typically 20\u201350 \u00b5m of damaged crystal must be removed). Uses diamond lapping plates or coarse fixed-abrasive pads with 6\u201315 \u00b5m diamond abrasive. Removal rate: 2,000\u201310,000 \u00c5\/min. Surface after this stage: Ra 50\u2013200 nm, sub-surface damage depth 0.5\u20132 \u00b5m. A conventional CMP pad is not used at this stage \u2014 this is pure mechanical lapping.<\/p>\n    <\/div>\n  <\/div>\n  <div class=\"jz-step\">\n    <div class=\"jz-step-num\">2<\/div>\n    <div class=\"jz-step-body\">\n      <h4>Stage 2 \u2014 Damage Removal CMP (Intermediate Polish)<\/h4>\n      <p>The critical transition step. Uses a specialty hard PU pad (Shore D 62\u201368, polycarbonate-backbone) with a diamond slurry (0.1\u20130.5 \u00b5m diamond, pH 8\u201310, H\u2082O\u2082 5\u201315 wt%). Target: removal of 5\u201315 \u00b5m of material, reducing Ra from 50\u2013200 nm to 1\u20135 nm, and reducing sub-surface damage depth from 0.5\u20132 \u00b5m to &lt;30 nm. Removal rate: 300\u2013800 \u00c5\/min. Down-force: 4\u20138 psi. This is where Jizhi&#8217;s JZ-SiC-I series pad is designed to operate.<\/p>\n    <\/div>\n  <\/div>\n  <div class=\"jz-step\">\n    <div class=\"jz-step-num\">3<\/div>\n    <div class=\"jz-step-body\">\n      <h4>Stage 3 \u2014 Final CMP (Epitaxial-Ready Surface)<\/h4>\n      <p>The highest-precision step. Uses a medium-hard specialty PU pad (Shore D 52\u201360, controlled compliance) with colloidal ceria or fine silica slurry (pH 9\u201311, KMnO\u2084 0.5\u20131.5 wt% or H\u2082O\u2082 10\u201320 wt%). Target: Ra &lt; 0.2 nm, sub-surface damage depth &lt;5 nm, surface step density &lt;0.1 steps\/\u00b5m\u00b2. Removal rate: 80\u2013300 \u00c5\/min. Down-force: 1.5\u20133 psi. This step is the most critical determinant of epilayer quality and device performance. Jizhi&#8217;s JZ-SiC-II series is engineered for this stage.<\/p>\n    <\/div>\n  <\/div>\n<\/div>\n\n<div class=\"jz-callout tip\">\n  <div class=\"jz-callout-icon\">\ud83d\udca1<\/div>\n  <div class=\"jz-callout-body\">\n    <strong>Surface Step Structure: The Hidden Quality Metric<\/strong>\n    Beyond Ra surface roughness, the atomic step structure of the final SiC surface is critical for epilayer quality. A well-prepared 4H-SiC surface should show step-flow morphology with uniform step heights of 0.25 nm (one Si-C bilayer) and step widths of 100\u2013300 nm, as measured by AFM. Polishing pads that introduce localized pressure non-uniformity \u2014 from non-uniform groove patterns or inconsistent asperity distribution \u2014 disrupt this step structure, causing step bunching that propagates as threading dislocations into the epitaxial layer. Pad uniformity characterization from Jizhi includes asperity height distribution mapping across the full pad surface.\n  <\/div>\n<\/div>\n\n<!-- \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 SECTION 8 \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 -->\n<h2 id=\"gan\">8. GaN CMP: How It Differs from SiC<\/h2>\n\n<p>Gallium nitride presents a related but distinct CMP challenge from SiC. GaN is used primarily in RF power amplifiers (for 5G base stations), high-electron-mobility transistors (HEMTs), and, increasingly, in GaN-on-Si power switches competing with SiC in the 600 V range.<\/p>\n\n<div class=\"jz-two-col\">\n  <div class=\"jz-col-box\">\n    <h4>\ud83d\udd34 Where GaN CMP Is Harder Than SiC<\/h4>\n    <ul>\n      <li>GaN is chemically even more inert than SiC under most oxidizing conditions \u2014 its Ga-N bond energy (8.92 eV\/bond) is very high<\/li>\n      <li>Effective wet chemical etchants for GaN are limited to hot KOH (anisotropic) \u2014 not usable in CMP<\/li>\n      <li>GaN is typically grown as a thin epilayer on Si, SiC, or sapphire substrates \u2014 polishing through the GaN without damaging the substrate or the active device region below requires exceptional endpoint control<\/li>\n      <li>Polarity matters: N-face GaN polishes at a dramatically different rate than Ga-face GaN, creating non-uniformity risk on wafers with any polarity domains<\/li>\n    <\/ul>\n  <\/div>\n  <div class=\"jz-col-box\">\n    <h4>\ud83d\udfe2 Where GaN CMP Is More Tractable Than SiC<\/h4>\n    <ul>\n      <li>GaN-on-Si substrates benefit from the relative ease of polishing Si \u2014 the GaN layer CMP can use the Si substrate as a natural stop layer<\/li>\n      <li>Photo-enhanced CMP (using UV illumination to generate photo-carriers that accelerate oxidation) is particularly effective on GaN, enabling higher MRR without requiring extreme oxidizer concentrations<\/li>\n      <li>For GaN power devices, the CMP requirements are often less stringent than for SiC epitaxial substrates \u2014 Ra &lt; 1 nm is typically acceptable rather than &lt; 0.2 nm<\/li>\n      <li>Pad requirements are similar to Stage 3 SiC CMP \u2014 medium-hard specialty PU with high chemical resistance<\/li>\n    <\/ul>\n  <\/div>\n<\/div>\n\n<!-- \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 SECTION 9 \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 -->\n<h2 id=\"jizhi-sic\">9. Jizhi SiC CMP Pad Series<\/h2>\n\n<p>Jizhi Electronic Technology has developed a dedicated SiC CMP pad series through a multi-year R&amp;D program combining polymer materials science, tribology characterization, and SiC process engineering. Our pads are actively supplied to power device fabs, SiC substrate manufacturers, and university research groups as of April 2026.<\/p>\n\n<div class=\"jz-table-wrap\">\n  <table class=\"jz-table\">\n    <thead>\n      <tr>\n        <th>Product<\/th>\n        <th>Shore D<\/th>\n        <th>Polymer Matrix<\/th>\n        <th>Target Stage<\/th>\n        <th>Compatible Slurry<\/th>\n        <th>Typical MRR<\/th>\n      <\/tr>\n    <\/thead>\n    <tbody>\n      <tr>\n        <td><strong>JZ-SiC-I<\/strong><\/td>\n        <td>63\u201368<\/td>\n        <td>Polycarbonate-PU, high cross-link density<\/td>\n        <td>Stage 2 \u2014 damage removal<\/td>\n        <td>Diamond 0.1\u20130.5 \u00b5m + H\u2082O\u2082 10\u201320%<\/td>\n        <td>350\u2013800 \u00c5\/min<\/td>\n      <\/tr>\n      <tr>\n        <td><strong>JZ-SiC-II<\/strong><\/td>\n        <td>53\u201360<\/td>\n        <td>Polycarbonate-PU, controlled compliance<\/td>\n        <td>Stage 3 \u2014 final CMP<\/td>\n        <td>Ceria or silica + KMnO\u2084 0.5\u20131.5% or H\u2082O\u2082 10\u201320%<\/td>\n        <td>100\u2013350 \u00c5\/min<\/td>\n      <\/tr>\n      <tr>\n        <td><strong>JZ-GaN-F<\/strong><\/td>\n        <td>50\u201358<\/td>\n        <td>Polycarbonate-PU, UV-transparent variant<\/td>\n        <td>GaN final CMP<\/td>\n        <td>Colloidal silica + mild oxidizer, pH 9\u201311<\/td>\n        <td>80\u2013250 \u00c5\/min<\/td>\n      <\/tr>\n      <tr>\n        <td><strong>JZ-SiC-Custom<\/strong><\/td>\n        <td>Customer-specified<\/td>\n        <td>Per application requirement<\/td>\n        <td>Custom process step<\/td>\n        <td>Validated per customer slurry<\/td>\n        <td>Per characterization<\/td>\n      <\/tr>\n    <\/tbody>\n  <\/table>\n<\/div>\n\n<div class=\"jz-callout success\">\n  <div class=\"jz-callout-icon\">\u2705<\/div>\n  <div class=\"jz-callout-body\">\n    <strong>What&#8217;s Included with Every JZ-SiC Pad Order<\/strong>\n    Every Jizhi SiC CMP pad shipment includes: (1) Shore D hardness map (9-point across pad surface); (2) chemical resistance certification \u2014 immersion test data at customer&#8217;s specified slurry chemistry and concentration; (3) baseline MRR data on 4H-SiC reference wafers at our standard Stage 2 or Stage 3 reference recipe; (4) recommended conditioning protocol for break-in and steady-state operation; (5) SDS and material certification documentation for fab chemical management systems.\n  <\/div>\n<\/div>\n\n<p>For customers requiring custom pad formulations \u2014 for example, for 200 mm SiC wafers, Ga\u2082O\u2083 substrates, diamond substrates, or proprietary slurry systems \u2014 Jizhi&#8217;s application engineering team manages the full co-development cycle. See our custom pad development program at: <a class=\"jz-link-chip\" href=\"https:\/\/jeez-semicon.com\/es\/blog\/Custom-CMP-Polishing-Pad-Solutions\/\" target=\"_blank\">Custom CMP Polishing Pad Solutions<\/a>.<\/p>\n\n<!-- \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 FAQ \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 -->\n<h2>10. Frequently Asked Questions<\/h2>\n\n<div class=\"jz-faq\">\n  <div class=\"jz-faq-item\">\n    <div class=\"jz-faq-q\">Can I use a standard IC1000-type pad for SiC CMP?<\/div>\n    <div class=\"jz-faq-a\">No, not effectively. IC1000-type pads are formulated for silicon oxide CMP at neutral-to-alkaline pH with silica or ceria abrasives. On SiC, they will achieve only 20\u201350 \u00c5\/min removal rate \u2014 10 to 20\u00d7 lower than what specialty SiC pads achieve \u2014 and will themselves abrade rapidly under contact with SiC and diamond-containing slurries. Additionally, IC1000 polyether-PU formulations degrade under the high-concentration oxidizer slurries needed for SiC. Using IC1000 on SiC is not only ineffective but actively shortens pad life and can contaminate the wafer with polymer debris from rapid pad degradation.<\/div>\n  <\/div>\n  <div class=\"jz-faq-item\">\n    <div class=\"jz-faq-q\">What wafer sizes does Jizhi supply SiC pads for?<\/div>\n    <div class=\"jz-faq-a\">Jizhi supplies SiC CMP pads in sizes compatible with all major SiC wafer production formats: 100 mm (4-inch) pads for legacy R&amp;D tools, 150 mm (6-inch) format \u2014 currently the dominant production size for SiC \u2014 and 200 mm (8-inch) format, which is entering production ramp at leading SiC substrate manufacturers in 2025\u20132026. Custom pad sizes for non-standard research tools are also available. Please specify your tool&#8217;s platen diameter when requesting a quote.<\/div>\n  <\/div>\n  <div class=\"jz-faq-item\">\n    <div class=\"jz-faq-q\">How does SiC CMP affect downstream epitaxial layer quality?<\/div>\n    <div class=\"jz-faq-a\">The post-CMP surface condition of a SiC substrate is the single most important predictor of epilayer crystal quality. Sub-surface damage from inadequate CMP (insufficient damage-removal steps or wrong pad type) propagates as threading screw dislocations (TSDs) and basal plane dislocations (BPDs) into the epilayer during CVD growth at 1,500\u20131,650\u00b0C. These defects create forward voltage degradation in bipolar devices and reliability failures in power MOSFETs. A correctly polished SiC surface \u2014 Ra &lt; 0.2 nm, sub-surface damage &lt; 5 nm \u2014 enables epi layers with dislocation densities below 10\u00b3 cm\u207b\u00b2 and basal plane conversion ratios exceeding 99%, which are standard specifications for SiC power device production.<\/div>\n  <\/div>\n  <div class=\"jz-faq-item\">\n    <div class=\"jz-faq-q\">What conditioning protocol does Jizhi recommend for SiC CMP pads?<\/div>\n    <div class=\"jz-faq-a\">SiC CMP pads require a more aggressive break-in protocol than standard oxide CMP pads due to their higher cross-link density and thicker skin layer. Jizhi recommends: (1) 60\u2013100 ex-situ conditioning sweeps on a fresh wet pad before the first SiC wafer; (2) in-situ conditioning with a 100-grit or coarser diamond conditioner disk at 5\u20137 lbf throughout the polishing run; (3) post-run ex-situ conditioning of 20 sweeps before the next wafer. The more aggressive conditioning compared to standard pads is necessary because SiC&#8217;s abrasive action on the pad surface compacts the asperity tips \u2014 conditioning frequency must be calibrated to prevent the glazing that would otherwise rapidly drop MRR.<\/div>\n  <\/div>\n  <div class=\"jz-faq-item\">\n    <div class=\"jz-faq-q\">Is SiC CMP different for 4H-SiC versus 6H-SiC polytypes?<\/div>\n    <div class=\"jz-faq-a\">Yes, modestly. 4H-SiC is the dominant polytype for power devices due to its higher electron mobility and more isotropic electrical properties. 6H-SiC has a slightly different crystal structure and hardness anisotropy \u2014 the C-face (0001\u0304) of 6H-SiC polishes approximately 1.5\u20132\u00d7 faster than the Si-face (0001) under identical conditions, while 4H-SiC shows a smaller Si\/C-face ratio of approximately 1.2\u20131.5\u00d7. Pad selection is not dramatically different between polytypes, but slurry pH and oxidizer concentration may need adjustment to equalize Si-face and C-face removal rates when polishing mixed-face wafers or to optimize for a specific face orientation.<\/div>\n  <\/div>\n<\/div>\n\n<!-- Related Articles -->\n<div class=\"jz-related\">\n  <div class=\"jz-related-title\">\ud83d\udcda Continue Reading \u2014 CMP Pad Deep Dives<\/div>\n  <div class=\"jz-related-grid\">\n    <div class=\"jz-related-item\">\n      <div class=\"jz-related-cat\">PILLAR \u2014 COMPLETE GUIDE<\/div>\n      <a href=\"https:\/\/jeez-semicon.com\/es\/blog\/CMP-Polishing-Pads-The-Complete-Guide\/\" target=\"_blank\">CMP Polishing Pads: The Complete Guide<\/a>\n    <\/div>\n    <div class=\"jz-related-item\">\n      <div class=\"jz-related-cat\">FUNDAMENTALS<\/div>\n      <a href=\"https:\/\/jeez-semicon.com\/es\/blog\/What-Is-a-CMP-Polishing-Pad-The-Ultimate-Guide\/\" target=\"_blank\">What Is a CMP Polishing Pad? The Ultimate Guide<\/a>\n    <\/div>\n    <div class=\"jz-related-item\">\n      <div class=\"jz-related-cat\">FUNDAMENTALS<\/div>\n      <a href=\"https:\/\/jeez-semicon.com\/es\/blog\/How-CMP-Polishing-Pads-Work\/\" target=\"_blank\">How CMP Polishing Pads Work<\/a>\n    <\/div>\n    <div class=\"jz-related-item\">\n      <div class=\"jz-related-cat\">MATERIALS<\/div>\n      <a href=\"https:\/\/jeez-semicon.com\/es\/blog\/CMP-Pad-Materials-Polyurethane-vs-Other-Options\/\" target=\"_blank\">CMP Pad Materials: Polyurethane vs Other Options<\/a>\n    <\/div>\n    <div class=\"jz-related-item\">\n      <div class=\"jz-related-cat\">SELECTION<\/div>\n      <a href=\"https:\/\/jeez-semicon.com\/es\/blog\/Hard-vs-Soft-CMP-Polishing-Pads-Selection-Guide\/\" target=\"_blank\">Hard vs. Soft CMP Polishing Pads: Selection Guide<\/a>\n    <\/div>\n    <div class=\"jz-related-item\">\n      <div class=\"jz-related-cat\">APPLICATIONS<\/div>\n      <a href=\"https:\/\/jeez-semicon.com\/es\/blog\/Semiconductor-CMP-Polishing-Pads\/\" target=\"_blank\">Semiconductor CMP Polishing Pads<\/a>\n    <\/div>\n    <div class=\"jz-related-item\">\n      <div class=\"jz-related-cat\">CUSTOMIZATION<\/div>\n      <a href=\"https:\/\/jeez-semicon.com\/es\/blog\/Custom-CMP-Polishing-Pad-Solutions\/\" target=\"_blank\">Custom CMP Polishing Pad Solutions<\/a>\n    <\/div>\n    <div class=\"jz-related-item\">\n      <div class=\"jz-related-cat\">ENGINEERING<\/div>\n      <a href=\"https:\/\/jeez-semicon.com\/es\/blog\/CMP-Pad-Groove-Design-and-Slurry-Distribution\/\" target=\"_blank\">CMP Pad Groove Design and Slurry Distribution<\/a>\n    <\/div>\n    <div class=\"jz-related-item\">\n      <div class=\"jz-related-cat\">OPERATIONS<\/div>\n      <a href=\"https:\/\/jeez-semicon.com\/es\/blog\/CMP-Pad-Conditioning-and-Lifespan-Management\/\" target=\"_blank\">CMP Pad Conditioning and Lifespan Management<\/a>\n    <\/div>\n    <div class=\"jz-related-item\">\n      <div class=\"jz-related-cat\">PROCESS<\/div>\n      <a href=\"https:\/\/jeez-semicon.com\/es\/blog\/CMP-Material-Removal-Rate-and-Pad-Parameters\/\" target=\"_blank\">CMP Material Removal Rate and Pad Parameters<\/a>\n    <\/div>\n    <div class=\"jz-related-item\">\n      <div class=\"jz-related-cat\">TECHNOLOGY<\/div>\n      <a href=\"https:\/\/jeez-semicon.com\/es\/blog\/Poreless-CMP-Pads-vs-Porous-Structure\/\" target=\"_blank\">Poreless CMP Pads vs. Porous Structure<\/a>\n    <\/div>\n    <div class=\"jz-related-item\">\n      <div class=\"jz-related-cat\">PROCUREMENT<\/div>\n      <a href=\"https:\/\/jeez-semicon.com\/es\/blog\/CMP-Polishing-Pad-Price-Factors-and-Buying-Guide\/\" target=\"_blank\">CMP Polishing Pad Price Factors and Buying Guide<\/a>\n    <\/div>\n  <\/div>\n<\/div>\n\n<!-- CTA -->\n<div class=\"jz-cta-banner\">\n  <h2>SiC and GaN CMP Pads \u2014 Purpose-Built for Third-Generation Semiconductors<\/h2>\n  <p>Jizhi Electronic Technology&#8217;s JZ-SiC and JZ-GaN pad series are engineered for the extreme demands of wide-bandgap semiconductor polishing. Polycarbonate-backbone PU, high chemical resistance, full process characterization data, and application engineering support included.<\/p>\n  <a class=\"jz-btn jz-btn-white\" href=\"https:\/\/jeez-semicon.com\/es\/semi-categories\/polishing-pad\/\" target=\"_blank\">Browse SiC CMP Pads<\/a>\n  <a class=\"jz-btn jz-btn-outline\" href=\"https:\/\/jeez-semicon.com\/es\/contact\/\" target=\"_blank\">Request SiC Pad Data Sheet<\/a>\n<\/div>\n\n<!--\n  \u2554\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\n  \u2551  SEO NOTES \u2014 Cluster 5\n  \u2560\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\n  \u2551  Title tag:  SiC CMP Polishing Pads for Third-Generation Semiconductors (2026)\n  \u2551  Meta desc:  Complete guide to CMP polishing pads for SiC and GaN \u2014 material\n  \u2551              challenges, pad requirements, 3-stage process, slurry compatibility,\n  \u2551              and Jizhi's JZ-SiC series. April 2026.\n  \u2551  Focus KW:   SiC CMP polishing pad\n  \u2551  Secondary:  silicon carbide polishing pad, GaN CMP pad, SiC wafer CMP,\n  \u2551              third generation semiconductor CMP, wide bandgap CMP pad\n  \u2551  Schema:     Article + FAQPage\n  \u2551  Intent:     Informational \/ Technical research \/ Commercial investigation\n  \u255a\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\n-->\n\n<\/div><!-- .jz-art -->","protected":false},"excerpt":{"rendered":"<p>Back to CMP Polishing Pads: The Complete Guide Jizhi Electronic Technology \u2014 Applications Series A complete technical guide to CMP polishing pads for silicon carbide, gallium nitride, and other third-generation  &#8230;<\/p>","protected":false},"author":1,"featured_media":1810,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[9,59],"tags":[],"class_list":["post-1770","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-blog","category-industry"],"acf":[],"_links":{"self":[{"href":"https:\/\/jeez-semicon.com\/es\/wp-json\/wp\/v2\/posts\/1770","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/jeez-semicon.com\/es\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/jeez-semicon.com\/es\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/es\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/es\/wp-json\/wp\/v2\/comments?post=1770"}],"version-history":[{"count":2,"href":"https:\/\/jeez-semicon.com\/es\/wp-json\/wp\/v2\/posts\/1770\/revisions"}],"predecessor-version":[{"id":1772,"href":"https:\/\/jeez-semicon.com\/es\/wp-json\/wp\/v2\/posts\/1770\/revisions\/1772"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/es\/wp-json\/wp\/v2\/media\/1810"}],"wp:attachment":[{"href":"https:\/\/jeez-semicon.com\/es\/wp-json\/wp\/v2\/media?parent=1770"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/jeez-semicon.com\/es\/wp-json\/wp\/v2\/categories?post=1770"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/jeez-semicon.com\/es\/wp-json\/wp\/v2\/tags?post=1770"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}