{"id":1782,"date":"2026-04-07T15:55:33","date_gmt":"2026-04-07T07:55:33","guid":{"rendered":"https:\/\/jeez-semicon.com\/?p=1782"},"modified":"2026-04-07T16:36:14","modified_gmt":"2026-04-07T08:36:14","slug":"cmp-pad-defect-control-scratches-and-uniformity","status":"publish","type":"post","link":"https:\/\/jeez-semicon.com\/es\/blog\/cmp-pad-defect-control-scratches-and-uniformity\/","title":{"rendered":"CMP Pad Defect Control: Scratches, Uniformity, and Surface Quality"},"content":{"rendered":"<!-- CLUSTER 9 \u2014 CMP Pad Defect Control: Scratches and Uniformity --><!-- ============================================================\r\n     Jizhi Electronic Technology Co., Ltd. | April 2026\r\n     URL: \/blog\/CMP-Pad-Defect-Control-Scratches-and-Uniformity\r\n     ============================================================ -->\r\n<p><style>\r\n@import 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.2s}\r\n.jz-btn:hover{transform:translateY(-2px);text-decoration:none}\r\n.jz-btn-white{background:#fff;color:var(--c-primary)}\r\n.jz-btn-white:hover{box-shadow:0 4px 20px rgba(0,0,0,.18);color:var(--c-primary)}\r\n.jz-btn-outline{background:transparent;color:#fff;border:2px solid rgba(255,255,255,.6);margin-left:12px}\r\n.jz-btn-outline:hover{background:rgba(255,255,255,.12);color:#fff}\r\n.jz-faq{margin:28px 0}\r\n.jz-faq-item{border:1px solid var(--c-border);border-radius:var(--radius);margin-bottom:12px;overflow:hidden;background:var(--c-surface)}\r\n.jz-faq-q{padding:16px 20px;font-weight:600;font-size:15px;color:var(--c-primary-dark);display:flex;justify-content:space-between;align-items:center}\r\n.jz-faq-q::after{content:'+';font-size:20px;font-weight:300;color:var(--c-accent);flex-shrink:0}\r\n.jz-faq-a{padding:0 20px 16px;font-size:15px;color:#3a4255;line-height:1.75}\r\n@media(max-width:640px){.jz-hero{padding:36px 24px 32px}.jz-cta-banner{padding:32px 22px}.jz-related{padding:24px 18px}.jz-btn-outline{margin-left:0;margin-top:10px;display:inline-block}}\r\n<\/style><\/p>\r\n<div class=\"jz-art\"><a class=\"jz-back\" href=\"https:\/\/jeez-semicon.com\/es\/blog\/CMP-Polishing-Pads-The-Complete-Guide\/\" target=\"_blank\" rel=\"noopener\">Back to CMP Polishing Pads: The Complete Guide<\/a>\r\n<div class=\"jz-hero\">\r\n<div class=\"jz-hero-kicker\">Jizhi Electronic Technology \u2014 Quality Series<\/div>\r\n<h1>CMP Pad Defect Control: Scratches, Uniformity, and Surface Quality<\/h1>\r\n<p class=\"jz-hero-lead\">A systematic guide to identifying, diagnosing, and eliminating the post-CMP defect types most commonly caused by polishing pad properties \u2014 from micro-scratches and particle residues to edge-exclusion non-uniformity and pitting.<\/p>\r\n<div class=\"jz-hero-meta\">\ud83d\udcc5 April 2026\u23f1 13 min read\ud83c\udfed Jizhi Electronic Technology Co., Ltd.<\/div>\r\n<\/div>\r\n<div class=\"jz-tags\"><span class=\"jz-tag\">CMP Defect Control<\/span> <span class=\"jz-tag\">Scratch Defects<\/span> <span class=\"jz-tag\">WIWNU<\/span> <span class=\"jz-tag\">Calidad de la superficie<\/span> <span class=\"jz-tag\">Post-CMP Inspection<\/span> <span class=\"jz-tag\">Edge Exclusion<\/span> <span class=\"jz-tag\">Yield<\/span><\/div>\r\n<div class=\"jz-trust\">\r\n<div class=\"jz-trust-badge\">Yield<br \/>Focus<\/div>\r\n<div class=\"jz-trust-text\"><strong>Written by Jizhi Electronic Technology Co., Ltd.<\/strong> \u2014 CMP pad manufacturer with in-house defect characterization capability. Defect analysis and root cause mapping in this guide reflects our R&amp;D findings and current April 2026 fab best practice.<\/div>\r\n<\/div>\r\n<div class=\"jz-toc\">\r\n<div class=\"jz-toc-title\">\ud83d\udccb Table of Contents<\/div>\r\n<ol>\r\n<li><a href=\"#defect-landscape\">The CMP Defect Landscape<\/a><\/li>\r\n<li><a href=\"#scratch-types\">Scratch Types and Their Pad Origins<\/a><\/li>\r\n<li><a href=\"#particle-residue\">Particle Residues and Contamination<\/a><\/li>\r\n<li><a href=\"#uniformity\">Within-Wafer Uniformity: Sources and Metrics<\/a><\/li>\r\n<li><a href=\"#edge-exclusion\">Edge Exclusion Non-Uniformity<\/a><\/li>\r\n<li><a href=\"#pitting\">Pitting and Corrosion Defects<\/a><\/li>\r\n<li><a href=\"#diagnosis\">Defect Diagnosis: Root Cause Matrix<\/a><\/li>\r\n<li><a href=\"#pad-selection-defects\">Pad Selection for Defect Minimization<\/a><\/li>\r\n<li><a href=\"#inspection\">Post-CMP Inspection Strategy<\/a><\/li>\r\n<li><a href=\"#faq\">FAQ<\/a><\/li>\r\n<\/ol>\r\n<\/div>\r\n<p>Post-CMP surface defects are one of the top yield loss mechanisms in advanced semiconductor manufacturing. A single scratch propagating through a critical metal interconnect layer can open-circuit the conductor; a cluster of particles left on the wafer surface before a thermal anneal can cause localized dielectric breakdown. At leading-edge process nodes (7 nm and below), the allowed post-CMP defect density is measured in single digits per wafer \u2014 defect levels that were considered impossible targets just a decade ago.<\/p>\r\n<p>The polishing pad is not the only source of CMP defects \u2014 slurry chemistry, conditioner disk condition, post-CMP cleaning, and tool mechanical issues all contribute. But pad properties are among the most controllable and impactful variables available to process engineers. This guide provides a systematic framework for understanding which pad properties contribute to each defect type and how to minimize them. For how pad properties affect removal rate alongside defects, see: <a class=\"jz-link-chip\" href=\"https:\/\/jeez-semicon.com\/es\/blog\/CMP-Material-Removal-Rate-and-Pad-Parameters\/\" target=\"_blank\" rel=\"noopener\">CMP Material Removal Rate and Pad Parameters<\/a>.<\/p>\r\n<div class=\"jz-stats\">\r\n<div class=\"jz-stat\">\r\n<div class=\"jz-stat-num\">&lt;10<\/div>\r\n<div class=\"jz-stat-label\">Post-CMP scratches per wafer \u2014 target at advanced logic fabs (7 nm and below)<\/div>\r\n<\/div>\r\n<div class=\"jz-stat\">\r\n<div class=\"jz-stat-num\">&lt;1%<\/div>\r\n<div class=\"jz-stat-label\">WIWNU (1\u03c3) target for Cu BEOL CMP at advanced nodes<\/div>\r\n<\/div>\r\n<div class=\"jz-stat\">\r\n<div class=\"jz-stat-num\">3\u20135\u00d7<\/div>\r\n<div class=\"jz-stat-label\">Higher scratch density on hard pads vs. soft pads at equivalent process conditions<\/div>\r\n<\/div>\r\n<div class=\"jz-stat\">\r\n<div class=\"jz-stat-num\">2 mm<\/div>\r\n<div class=\"jz-stat-label\">Typical edge exclusion zone width at 300 mm wafer edge in production CMP<\/div>\r\n<\/div>\r\n<\/div>\r\n<h2 id=\"defect-landscape\">1. The CMP Defect Landscape<\/h2>\r\n<p>CMP-generated defects fall into four severity tiers based on their impact on device yield and reliability. Understanding where pad properties contribute \u2014 and where they do not \u2014 is the first step in targeted defect reduction.<\/p>\r\n<div class=\"jz-defect-matrix\">\r\n<div class=\"jz-defect-card critical\">\r\n<div class=\"jz-defect-severity\">Critical \u2014 Direct Yield Loss<\/div>\r\n<div class=\"jz-defect-title\">Deep Scratches (&gt;50 nm depth)<\/div>\r\n<div class=\"jz-defect-desc\">Penetrate through thin dielectric or barrier layers into active device regions. Cause open circuits, junction shorts, or reliability failures. Zero tolerance in production \u2014 one deep scratch per wafer is one too many. Primary pad-related causes: over-conditioned hard pad; agglomerated abrasive particles trapped under pad debris.<\/div>\r\n<\/div>\r\n<div class=\"jz-defect-card major\">\r\n<div class=\"jz-defect-severity\">Major \u2014 Yield Impact at Scale<\/div>\r\n<div class=\"jz-defect-title\">Micro-Scratches (5\u201350 nm depth)<\/div>\r\n<div class=\"jz-defect-desc\">Individually below electrical failure threshold but cause reliability issues (stress-induced voiding, electromigration acceleration) and compound into yield loss at high densities. Pad hardness, asperity distribution, and conditioning protocol are primary controls.<\/div>\r\n<\/div>\r\n<div class=\"jz-defect-card minor\">\r\n<div class=\"jz-defect-severity\">Major \u2014 Uniformity-Driven Yield Loss<\/div>\r\n<div class=\"jz-defect-title\">Within-Wafer Non-Uniformity<\/div>\r\n<div class=\"jz-defect-desc\">Film thickness variation across the wafer after CMP \u2014 not a surface defect but a process outcome defect. High WIWNU causes devices at the edge or center to be out-of-spec even when the mean is correct. Pad compressibility, groove design, and retaining ring geometry are primary controls.<\/div>\r\n<\/div>\r\n<div class=\"jz-defect-card cosmetic\">\r\n<div class=\"jz-defect-severity\">Minor \u2014 Manageable with Post-CMP Clean<\/div>\r\n<div class=\"jz-defect-title\">Particle Residues<\/div>\r\n<div class=\"jz-defect-desc\">Spent slurry particles, pad polymer debris, and reaction byproducts deposited on the post-CMP surface. Removable by post-CMP brush cleaning in most cases. Become yield-critical if post-CMP cleaning is insufficient or if particles are mechanically embedded in soft film surfaces.<\/div>\r\n<\/div>\r\n<\/div>\r\n<h2 id=\"scratch-types\">2. Scratch Types and Their Pad Origins<\/h2>\r\n<p>Not all scratches have the same origin or require the same corrective action. The first step in scratch defect reduction is correctly classifying the scratch type from post-CMP inspection data.<\/p>\r\n<div class=\"jz-table-wrap\">\r\n<table class=\"jz-table\">\r\n<thead>\r\n<tr>\r\n<th>Scratch Type<\/th>\r\n<th>Inspection Signature<\/th>\r\n<th>Primary Pad-Related Cause<\/th>\r\n<th>Corrective Action<\/th>\r\n<\/tr>\r\n<\/thead>\r\n<tbody>\r\n<tr>\r\n<td><strong>Deep linear scratch<\/strong><\/td>\r\n<td>Long, straight or curved groove; consistent width; depth &gt;50 nm by AFM<\/td>\r\n<td>Large debris particle (pad chunk, agglomerated slurry) trapped between pad and wafer<\/td>\r\n<td>Increase in-situ DI water flush; improve slurry filtration; check conditioner disk for chipping<\/td>\r\n<\/tr>\r\n<tr>\r\n<td><strong>Micro-scratch field<\/strong><\/td>\r\n<td>Dense population of fine, short scratches distributed across full wafer; depth &lt;20 nm<\/td>\r\n<td>Over-conditioned pad (high Ra); hard pad at excessive pressure; abrasive particle size too large<\/td>\r\n<td>Reduce conditioner down-force; lower down-force pressure; switch to finer abrasive or softer pad<\/td>\r\n<\/tr>\r\n<tr>\r\n<td><strong>Arc scratches<\/strong><\/td>\r\n<td>Scratches follow circular arc pattern corresponding to platen or carrier rotation<\/td>\r\n<td>Periodic hard particle source rotating with pad \u2014 conditioner disk edge chipping or pad debris embedded in groove<\/td>\r\n<td>Inspect and replace conditioner disk; clean groove network; check pad surface for embedded particles<\/td>\r\n<\/tr>\r\n<tr>\r\n<td><strong>Edge scratch ring<\/strong><\/td>\r\n<td>Scratch density elevated in a ring near wafer edge (1\u20135 mm from edge)<\/td>\r\n<td>Retaining ring debris or retaining ring-pad contact creating abrasive debris at wafer perimeter<\/td>\r\n<td>Check retaining ring wear; adjust retaining ring pressure; ensure pad is properly seated and flat at edge<\/td>\r\n<\/tr>\r\n<tr>\r\n<td><strong>Center pit cluster<\/strong><\/td>\r\n<td>Localized pitting at wafer center; associated with low-pH slurry<\/td>\r\n<td>Slurry starvation at wafer center (groove design insufficient for center delivery) combined with chemical attack on unpolished film regions<\/td>\r\n<td>Switch to finer-pitch groove pad; increase slurry flow rate; verify groove is not clogged at center<\/td>\r\n<\/tr>\r\n<\/tbody>\r\n<\/table>\r\n<\/div>\r\n<div class=\"jz-callout warn\">\r\n<div class=\"jz-callout-icon\">\u26a0\ufe0f<\/div>\r\n<div class=\"jz-callout-body\"><strong>Scratch Excursions: Always Check the Conditioner Disk First<\/strong> When a sudden increase in scratch density is observed \u2014 especially deep linear scratches \u2014 the conditioner disk is the most common cause, not the polishing pad. Diamond conditioner disks that have shed a diamond crystal leave a hard, irregularly shaped particle on the pad surface that can plow across the entire wafer diameter. Always perform a pad surface inspection (visual and optical) and conditioner disk inspection (SEM or optical microscope of disk surface) before blaming the pad for a scratch excursion.<\/div>\r\n<\/div>\r\n<h2 id=\"particle-residue\">3. Particle Residues and Pad-Related Contamination<\/h2>\r\n<p>Particle residues on the post-CMP wafer surface fall into three categories based on origin, with different pad design implications for each:<\/p>\r\n<div class=\"jz-card-grid\">\r\n<div class=\"jz-card\">\r\n<div class=\"jz-card-icon\">\ud83d\udd35<\/div>\r\n<h4>Slurry Abrasive Residues<\/h4>\r\n<p>Spent or agglomerated abrasive particles (silica, ceria) that were not swept away by groove transport. Linked to insufficient groove drainage. Fine-pitch grooves and spiral patterns reduce this defect type by improving byproduct evacuation frequency. Primarily controlled by groove design and slurry flow rate, not pad hardness.<\/p>\r\n<\/div>\r\n<div class=\"jz-card\">\r\n<div class=\"jz-card-icon\">\ud83d\udfe0<\/div>\r\n<h4>Pad Polymer Debris<\/h4>\r\n<p>Fragments of polyurethane shed from the pad surface during conditioning or polishing. Higher in early pad life (break-in debris) and in over-conditioned pads. Poreless pads dramatically reduce this defect type by eliminating the pore-derived debris source. Pad polymer debris is the primary differentiator between porous and poreless pad defect performance.<\/p>\r\n<\/div>\r\n<div class=\"jz-card\">\r\n<div class=\"jz-card-icon\">\ud83d\udfe1<\/div>\r\n<h4>Reaction Byproduct Deposits<\/h4>\r\n<p>Precipitates from dissolved film material (Cu\u00b2\u207a-BTA complexes in Cu CMP, WO\u2084\u00b2\u207b in W CMP) that re-deposit on the wafer surface when groove drainage is insufficient. Controlled by groove depth and pitch \u2014 deeper, finer-pitch grooves provide more frequent and complete byproduct evacuation. Also controlled by slurry pH and complexing agent concentration.<\/p>\r\n<\/div>\r\n<\/div>\r\n<h2 id=\"uniformity\">4. Within-Wafer Uniformity: Sources, Metrics, and Pad Controls<\/h2>\r\n<p>Within-wafer non-uniformity (WIWNU) is measured as the standard deviation (1\u03c3) of post-CMP film thickness across a multi-point wafer map, expressed as a percentage of mean remaining thickness. At advanced nodes, WIWNU targets of below 1% (1\u03c3) are standard for CMP steps preceding critical lithography levels. Three pad-related mechanisms generate WIWNU:<\/p>\r\n<ul>\r\n<li><strong>Asperity height non-uniformity:<\/strong> If asperity height distribution is not uniform across the pad radius, contact pressure varies radially, causing radial MRR variation. This is controlled by pad surface Ra uniformity \u2014 a key QC metric that Jizhi measures across all production pads.<\/li>\r\n<li><strong>Slurry delivery non-uniformity:<\/strong> Groove design that delivers slurry unevenly across the wafer diameter generates center-high or edge-high removal profiles. Addressed by groove pitch optimization or zone-varying patterns.<\/li>\r\n<li><strong>Macro-scale pad flatness:<\/strong> A pad that is not flat (due to mounting defects or uneven wear) delivers non-uniform pressure distribution across the wafer, generating wafer-scale MRR gradients. Pad thickness uniformity (&lt;0.05 mm 5-point variation) is a Jizhi production release criterion.<\/li>\r\n<\/ul>\r\n<h2 id=\"edge-exclusion\">5. Edge Exclusion Non-Uniformity<\/h2>\r\n<p>Edge exclusion (EE) non-uniformity \u2014 systematically higher or lower removal at the wafer edge compared to the center \u2014 is one of the most persistent CMP uniformity challenges on 300 mm wafers. It has two primary origins that require different pad-related corrective actions:<\/p>\r\n<div class=\"jz-table-wrap\">\r\n<table class=\"jz-table\">\r\n<thead>\r\n<tr>\r\n<th>Edge Profile Type<\/th>\r\n<th>Likely Cause<\/th>\r\n<th>Pad-Related Correction<\/th>\r\n<\/tr>\r\n<\/thead>\r\n<tbody>\r\n<tr>\r\n<td><strong>Edge-fast (over-removal at edge)<\/strong><\/td>\r\n<td>Retaining ring pressure higher than carrier down-force; hard pad with low compressibility; high wafer bow concentrating stress at edge<\/td>\r\n<td>Switch to softer subpad or stacked pad to increase edge compliance; verify retaining ring pressure calibration; reduce conditioner down-force to lower edge-zone Ra<\/td>\r\n<\/tr>\r\n<tr>\r\n<td><strong>Edge-slow (under-removal at edge)<\/strong><\/td>\r\n<td>Slurry starvation near wafer edge \u2014 centrifugal force drains groove channels before reaching wafer periphery; low carrier-to-platen velocity ratio at outer wafer radius<\/td>\r\n<td>Switch to spiral groove pattern to enhance centrifugal delivery to pad edge; increase slurry flow rate; reduce groove pitch in outer pad zone<\/td>\r\n<\/tr>\r\n<tr>\r\n<td><strong>Oscillating profile (ring pattern)<\/strong><\/td>\r\n<td>Groove interference pattern \u2014 standing wave in slurry delivery as specific groove-wafer alignment repeats at fixed intervals<\/td>\r\n<td>Change groove pitch to a value incommensurate with carrier oscillation frequency; switch from concentric to XY or spiral pattern to eliminate angular interference<\/td>\r\n<\/tr>\r\n<\/tbody>\r\n<\/table>\r\n<\/div>\r\n<h2 id=\"pitting\">6. Pitting and Corrosion Defects<\/h2>\r\n<p>Pitting \u2014 small, localized depressions in the polished film surface \u2014 is chemically rather than mechanically driven, but pad groove design plays a contributing role. Pitting occurs when slurry chemistry attacks the wafer film at a locally elevated rate in areas of low or stagnant slurry renewal. The relevant pad design connection: pads with insufficient groove drainage (shallow grooves, wide pitch) create zones of slurry stagnation under the wafer where spent, enriched slurry accumulates. In Cu CMP, this enriched slurry can cause local galvanic corrosion; in oxide CMP, it can cause etch-back of the dielectric at pH-excursion zones. Optimized groove design that ensures complete slurry renewal on every platen revolution is the pad-level mitigation.<\/p>\r\n<h2 id=\"diagnosis\">7. Defect Diagnosis: Root Cause Matrix<\/h2>\r\n<div class=\"jz-table-wrap\">\r\n<table class=\"jz-table\">\r\n<thead>\r\n<tr>\r\n<th>Observation<\/th>\r\n<th>Most Likely Pad-Related Root Cause<\/th>\r\n<th>Verification Test<\/th>\r\n<th>Primary Corrective Action<\/th>\r\n<\/tr>\r\n<\/thead>\r\n<tbody>\r\n<tr>\r\n<td>Sudden scratch density increase (all types)<\/td>\r\n<td>Conditioner disk damage \/ particle shedding<\/td>\r\n<td>SEM inspection of conditioner disk surface<\/td>\r\n<td>Replace conditioner disk; clean pad surface with DI flush<\/td>\r\n<\/tr>\r\n<tr>\r\n<td>Gradual micro-scratch density increase over pad life<\/td>\r\n<td>Over-conditioning or pad surface Ra drifting high<\/td>\r\n<td>Profilometer Ra measurement of pad surface<\/td>\r\n<td>Reduce conditioner down-force; verify conditioning frequency<\/td>\r\n<\/tr>\r\n<tr>\r\n<td>Center-low MRR (concave profile)<\/td>\r\n<td>Slurry starvation at wafer center \u2014 groove design or flow rate<\/td>\r\n<td>Test with 50% higher slurry flow rate \u2014 if profile improves, groove\/flow is limiting<\/td>\r\n<td>Switch to finer-pitch or spiral groove pad; increase slurry flow<\/td>\r\n<\/tr>\r\n<tr>\r\n<td>High particle count, distributed uniformly<\/td>\r\n<td>Pad polymer debris from over-conditioned or worn pad<\/td>\r\n<td>EDX analysis of particles \u2014 polymer vs. slurry<\/td>\r\n<td>Replace pad; reduce conditioning intensity; consider poreless pad<\/td>\r\n<\/tr>\r\n<tr>\r\n<td>High particle count at wafer center only<\/td>\r\n<td>Byproduct re-deposition from groove stagnation at center<\/td>\r\n<td>Increase slurry flow \u2014 if particles decrease, groove drainage is limiting<\/td>\r\n<td>Finer-pitch groove pad; increase groove depth; increase slurry flow<\/td>\r\n<\/tr>\r\n<tr>\r\n<td>Edge-fast removal profile worsening with pad age<\/td>\r\n<td>Pad non-uniformity increasing as edge wears faster than center<\/td>\r\n<td>5-point pad thickness map \u2014 confirm edge-thin<\/td>\r\n<td>Replace pad; adjust conditioning sweep profile to equalize wear<\/td>\r\n<\/tr>\r\n<\/tbody>\r\n<\/table>\r\n<\/div>\r\n<h2 id=\"pad-selection-defects\">8. Pad Selection for Defect Minimization<\/h2>\r\n<p>The following pad selection guidance prioritizes defect performance \u2014 recommended when post-CMP defect density is the primary process constraint, even at some cost to throughput:<\/p>\r\n<ul>\r\n<li><strong>For scratch defect reduction:<\/strong> Select the softest pad hardness consistent with meeting planarization efficiency requirements. For Cu BEOL buff steps, Shore D 28\u201338 with fine-grit conditioner (D40\u2013D60). For oxide steps where both planarity and low scratches are required, consider a stacked configuration (IC1000-type top + very soft subpad) to get hard-pad planarization with reduced edge contact stress.<\/li>\r\n<li><strong>For particle residue reduction:<\/strong> Consider poreless pads, which eliminate the primary source of pad polymer debris. Switch to finer-pitch grooves to improve slurry byproduct evacuation. Verify post-CMP cleaning compatibility with your particle types.<\/li>\r\n<li><strong>For WIWNU reduction:<\/strong> Select a pad with higher compressibility (softer subpad in stacked configuration, or softer top pad) to improve macro-scale wafer conformance. Switch to finer-pitch or spiral groove pattern for better slurry uniformity. For the full selection framework, see: <a class=\"jz-link-chip\" href=\"https:\/\/jeez-semicon.com\/es\/blog\/Hard-vs-Soft-CMP-Polishing-Pads-Selection-Guide\/\" target=\"_blank\" rel=\"noopener\">Hard vs. Soft CMP Polishing Pads: Selection Guide<\/a>.<\/li>\r\n<\/ul>\r\n<h2 id=\"inspection\">9. Post-CMP Inspection Strategy<\/h2>\r\n<p>Effective defect management requires a structured post-CMP inspection program. The following inspection layers work together to catch different defect types:<\/p>\r\n<ul>\r\n<li><strong>Optical surface inspection (KLA, Hitachi, AMAT):<\/strong> Dark-field and bright-field wafer scanning after every CMP step for production wafers. Captures scratches &gt;20 nm depth and particles &gt;50 nm diameter. The primary in-line defect detection tool.<\/li>\r\n<li><strong>AFM (atomic force microscopy):<\/strong> Periodic off-line measurement of surface roughness Ra and sub-10 nm surface features. Required for qualifying new pads and verifying that conditioning protocol changes do not degrade surface quality.<\/li>\r\n<li><strong>SEM-EDX:<\/strong> Used for particle origin analysis when optical inspection identifies elevated particle counts \u2014 distinguishes pad polymer debris from slurry abrasive from process film fragments by elemental analysis.<\/li>\r\n<li><strong>Sheet resistance mapping (4-point probe):<\/strong> For metal CMP steps \u2014 measures electrical thickness uniformity as a proxy for WIWNU. Catches uniformity issues that optical inspection misses.<\/li>\r\n<\/ul>\r\n<div class=\"jz-callout success\">\r\n<div class=\"jz-callout-icon\">\u2705<\/div>\r\n<div class=\"jz-callout-body\"><strong>Jizhi Defect Qualification Package<\/strong> For customers qualifying Jizhi CMP pads in defect-sensitive applications (Cu BEOL, low-k dielectric, SiC device layer), we provide a defect qualification data package including: post-CMP KLA inspection results from our in-house test wafer lots (scratch density, particle count), AFM surface roughness data from conditioned pad surface, and recommended conditioning protocol to minimize pad polymer debris during break-in. Contact our application engineering team to receive the relevant package for your process step.<\/div>\r\n<\/div>\r\n<h2>10. Frequently Asked Questions<\/h2>\r\n<div class=\"jz-faq\">\r\n<div class=\"jz-faq-item\">\r\n<div class=\"jz-faq-q\">How do I distinguish pad-caused scratches from slurry-caused scratches?<\/div>\r\n<div class=\"jz-faq-a\">The distinction is made by controlled experiment: run a split lot alternating between your current pad (control) and a new pad (test) with all other process parameters identical, including slurry lot, conditioning disk, and recipe. If scratch density changes proportionally to the pad change, the pad is the primary driver. If scratch density is the same, the slurry, conditioner disk, or tool is the root cause. Additionally, scratch morphology provides clues: slurry agglomerate scratches tend to be irregular in width and depth; pad debris scratches tend to be wider and shallower; conditioner disk shedding produces very long, deep, consistent-width scratches.<\/div>\r\n<\/div>\r\n<div class=\"jz-faq-item\">\r\n<div class=\"jz-faq-q\">Can WIWNU be improved without changing the pad?<\/div>\r\n<div class=\"jz-faq-a\">Yes \u2014 several recipe adjustments improve WIWNU without pad change: reducing down-force pressure (reduces the contribution of wafer bow to edge-center pressure variation), adjusting carrier oscillation frequency (changes the geometric averaging of pad-wafer contact), increasing slurry flow rate (improves radial slurry uniformity), and adjusting retaining ring pressure (controls edge loading independently of carrier down-force). However, if WIWNU is fundamentally limited by pad compressibility or groove design \u2014 as it often is for 300 mm wafers with high incoming bow \u2014 pad selection changes are the most impactful lever.<\/div>\r\n<\/div>\r\n<div class=\"jz-faq-item\">\r\n<div class=\"jz-faq-q\">Why do scratch defects often increase at the end of pad life?<\/div>\r\n<div class=\"jz-faq-a\">Three concurrent mechanisms drive higher scratch density near pad end-of-life. First, reduced groove depth (from cumulative wear) impairs byproduct removal, increasing the probability of abrasive agglomerate accumulation at the pad-wafer interface. Second, as the pad thins toward the backing layer, bulk mechanical response changes \u2014 local stiffness can increase in some pad designs, increasing contact stress at asperity tips. Third, the conditioning protocol that was optimal for a full-thickness pad may over-condition the thinner end-of-life pad, generating excessive Ra and therefore higher abrasive engagement force. Monitoring pad thickness and adjusting conditioning intensity as pad ages is a best practice for maintaining scratch density control throughout pad lifetime.<\/div>\r\n<\/div>\r\n<div class=\"jz-faq-item\">\r\n<div class=\"jz-faq-q\">What is the relationship between post-CMP cleaning and pad defect performance?<\/div>\r\n<div class=\"jz-faq-a\">Post-CMP cleaning (brush scrubbing, megasonic, or combined) removes particle residues that were deposited during polishing but not evacuated by groove transport. Pad design and post-CMP cleaning are complementary defect controls \u2014 a pad with excellent groove drainage deposits fewer particles, reducing the burden on post-CMP cleaning. However, some residue types \u2014 particularly mechanically embedded particles (forced into soft film surfaces by pad contact force) \u2014 cannot be removed by post-CMP cleaning regardless of cleaning aggressiveness. These embedded defects require pad-level mitigation: softer pad to reduce embedding force, finer-pitch grooves to reduce the time between groove sweeps during which particle accumulation can cause embedding.<\/div>\r\n<\/div>\r\n<\/div>\r\n<div class=\"jz-related\">\r\n<div class=\"jz-related-title\">\ud83d\udcda Continue Reading \u2014 CMP Pad Deep Dives<\/div>\r\n<div class=\"jz-related-grid\">\r\n<div class=\"jz-related-item\">\r\n<div class=\"jz-related-cat\">PILLAR<\/div>\r\n<a href=\"https:\/\/jeez-semicon.com\/es\/blog\/CMP-Polishing-Pads-The-Complete-Guide\/\" target=\"_blank\" rel=\"noopener\">CMP Polishing Pads: The Complete Guide<\/a><\/div>\r\n<div class=\"jz-related-item\">\r\n<div class=\"jz-related-cat\">FUNDAMENTALS<\/div>\r\n<a href=\"https:\/\/jeez-semicon.com\/es\/blog\/How-CMP-Polishing-Pads-Work\/\" target=\"_blank\" rel=\"noopener\">How CMP Polishing Pads Work<\/a><\/div>\r\n<div class=\"jz-related-item\">\r\n<div class=\"jz-related-cat\">SELECTION<\/div>\r\n<a href=\"https:\/\/jeez-semicon.com\/es\/blog\/Hard-vs-Soft-CMP-Polishing-Pads-Selection-Guide\/\" target=\"_blank\" rel=\"noopener\">Hard vs. Soft CMP Polishing Pads: Selection Guide<\/a><\/div>\r\n<div class=\"jz-related-item\">\r\n<div class=\"jz-related-cat\">PROCESS<\/div>\r\n<a href=\"https:\/\/jeez-semicon.com\/es\/blog\/CMP-Material-Removal-Rate-and-Pad-Parameters\/\" target=\"_blank\" rel=\"noopener\">CMP Material Removal Rate and Pad Parameters<\/a><\/div>\r\n<div class=\"jz-related-item\">\r\n<div class=\"jz-related-cat\">OPERATIONS<\/div>\r\n<a href=\"https:\/\/jeez-semicon.com\/es\/blog\/CMP-Pad-Conditioning-and-Lifespan-Management\/\" target=\"_blank\" rel=\"noopener\">CMP Pad Conditioning and Lifespan Management<\/a><\/div>\r\n<div class=\"jz-related-item\">\r\n<div class=\"jz-related-cat\">TECHNOLOGY<\/div>\r\n<a href=\"https:\/\/jeez-semicon.com\/es\/blog\/Poreless-CMP-Pads-vs-Porous-Structure\/\" target=\"_blank\" rel=\"noopener\">Poreless CMP Pads vs. Porous Structure<\/a><\/div>\r\n<div class=\"jz-related-item\">\r\n<div class=\"jz-related-cat\">ENGINEERING<\/div>\r\n<a href=\"https:\/\/jeez-semicon.com\/es\/blog\/CMP-Pad-Groove-Design-and-Slurry-Distribution\/\" target=\"_blank\" rel=\"noopener\">CMP Pad Groove Design and Slurry Distribution<\/a><\/div>\r\n<div class=\"jz-related-item\">\r\n<div class=\"jz-related-cat\">SOURCING<\/div>\r\n<a href=\"https:\/\/jeez-semicon.com\/es\/blog\/CMP-Polishing-Pad-Brands-Comparison\/\" target=\"_blank\" rel=\"noopener\">CMP Polishing Pad Brands Comparison<\/a><\/div>\r\n<div class=\"jz-related-item\">\r\n<div class=\"jz-related-cat\">PROCUREMENT<\/div>\r\n<a href=\"https:\/\/jeez-semicon.com\/es\/blog\/CMP-Polishing-Pad-Price-Factors-and-Buying-Guide\/\" target=\"_blank\" rel=\"noopener\">CMP Polishing Pad Price Factors and Buying Guide<\/a><\/div>\r\n<\/div>\r\n<\/div>\r\n<div class=\"jz-cta-banner\">\r\n<h2>Lower Defect Density Starts with the Right Pad<\/h2>\r\n<p>Jizhi Electronic Technology&#8217;s CMP pad series delivers low defect performance through controlled pore size distribution, optimized groove design, and full defect qualification data packages. Hard pads, soft subpads, and poreless options available.<\/p>\r\n<a class=\"jz-btn jz-btn-white\" href=\"https:\/\/jeez-semicon.com\/es\/semi-categories\/polishing-pad\/\" target=\"_blank\" rel=\"noopener\">Browse CMP Polishing Pads<\/a> <a class=\"jz-btn jz-btn-outline\" href=\"https:\/\/jeez-semicon.com\/es\/contact\/\" target=\"_blank\" rel=\"noopener\">Request Defect Data Package<\/a><\/div>\r\n<\/div>","protected":false},"excerpt":{"rendered":"<p>Back to CMP Polishing Pads: The Complete Guide Jizhi Electronic Technology \u2014 Quality Series CMP Pad Defect Control: Scratches, Uniformity, and Surface Quality A systematic guide to identifying, diagnosing, and  &#8230;<\/p>","protected":false},"author":1,"featured_media":1814,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[9,59],"tags":[],"class_list":["post-1782","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-blog","category-industry"],"acf":[],"_links":{"self":[{"href":"https:\/\/jeez-semicon.com\/es\/wp-json\/wp\/v2\/posts\/1782","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/jeez-semicon.com\/es\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/jeez-semicon.com\/es\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/es\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/es\/wp-json\/wp\/v2\/comments?post=1782"}],"version-history":[{"count":3,"href":"https:\/\/jeez-semicon.com\/es\/wp-json\/wp\/v2\/posts\/1782\/revisions"}],"predecessor-version":[{"id":1824,"href":"https:\/\/jeez-semicon.com\/es\/wp-json\/wp\/v2\/posts\/1782\/revisions\/1824"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/es\/wp-json\/wp\/v2\/media\/1814"}],"wp:attachment":[{"href":"https:\/\/jeez-semicon.com\/es\/wp-json\/wp\/v2\/media?parent=1782"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/jeez-semicon.com\/es\/wp-json\/wp\/v2\/categories?post=1782"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/jeez-semicon.com\/es\/wp-json\/wp\/v2\/tags?post=1782"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}