{"id":2305,"date":"2026-06-09T15:53:59","date_gmt":"2026-06-09T07:53:59","guid":{"rendered":"https:\/\/jeez-semicon.com\/?p=2305"},"modified":"2026-06-09T15:53:59","modified_gmt":"2026-06-09T07:53:59","slug":"post-cmp-cleaning-for-silicon-wafers-methods-and-best-practices","status":"publish","type":"post","link":"https:\/\/jeez-semicon.com\/es\/blog\/post-cmp-cleaning-for-silicon-wafers-methods-and-best-practices\/","title":{"rendered":"Post-CMP Cleaning for Silicon Wafers: Methods and Best Practices"},"content":{"rendered":"<style>\n@import url('https:\/\/fonts.googleapis.com\/css2?family=Sora:wght@400;500;600;700;800&family=IBM+Plex+Sans:ital,wght@0,300;0,400;0,500;0,600;1,400&display=swap');\n.jeez-pillar*,.jeez-pillar*::before,.jeez-pillar*::after{box-sizing:border-box;margin:0;padding:0}\n.jeez-pillar{font-family:'IBM Plex Sans',-apple-system,BlinkMacSystemFont,sans-serif;font-size:17px;line-height:1.78;color:#1C2B3A;max-width:900px;margin:0 auto;padding:0 0 3rem}\n.jeez-pillar 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h2{font-size:1.4rem}.jp-cta{padding:2rem 1.5rem}}\n.jeez-pillar [id]{scroll-margin-top:90px}\n<\/style>\n<div class=\"jeez-pillar\">\n<a href=\"https:\/\/jeez-semicon.com\/es\/blog\/The-Complete-Guide-to-Silicon-Wafer-Polishing\/\" target=\"_blank\" class=\"jp-back\">\u2190 Back to: The Complete Guide to Silicon Wafer Polishing<\/a>\n<div class=\"jp-hero\">\n<div class=\"jp-hero-eyebrow\">JEEZ Semiconductor Materials &nbsp;\u00b7&nbsp; Technical Guide &nbsp;\u00b7&nbsp; Updated June 2026<\/div>\n<p class=\"jp-hero-lead\">A complete technical guide to post-CMP cleaning \u2014 covering contamination types, SC-1 particle removal, SC-2 metal removal, DHF dip, megasonic cleaning, brush scrubbing, and Marangoni drying \u2014 with process parameters and LPD performance targets.<\/p>\n<div class=\"jp-hero-meta\">~2,700 words &nbsp;\u00b7&nbsp; 11-minute read &nbsp;\u00b7&nbsp; Published by JEEZ<\/div>\n<\/div>\n<div class=\"jp-toc\"><div class=\"jp-toc-title\">\u00cdndice<\/div><ol><li><a href=\"#intro\">Why Cleaning Is a Process-Defining Step<\/a><\/li><li><a href=\"#contamination\">What Is Left on the Wafer After CMP<\/a><\/li><li><a href=\"#sc1\">SC-1 Cleaning: Particle and Organic Removal<\/a><\/li><li><a href=\"#sc2\">SC-2 Cleaning: Metallic Contamination<\/a><\/li><li><a href=\"#dhf\">DHF Dip: Native Oxide and Surface Passivation<\/a><\/li><li><a href=\"#megasonic\">Megasonic and Brush Scrubbing<\/a><\/li><li><a href=\"#drying\">Final Rinse and Drying<\/a><\/li><li><a href=\"#faq\">Preguntas frecuentes<\/a><\/li><\/ol><\/div>\n\n<section id=\"intro\">\n<h2>Why Post-CMP Cleaning Is a Process-Defining Step, Not a Clean-Up Step<\/h2>\n<p>The most common misconception in silicon wafer CMP operations is that post-process cleaning is simply a rinse to wash away polishing residue \u2014 a trivial step after the real engineering work of CMP is done. In reality, post-CMP cleaning is the step that determines whether the carefully optimized CMP process will translate into a wafer that passes final inspection. A polished surface with Ra = 0.08 nm and excellent SFQR will still fail inspection \u2014 and ultimately be rejected \u2014 if post-CMP cleaning leaves residual particles, organic films, or metallic contamination above specification.<\/p>\n<p>This guide from Jizhi Electronic Technology Co., Ltd. (JEEZ) covers every major cleaning step in the post-CMP sequence, the contamination types each step removes, the process parameters that govern its effectiveness, and how to design an optimized cleaning sequence for your specific application. It is a companion to our broader <a href=\"https:\/\/jeez-semicon.com\/es\/blog\/The-Complete-Guide-to-Silicon-Wafer-Polishing\/\" target=\"_blank\">Complete Guide to Silicon Wafer Polishing<\/a>.<\/p>\n<div class=\"jp-stats\">\n<div class=\"jp-stat\"><span class=\"jp-stat-value\">&lt;1\u00d710\u00b9\u2070<\/span><span class=\"jp-stat-label\">Fe, Cu atoms\/cm\u00b2 \u2014 metallic contamination target after post-CMP cleaning<\/span><\/div>\n<div class=\"jp-stat\"><span class=\"jp-stat-value\">&lt;30<\/span><span class=\"jp-stat-label\">LPD count @ 35 nm threshold on 300mm wafer after clean<\/span><\/div>\n<div class=\"jp-stat\"><span class=\"jp-stat-value\">18.2 M\u03a9\u00b7cm<\/span><span class=\"jp-stat-label\">Minimum DI water resistivity specification for final rinse water<\/span><\/div>\n<\/div>\n<\/section>\n<hr class=\"jp-hr\">\n\n<section id=\"contamination\">\n<h2>What Is Left on the Wafer Surface After CMP?<\/h2>\n<p>Immediately after the polishing step and before any cleaning, the silicon wafer front surface carries a complex mixture of at least four distinct contamination types, each requiring a different chemical approach for effective removal:<\/p>\n<ul>\n<li><strong>Particulate contamination:<\/strong> Residual slurry abrasive particles (colloidal silica, 20\u2013150 nm diameter) that have physically adsorbed to the polished silicon surface. Adhesion is primarily electrostatic: at typical post-polish pH values (9\u201310), the silicon surface carries a slight net charge that can attract or resist particle adhesion depending on the specific surface chemistry. Additional particles include polishing pad debris (polyurethane fragments), environmental contamination from the cleanroom air, and crystalline silicon fragments from the polishing reaction itself.<\/li>\n<li><strong>Organic contamination:<\/strong> Slurry formulations typically contain non-ionic surfactants, chelating agents, and dispersant polymers to maintain abrasive stability and improve surface passivation. These organic additives adsorb onto the polished surface as a thin (~0.5\u20132 nm) organic film. Left in place, they would appear as organic contamination in subsequent thermal process steps (oxidation, epitaxy) and could impact gate dielectric interface quality.<\/li>\n<li><strong>Metallic contamination:<\/strong> Ionic metal species \u2014 principally K\u207a and Na\u207a from the alkaline slurry base (KOH or TMAH), and transition metals (Fe, Cu, Ni, Cr) from polishing pad hardware, platen surfaces, and slurry delivery components \u2014 are present in the slurry liquid and can deposit on the silicon surface during polishing or during the post-polish immersion period. Even trace-level metallic contamination (ppb range) is unacceptable in gate oxide applications because Na\u207a and K\u207a diffuse through SiO\u2082 under bias, causing threshold voltage shift and long-term reliability degradation.<\/li>\n<li><strong>Dissolved silicon species:<\/strong> The polishing reaction dissolves silicon as SiO\u2082\u00b7nH\u2082O (silicic acid). At the high alkaline pH of CMP, silicic acid remains soluble. However, as the wafer is rinsed and the pH drops toward neutral during cleaning, silicic acid can precipitate as amorphous silica micro-deposits on the wafer surface, appearing as LPDs on post-clean inspection. Careful pH management during the rinse steps prevents this re-deposition.<\/li>\n<\/ul>\n<\/section>\n<hr class=\"jp-hr\">\n\n<section id=\"sc1\">\n<h2>SC-1 Cleaning (APM): Particle and Organic Removal<\/h2>\n<p>SC-1 \u2014 named from the original RCA cleaning protocol \u2014 uses an ammonium peroxide mixture (APM) of ammonium hydroxide (NH\u2084OH), hydrogen peroxide (H\u2082O\u2082), and ultra-pure deionized water, typically in a 1:2:10 volume ratio at 65\u201380\u00b0C.<\/p>\n<h3>SC-1 Removal Mechanisms<\/h3>\n<ul>\n<li><strong>Particle removal:<\/strong> SC-1 mildly etches the silicon surface at ~0.5\u20131 nm per minute, &#8220;undercutting&#8221; adhered particles and liberating them from the surface. Simultaneously, the NH\u2084OH raises the surface pH to ~10, ensuring that both the silicon surface and colloidal silica particles carry strongly negative zeta potentials \u2014 creating electrostatic repulsion that keeps dislodged particles from re-adhering. The H\u2082O\u2082 provides an oxidizing environment that helps break down organic coatings that might anchor particles.<\/li>\n<li><strong>Organic removal:<\/strong> H\u2082O\u2082 oxidatively degrades adsorbed organic films (surfactant residues, polymer dispersants) into smaller water-soluble fragments that are rinsed away. The combination of alkaline pH and peroxide is effective against most non-ionic and anionic organic contaminants used in CMP slurry formulations.<\/li>\n<\/ul>\n<h3>SC-1 Operating Conditions<\/h3>\n<div class=\"jp-table-wrap\">\n<table class=\"jp-table\">\n<thead><tr><th>Par\u00e1metro<\/th><th>Standard Range<\/th><th>Notas<\/th><\/tr><\/thead>\n<tbody>\n<tr><td>NH\u2084OH : H\u2082O\u2082 : H\u2082O ratio<\/td><td>1:2:10 to 1:2:20<\/td><td>More dilute ratios reduce etch rate; less effective for tenacious particles<\/td><\/tr>\n<tr><td>Temperature<\/td><td>65\u201380\u00b0C<\/td><td>Higher temperature: faster etch and organic decomposition; risk of ammonia evaporation<\/td><\/tr>\n<tr><td>Immersion time<\/td><td>5\u201310 min<\/td><td>Sufficient for particle removal; longer risks excessive Si etch and roughness increase<\/td><\/tr>\n<tr><td>Megasonic frequency<\/td><td>900 kHz \u2013 1 MHz (when used)<\/td><td>Acoustic cavitation at wafer surface physically dislodges stubborn particles<\/td><\/tr>\n<\/tbody>\n<\/table>\n<\/div>\n<div class=\"jp-callout teal\">\n<strong>Megasonic-enhanced SC-1<\/strong> is more effective for particle removal than immersion SC-1 alone, particularly for tenacious particles &lt;100 nm. Megasonic transducers in the SC-1 bath generate acoustic streaming and micro-cavitation events that physically impart momentum to adhered particles, complementing the chemical undercutting mechanism. For prime-grade 300mm silicon targeting &lt;30 LPDs at 35 nm, megasonic SC-1 is generally necessary.\n<\/div>\n<\/section>\n<hr class=\"jp-hr\">\n\n<section id=\"sc2\">\n<h2>SC-2 Cleaning (HPM): Metallic Contamination Removal<\/h2>\n<p>SC-2 uses a hydrochloric peroxide mixture (HPM) of hydrochloric acid (HCl), hydrogen peroxide (H\u2082O\u2082), and ultra-pure DI water, typically at a 1:1:5 ratio and 70\u201380\u00b0C. SC-2 is specifically engineered for metallic contamination removal \u2014 the contamination type that is most damaging to gate oxide reliability but least visually apparent.<\/p>\n<h3>SC-2 Chemistry<\/h3>\n<p>HCl provides Cl\u207b ions that form stable chloride complexes with transition metals (FeCl\u2083, CuCl\u2082, NiCl\u2082) and alkali metals (KCl, NaCl). These metal chloride complexes are highly soluble in the acidic SC-2 solution and are efficiently removed from the silicon surface into the bulk solution. H\u2082O\u2082 provides an oxidizing environment that promotes metal oxide dissolution and maintains the silicon surface in a passivated (oxidized) state, preventing metal re-adsorption during the cleaning step.<\/p>\n<p>SC-2 is critical for gate oxide applications where K\u207a and Na\u207a \u2014 the primary metallic contaminants from KOH-based CMP slurries \u2014 must be reduced below 1\u00d710\u00b9\u2070 atoms\/cm\u00b2. TMAH-based slurries reduce the K\u207a\/Na\u207a challenge but do not eliminate the need for SC-2, because Fe and Cu from process hardware remain significant contamination sources.<\/p>\n<\/section>\n<hr class=\"jp-hr\">\n\n<section id=\"dhf\">\n<h2>DHF Dip: Native Oxide Removal and Surface Passivation<\/h2>\n<p>A dilute hydrofluoric acid (DHF) dip \u2014 typically 0.5\u20131.0% HF in ultra-pure DI water at room temperature for 30\u201360 seconds \u2014 etches the native silicon oxide (SiO\u2082) layer that grows on the silicon surface during SC-1 and SC-2 cleaning. The DHF dip is not always included in post-CMP cleaning sequences but is used in specific applications:<\/p>\n<ul>\n<li>Before SC-1, as a first step to strip any thick native oxide and liberate metallic contamination trapped at the oxide\/silicon interface<\/li>\n<li>After SC-2, to produce a hydrogen-passivated (hydrophobic) silicon surface that is highly resistant to re-oxidation and metallic contamination adsorption for the brief period before the wafer is further processed<\/li>\n<li>As a pre-epi clean, to ensure the silicon substrate surface is oxide-free immediately before epitaxial silicon deposition<\/li>\n<\/ul>\n<p>The hydrophobic silicon surface produced by DHF is also useful for detecting contamination: particles that land on a hydrophobic surface adhere less strongly than on a hydrophilic (oxidized) surface, and the surface dries more uniformly. However, a hydrophobic surface is more susceptible to hydrocarbon adsorption from the ambient, so exposure time between DHF clean and the next process step must be minimized.<\/p>\n<\/section>\n<hr class=\"jp-hr\">\n\n<section id=\"megasonic\">\n<h2>Megasonic Cleaning and Brush Scrubbing<\/h2>\n<h3>Megasonic Cleaning<\/h3>\n<p>Megasonic transducers operating at 900 kHz\u20131 MHz are immersed in or mounted on the walls of cleaning baths to generate acoustic streaming and controlled micro-cavitation in the cleaning liquid. The resulting fluid motion at the wafer surface generates a boundary-layer shear stress that dislodges adhered particles too small to be removed by chemical mechanisms alone. Megasonic enhancement is particularly valuable for particles &lt;100 nm, which have very high adhesion-to-removal-force ratios due to their large surface-area-to-mass ratio. The combination of megasonic energy with SC-1 chemistry is the most effective approach currently available for achieving LPD counts below 30 at 35 nm on 300mm prime silicon.<\/p>\n<h3>Brush Scrubbing (PVA Brush Clean)<\/h3>\n<p>Polyvinyl alcohol (PVA) sponge brush cleaners use rotating cylindrical brushes (100\u2013300 rpm) that gently contact the wafer surface while ultra-pure DI water is dispensed. The brushes are sufficiently compliant to avoid surface scratching (contact force &lt;0.1 N) while physically sweeping particles from the wafer surface. PVA brush scrubbing is effective for particles &gt;100 nm and complements megasonic cleaning, which is more effective for smaller particles. Brush scrubbing is typically used as the first cleaning step after the polishing tool \u2014 before any chemical bath \u2014 to remove the bulk of slurry particles before the chemical steps refine the surface to specification.<\/p>\n<\/section>\n<hr class=\"jp-hr\">\n\n<section id=\"drying\">\n<h2>Final Rinse and Drying: Preventing Watermarks<\/h2>\n<p>The final rinse uses ultra-pure DI water (resistivity &gt;18.2 M\u03a9\u00b7cm, TOC &lt;1 ppb, particle count &lt;1 particle\/ml at &gt;50 nm) to dilute and flush all chemical residues from the SC-2 step to negligible levels. The rinse must be thorough enough that the last rinse water expelled from the wafer surface has a resistivity approaching that of the incoming DI water \u2014 typically monitored by an inline conductivity sensor in the overflow rinse tank drain.<\/p>\n<p>Drying is where watermarks can be introduced. A water droplet that evaporates on the silicon surface concentrates its dissolved mineral load (silicic acid, trace metals, dissolved gases) into a ring-shaped deposit \u2014 a watermark \u2014 that appears as a cluster of LPDs at the evaporation boundary. Two drying approaches minimize watermarks:<\/p>\n<ul>\n<li><strong>Spin-dry (centrifugal drying):<\/strong> The wafer is spun at 1,000\u20133,000 rpm in a N\u2082 ambient while a small volume of ultra-pure DI water is dispensed near the wafer center. Centrifugal force drives the water film uniformly off the wafer edge faster than it can evaporate from the surface, preventing stationary droplet formation. This is the most common drying method in 300mm post-CMP cleaning tools.<\/li>\n<li><strong>Marangoni (IPA vapor) drying:<\/strong> The wafer is slowly withdrawn from the final DI water rinse through a zone of isopropyl alcohol (IPA) vapor. The surface-tension gradient (IPA has much lower surface tension than water) at the IPA\/water interface drives the water film to retract from the wafer surface cleanly, without leaving droplets. Marangoni drying consistently delivers lower watermark density than spin-dry and is preferred for the most stringent LPD specifications.<\/li>\n<\/ul>\n<p>For defect context on how incomplete cleaning manifests as LPD failures, see: <a href=\"https:\/\/jeez-semicon.com\/es\/blog\/Silicon-Wafer-Surface-Defects-in-CMP-Causes-Detection-Prevention\/\" target=\"_blank\">Silicon Wafer Surface Defects in CMP: Causes, Detection &amp; Prevention<\/a>. For the complete process sequence that post-CMP cleaning follows, see: <a href=\"https:\/\/jeez-semicon.com\/es\/blog\/Silicon-Wafer-Polishing-Process-Step-by-Step-from-Lapping-to-Final-Polish\/\" target=\"_blank\">Silicon Wafer Polishing Process: Step-by-Step from Lapping to Final Polish<\/a>.<\/p>\n<\/section>\n\n<div class=\"jp-related\"><div class=\"jp-related-title\">Related Articles in This Series<\/div><div class=\"jp-related-links\">\n<a href=\"https:\/\/jeez-semicon.com\/es\/blog\/The-Complete-Guide-to-Silicon-Wafer-Polishing\/\" target=\"_blank\" class=\"jp-rl\"><span class=\"jp-rl-icon\">\ud83d\udcd8<\/span><div><strong>The Complete Guide to Silicon Wafer Polishing<\/strong><span>The full silicon wafer CMP pillar guide from JEEZ.<\/span><\/div><\/a>\n<a href=\"https:\/\/jeez-semicon.com\/es\/blog\/Silicon-Wafer-Polishing-Process-Step-by-Step-from-Lapping-to-Final-Polish\/\" target=\"_blank\" class=\"jp-rl\"><span class=\"jp-rl-icon\">\u2699\ufe0f<\/span><div><strong>Silicon Wafer Polishing Process: Step-by-Step from Lapping to Final Polish<\/strong><span>Where post-CMP cleaning fits in the complete silicon wafer polishing process sequence.<\/span><\/div><\/a>\n<a href=\"https:\/\/jeez-semicon.com\/es\/blog\/Silicon-Wafer-Surface-Defects-in-CMP-Causes-Detection-Prevention\/\" target=\"_blank\" class=\"jp-rl\"><span class=\"jp-rl-icon\">\ud83d\udd2c<\/span><div><strong>Silicon Wafer Surface Defects in CMP: Causes, Detection &amp; Prevention<\/strong><span>How incomplete cleaning manifests as LPD, haze, and particle defects in inspection.<\/span><\/div><\/a>\n<a href=\"https:\/\/jeez-semicon.com\/es\/blog\/CMP-Slurry-for-Silicon-Wafer-Types-Selection-Best-Practices\/\" target=\"_blank\" class=\"jp-rl\"><span class=\"jp-rl-icon\">\ud83d\udca7<\/span><div><strong>CMP Slurry for Silicon Wafer: Types, Selection &amp; Best Practices<\/strong><span>How slurry formulation \u2014 organic additives, pH, metal impurities \u2014 affects post-CMP cleanability.<\/span><\/div><\/a>\n<\/div><\/div>\n<hr class=\"jp-hr\">\n<section id=\"faq\">\n<h2>Preguntas frecuentes<\/h2>\n<div class=\"jp-faq\"><div class=\"jp-faq-item\"><div class=\"jp-faq-q\" onclick=\"jeezToggleFaq(this)\">What is the standard post-CMP cleaning sequence for silicon wafers?<span class=\"jp-faq-icon\">+<\/span><\/div><div class=\"jp-faq-a\">The standard post-CMP cleaning sequence for silicon wafer final polish is: (1) PVA brush scrub with DI water to remove bulk slurry particles; (2) SC-1 clean (NH\u2084OH:H\u2082O\u2082:H\u2082O = 1:2:10, 70\u00b0C, 5\u201310 min, optionally with megasonic) for particle and organic removal; (3) cascade DI water rinse; (4) SC-2 clean (HCl:H\u2082O\u2082:H\u2082O = 1:1:5, 75\u00b0C, 5\u201310 min) for metallic contamination; (5) final cascade DI rinse; (6) spin-dry or Marangoni IPA drying. Some processes add a DHF dip between SC-1 and SC-2 for epi-ready applications.<\/div><\/div>\n<div class=\"jp-faq-item\"><div class=\"jp-faq-q\" onclick=\"jeezToggleFaq(this)\">Why is SC-1 cleaning needed after CMP?<span class=\"jp-faq-icon\">+<\/span><\/div><div class=\"jp-faq-a\">SC-1 (NH\u2084OH\/H\u2082O\u2082\/H\u2082O at elevated temperature) removes two critical contamination types after CMP: (1) residual slurry abrasive particles, which are lifted off the surface through mild chemical undercutting (~0.5 nm etch\/min) and electrostatic repulsion created by the alkaline pH; (2) organic slurry additives (surfactants, dispersants) that adsorb onto the polished surface as thin films and would contaminate subsequent thermal processes. Megasonic enhancement of SC-1 is typically required to achieve LPD counts below 30 at 35 nm on 300mm prime wafers.<\/div><\/div>\n<div class=\"jp-faq-item\"><div class=\"jp-faq-q\" onclick=\"jeezToggleFaq(this)\">What metallic contamination does SC-2 remove and why does it matter?<span class=\"jp-faq-icon\">+<\/span><\/div><div class=\"jp-faq-a\">SC-2 (HCl\/H\u2082O\u2082\/H\u2082O) removes alkali metals (K\u207a, Na\u207a) from KOH-based slurry chemistry and transition metals (Fe, Cu, Ni, Cr) from polishing hardware and slurry delivery components. K\u207a and Na\u207a are particularly damaging in gate oxide applications because they diffuse through SiO\u2082 under electrical bias, causing threshold voltage shift and long-term gate oxide reliability degradation. Target metallic contamination after cleaning is below 1\u00d710\u00b9\u2070 atoms\/cm\u00b2 for Fe and Cu, as measured by vapor-phase decomposition ICP-MS.<\/div><\/div>\n<div class=\"jp-faq-item\"><div class=\"jp-faq-q\" onclick=\"jeezToggleFaq(this)\">What causes watermarks on silicon wafers after cleaning?<span class=\"jp-faq-icon\">+<\/span><\/div><div class=\"jp-faq-a\">Watermarks form when a droplet of rinse water evaporates on the silicon surface, concentrating its dissolved mineral load (dissolved silicic acid, trace metals, dissolved CO\u2082) into a ring-shaped deposit at the droplet&#8217;s evaporation boundary. They appear as clusters of LPDs on surface inspection. Prevention strategies include: using ultra-pure DI water with TOC below 1 ppb and resistivity above 18.2 M\u03a9\u00b7cm; spin-dry at high speed in N\u2082 ambient; or Marangoni (IPA vapor) drying, which removes water uniformly without droplet formation and is the most effective watermark prevention method.<\/div><\/div>\n<div class=\"jp-faq-item\"><div class=\"jp-faq-q\" onclick=\"jeezToggleFaq(this)\">How does megasonic cleaning work and when is it necessary?<span class=\"jp-faq-icon\">+<\/span><\/div><div class=\"jp-faq-a\">Megasonic cleaners use piezoelectric transducers at 900 kHz\u20131 MHz to generate acoustic streaming and controlled micro-cavitation in the cleaning liquid. This creates a high shear stress at the wafer surface that physically dislodges particles too small for chemical mechanisms alone to remove. Megasonic cleaning is most effective for particles below 100 nm and is generally necessary for achieving LPD counts below 30 at the 35 nm detection threshold on 300mm prime-grade silicon wafers. It is typically applied during the SC-1 step, combining chemical undercutting with acoustic particle removal for synergistic effectiveness.<\/div><\/div>\n<\/div>\n<\/section>\n<hr class=\"jp-hr\">\n<div class=\"jp-cta\"><h2>Cleaner Wafers Start with Cleaner Slurry<\/h2><p>JEEZ CMP slurries are formulated with low organic additive loading and ultra-low metallic impurity levels (Fe, Cu &lt;1 ppb), reducing the post-CMP contamination burden and making it easier to reach the LPD and metallic cleanliness targets your process requires.<\/p>\n<a href=\"https:\/\/jeez-semicon.com\/es\/contact\/\" target=\"_blank\" class=\"jp-cta-btn\">Contact JEEZ Technical Team<\/a>\n<\/div>\n<\/div>\n<script type=\"application\/ld+json\">{\"@context\":\"https:\/\/schema.org\",\"@type\":\"FAQPage\",\"mainEntity\":[{\"@type\":\"Question\",\"name\":\"What is the standard post-CMP cleaning sequence for silicon wafers?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"The standard post-CMP cleaning sequence for silicon wafer final polish is: (1) PVA brush scrub with DI water to remove bulk slurry particles; (2) SC-1 clean (NH\u2084OH:H\u2082O\u2082:H\u2082O = 1:2:10, 70\u00b0C, 5\u201310 min, optionally with megasonic) for particle and organic removal; (3) cascade DI water rinse; (4) SC-2 clean (HCl:H\u2082O\u2082:H\u2082O = 1:1:5, 75\u00b0C, 5\u201310 min) for metallic contamination; (5) final cascade DI rinse; (6) spin-dry or Marangoni IPA drying. Some processes add a DHF dip between SC-1 and SC-2 for epi-ready applications.\"}},{\"@type\":\"Question\",\"name\":\"Why is SC-1 cleaning needed after CMP?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"SC-1 (NH\u2084OH\/H\u2082O\u2082\/H\u2082O at elevated temperature) removes two critical contamination types after CMP: (1) residual slurry abrasive particles, which are lifted off the surface through mild chemical undercutting (~0.5 nm etch\/min) and electrostatic repulsion created by the alkaline pH; (2) organic slurry additives (surfactants, dispersants) that adsorb onto the polished surface as thin films and would contaminate subsequent thermal processes. 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Target metallic contamination after cleaning is below 1\u00d710\u00b9\u2070 atoms\/cm\u00b2 for Fe and Cu, as measured by vapor-phase decomposition ICP-MS.\"}},{\"@type\":\"Question\",\"name\":\"What causes watermarks on silicon wafers after cleaning?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"Watermarks form when a droplet of rinse water evaporates on the silicon surface, concentrating its dissolved mineral load (dissolved silicic acid, trace metals, dissolved CO\u2082) into a ring-shaped deposit at the droplet's evaporation boundary. They appear as clusters of LPDs on surface inspection. Prevention strategies include: using ultra-pure DI water with TOC below 1 ppb and resistivity above 18.2 M\u03a9\u00b7cm; spin-dry at high speed in N\u2082 ambient; or Marangoni (IPA vapor) drying, which removes water uniformly without droplet formation and is the most effective watermark prevention method.\"}},{\"@type\":\"Question\",\"name\":\"How does megasonic cleaning work and when is it necessary?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"Megasonic cleaners use piezoelectric transducers at 900 kHz\u20131 MHz to generate acoustic streaming and controlled micro-cavitation in the cleaning liquid. This creates a high shear stress at the wafer surface that physically dislodges particles too small for chemical mechanisms alone to remove. Megasonic cleaning is most effective for particles below 100 nm and is generally necessary for achieving LPD counts below 30 at the 35 nm detection threshold on 300mm prime-grade silicon wafers. It is typically applied during the SC-1 step, combining chemical undercutting with acoustic particle removal for synergistic effectiveness.\"}}]}<\/script>\n<script>\nfunction jeezToggleFaq(el){\n  var a=el.nextElementSibling,o=a.classList.contains('jp-open');\n  document.querySelectorAll('.jp-faq-a').forEach(function(x){x.classList.remove('jp-open')});\n  document.querySelectorAll('.jp-faq-q').forEach(function(x){x.classList.remove('jp-open')});\n  if(!o){a.classList.add('jp-open');el.classList.add('jp-open');}\n}\n<\/script>","protected":false},"excerpt":{"rendered":"<p>\u2190 Back to: The Complete Guide to Silicon Wafer Polishing JEEZ Semiconductor Materials &nbsp;\u00b7&nbsp; Technical Guide &nbsp;\u00b7&nbsp; Updated June 2026 A complete technical guide to post-CMP cleaning \u2014 covering contamination  &#8230;<\/p>","protected":false},"author":1,"featured_media":2307,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[9,59],"tags":[],"class_list":["post-2305","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-blog","category-industry"],"acf":[],"_links":{"self":[{"href":"https:\/\/jeez-semicon.com\/es\/wp-json\/wp\/v2\/posts\/2305","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/jeez-semicon.com\/es\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/jeez-semicon.com\/es\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/es\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/es\/wp-json\/wp\/v2\/comments?post=2305"}],"version-history":[{"count":2,"href":"https:\/\/jeez-semicon.com\/es\/wp-json\/wp\/v2\/posts\/2305\/revisions"}],"predecessor-version":[{"id":2308,"href":"https:\/\/jeez-semicon.com\/es\/wp-json\/wp\/v2\/posts\/2305\/revisions\/2308"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/es\/wp-json\/wp\/v2\/media\/2307"}],"wp:attachment":[{"href":"https:\/\/jeez-semicon.com\/es\/wp-json\/wp\/v2\/media?parent=2305"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/jeez-semicon.com\/es\/wp-json\/wp\/v2\/categories?post=2305"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/jeez-semicon.com\/es\/wp-json\/wp\/v2\/tags?post=2305"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}