{"id":2398,"date":"2026-06-24T10:15:33","date_gmt":"2026-06-24T02:15:33","guid":{"rendered":"https:\/\/jeez-semicon.com\/?p=2398"},"modified":"2026-06-24T10:15:33","modified_gmt":"2026-06-24T02:15:33","slug":"sic-wide-bandgap-semiconductor-planarization-cmp-challenges-solutions","status":"publish","type":"post","link":"https:\/\/jeez-semicon.com\/fr\/blog\/sic-wide-bandgap-semiconductor-planarization-cmp-challenges-solutions\/","title":{"rendered":"SiC &amp; Wide Bandgap Semiconductor Planarization: CMP Challenges &amp; Solutions"},"content":{"rendered":"<!-- JEEZ | Cluster 08 | SiC & Wide Bandgap Semiconductor Planarization: CMP Challenges & Solutions -->\n<link rel=\"preconnect\" href=\"https:\/\/fonts.googleapis.com\">\n<link rel=\"preconnect\" href=\"https:\/\/fonts.gstatic.com\" crossorigin>\n<link href=\"https:\/\/fonts.googleapis.com\/css2?family=Syne:wght@600;700;800&#038;family=Inter:ital,wght@0,400;0,500;0,600;1,400&#038;display=swap\" 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h3{font-family:'Syne',sans-serif;color:#fff;font-size:1.4rem;font-weight:800;margin:0 0 10px;position:relative}\n.jeez-pl .jz-cta-box p{color:rgba(255,255,255,.74);max-width:520px;margin:0 auto 26px;font-size:14.5px;position:relative}\n.jeez-pl .jz-btn{display:inline-block;background:var(--jz-teal);color:#fff;font-size:14.5px;font-weight:700;padding:13px 36px;border-radius:8px;text-decoration:none;transition:background .15s,transform .1s}\n.jeez-pl .jz-btn:hover{background:var(--jz-teal-dark);color:#fff;text-decoration:none;transform:translateY(-2px)}\n.jeez-pl .jz-faq-list{margin-top:18px}\n.jeez-pl .jz-faq-item{border:1px solid var(--jz-border);border-radius:var(--jz-radius);margin-bottom:12px;overflow:hidden}\n.jeez-pl .jz-faq-q{background:var(--jz-bg);padding:15px 20px;font-weight:600;font-size:14.5px;color:var(--jz-navy);border-left:4px solid var(--jz-teal);line-height:1.4}\n.jeez-pl .jz-faq-a{padding:14px 20px 16px;font-size:14px;color:var(--jz-text);line-height:1.74;border-top:1px solid var(--jz-border)}\n@media(max-width:680px){.jeez-pl .jz-hero{padding:28px 22px}.jeez-pl .jz-toc ol{columns:1}.jeez-pl .jz-grid-2{grid-template-columns:1fr}.jeez-pl .jz-cta-box{padding:32px 22px}.jeez-pl h2{font-size:1.3rem}}\n<\/style>\n\n<div class=\"jeez-pl\">\n\n<a class=\"jz-back-link\" href=\"https:\/\/jeez-semicon.com\/fr\/blog\/Planarization-in-Semiconductor-Manufacturing-Complete-Guide\/\" target=\"_blank\" rel=\"noopener noreferrer\">\u2190 Back to Complete Planarization Guide<\/a>\n\n<div class=\"jz-hero\">\n  <span class=\"jz-hero-eyebrow\">Wide Bandgap Semiconductors<\/span>\n  <p class=\"jz-hero-lead\">Silicon carbide, gallium nitride, and other wide bandgap semiconductors are the materials enabling the next generation of power electronics \u2014 from electric vehicle inverters to renewable energy converters and industrial motor drives. But these materials&#8217; exceptional physical properties make them among the most challenging substrates to planarize. This guide covers the science of SiC and WBG CMP: why conventional silicon CMP approaches fail, what advanced chemistries are solving the problem, and what the market and technology trends mean for CMP in power semiconductor manufacturing.<\/p>\n  <div class=\"jz-hero-meta\">\n    <span>Updated: <strong>June 2026<\/strong><\/span>\n    <span class=\"jz-pipe\">|<\/span>\n    <span>By <strong>JEEZ Technical Team<\/strong><\/span>\n  <\/div>\n<\/div>\n\n<nav class=\"jz-toc\" aria-label=\"Table des mati\u00e8res\">\n  <span class=\"jz-toc-label\">Table des mati\u00e8res<\/span>\n  <ol>\n    <li><a href=\"#why-wbg\">Why Wide Bandgap Materials Need Different CMP<\/a><\/li>\n    <li><a href=\"#sic-properties\">SiC Material Properties and CMP Challenges<\/a><\/li>\n    <li><a href=\"#si-face-c-face\">Si-Face vs. C-Face: The Polarity Problem<\/a><\/li>\n    <li><a href=\"#conventional-limits\">Why Conventional CMP Fails for SiC<\/a><\/li>\n    <li><a href=\"#fenton\">Fenton Chemistry for SiC CMP<\/a><\/li>\n    <li><a href=\"#kmnO4\">KMnO\u2084-Based and Other Advanced Slurries<\/a><\/li>\n    <li><a href=\"#gan-planarization\">GaN Substrate Planarization<\/a><\/li>\n    <li><a href=\"#diamond-cmp\">Diamond Semiconductor CMP<\/a><\/li>\n    <li><a href=\"#metrology\">SiC CMP Metrology and Quality<\/a><\/li>\n    <li><a href=\"#market\">Market Context and Future Outlook<\/a><\/li>\n    <li><a href=\"#faq\">Questions fr\u00e9quemment pos\u00e9es<\/a><\/li>\n  <\/ol>\n<\/nav>\n\n\n<section id=\"why-wbg\">\n  <h2><span class=\"jz-sn\">01<\/span>Why Wide Bandgap Materials Need Different CMP<\/h2>\n  <p>The material properties that make silicon carbide (SiC), gallium nitride (GaN), and related wide bandgap (WBG) semiconductors superior to silicon for high-voltage, high-temperature power device applications \u2014 extreme hardness, high chemical stability, wide bandgap, high breakdown electric field \u2014 are the same properties that make them extremely difficult to planarize. The materials polished well by alkaline colloidal silica on a standard silicon CMP process tool are soft and chemically reactive. SiC and GaN are neither.<\/p>\n\n  <div class=\"jz-table-wrap\">\n    <table>\n      <thead>\n        <tr><th>Propri\u00e9t\u00e9<\/th><th>Silicium (Si)<\/th><th>Silicon Carbide (4H-SiC)<\/th><th>Nitrure de gallium (GaN)<\/th><th>Diamond<\/th><\/tr>\n      <\/thead>\n      <tbody>\n        <tr><td>Duret\u00e9 Mohs<\/td><td>6.5<\/td><td>9.2\u20139.5<\/td><td>8.5\u20139.0<\/td><td>10 (hardest known)<\/td><\/tr>\n        <tr><td>Bandgap (eV)<\/td><td>1.12<\/td><td>3.26<\/td><td>3.44<\/td><td>5.47<\/td><\/tr>\n        <tr><td>Breakdown Field (MV\/cm)<\/td><td>0.3<\/td><td>3.0<\/td><td>3.3<\/td><td>10<\/td><\/tr>\n        <tr><td>R\u00e9sistance chimique<\/td><td>Moderate (KOH etches)<\/td><td>Tr\u00e8s \u00e9lev\u00e9<\/td><td>Haut<\/td><td>Extreme<\/td><\/tr>\n        <tr><td>Typical CMP MRR (nm\/min)<\/td><td>200\u2013500<\/td><td>10\u2013100<\/td><td>5\u201350<\/td><td>&lt;5<\/td><\/tr>\n        <tr><td>Wafer Size (standard, 2026)<\/td><td>300 mm<\/td><td>150\u2013200 mm<\/td><td>150\u2013200 mm (on Si or SiC)<\/td><td>2\u20134 inch<\/td><\/tr>\n      <\/tbody>\n    <\/table>\n  <\/div>\n\n  <p>The CMP MRR values illustrate the challenge dramatically: SiC is polished at 10\u201350\u00d7 lower rates than silicon under comparable conditions. At commercial SiC wafer polishing throughput requirements (typically 40\u201380 wafers per hour on a production polishing tool), this MRR disparity directly translates to either longer polishing times (reducing throughput) or higher applied pressures (risking subsurface damage and higher defect density).<\/p>\n<\/section>\n\n\n<section id=\"sic-properties\">\n  <h2><span class=\"jz-sn\">02<\/span>SiC Material Properties and CMP Challenges<\/h2>\n\n  <h3>Crystal Structure and Polytypes<\/h3>\n  <p>Silicon carbide exists in over 200 polytypes \u2014 different stacking sequences of the same Si and C atomic layers \u2014 of which 4H-SiC (hexagonal, 4-layer stacking period) and 6H-SiC (hexagonal, 6-layer) are most relevant for power device manufacturing. 4H-SiC is preferred for power MOSFETs and Schottky diodes because of its superior isotropic electron mobility and larger bandgap relative to 6H-SiC. 3C-SiC (cubic) is used for research applications. The polytype-dependent crystal structure influences CMP behavior through differences in surface bond energy, oxidation rate, and cleavage plane orientation.<\/p>\n\n  <h3>Hardness and Its CMP Consequences<\/h3>\n  <p>With a Mohs hardness of 9.2\u20139.5, 4H-SiC is harder than all common CMP abrasive materials except diamond (Mohs 10) and is comparable to aluminum oxide (Mohs 9.0). This means that:<\/p>\n  <ul>\n    <li>Colloidal silica particles (SiO\u2082, Mohs 7) are too soft to mechanically scratch SiC surfaces at useful MRR levels under standard CMP pressures<\/li>\n    <li>Fumed alumina (Al\u2082O\u2083, Mohs 9.0) is marginally harder than SiC but produces high surface scratch densities due to angular particle morphology<\/li>\n    <li>Diamond abrasive provides the highest MRR but introduces subsurface crystal damage that is unacceptable for epitaxial layer growth quality<\/li>\n    <li>The only practical approach is to chemically soften the SiC surface before mechanical abrasion \u2014 the key principle behind all advanced SiC CMP chemistries<\/li>\n  <\/ul>\n\n  <h3>Chemical Stability<\/h3>\n  <p>SiC&#8217;s strong Si\u2013C covalent bonds (bond dissociation energy: 451 kJ\/mol for Si\u2013C vs. 368 kJ\/mol for Si\u2013O) make it resistant to most aqueous chemical etchants at room temperature. Conventional silicon CMP relies on alkaline chemistry (KOH, NH\u2084OH at pH 10\u201312) breaking Si\u2013O\u2013Si bonds on the oxidized silicon surface. This mechanism is largely ineffective on SiC because the native SiO\u2082 that forms on SiC surfaces at room temperature is much thinner (0.5\u20132 nm vs. 1\u20134 nm on Si) and grows more slowly, limiting the rate of chemical surface modification that CMP can exploit.<\/p>\n<\/section>\n\n\n<section id=\"si-face-c-face\">\n  <h2><span class=\"jz-sn\">03<\/span>Si-Face vs. C-Face: The Polarity Problem<\/h2>\n  <p>A 4H-SiC wafer has two distinct surfaces: the silicon-terminated face (Si-face, crystallographic direction [0001]) and the carbon-terminated face (C-face, [000-1]). These two surfaces have fundamentally different physical and chemical properties that complicate SiC CMP in multi-wafer batch processing:<\/p>\n\n  <div class=\"jz-grid-2\">\n    <div class=\"jz-card\">\n      <h4>Si-Face (0001)<\/h4>\n      <p>The Si-face is the primary device fabrication surface for power MOSFETs and Schottky diodes in 4H-SiC. It oxidizes more slowly than the C-face (oxidation rate ratio ~10:1). Surface roughness after standard polishing is lower. Majority of SiC CMP development targets the Si-face. Target Ra for epi-ready wafers: &lt;0.2 nm.<\/p>\n    <\/div>\n    <div class=\"jz-card\">\n      <h4>C-Face (000-1)<\/h4>\n      <p>The C-face oxidizes significantly faster than the Si-face (10\u00d7 higher oxidation rate under comparable conditions). This means that under identical CMP conditions, the C-face polishes substantially faster \u2014 creating a MRR asymmetry problem in any process that exposes both faces simultaneously. C-face surfaces are also more reactive to CMP slurry chemistry, requiring careful pH and oxidizer concentration control to avoid excessive material removal or roughness.<\/p>\n    <\/div>\n  <\/div>\n\n  <p>In single-wafer SiC CMP (which processes only the Si-face at a time), the polarity problem is manageable. In batch-process multi-wafer polishing (which polishes multiple wafers simultaneously in a carrier), wafers with different orientations or with both faces exposed due to carrier design can experience different MRR, leading to thickness non-uniformity within the batch. Production SiC polishing systems must account for this through carrier design, wafer fixturing, and process recipe optimization.<\/p>\n<\/section>\n\n\n<section id=\"conventional-limits\">\n  <h2><span class=\"jz-sn\">04<\/span>Why Conventional Silicon CMP Fails for SiC<\/h2>\n  <p>A conventional silicon CMP process \u2014 colloidal silica at pH 10\u201311, standard polyurethane pad, 2\u20134 psi down-force \u2014 applied directly to a 4H-SiC substrate produces:<\/p>\n  <ul>\n    <li><strong>MRR of 1\u20135 nm\/min:<\/strong> Compared to 200\u2013400 nm\/min for silicon oxide. At a commercial requirement to remove 10\u201320 \u00b5m of SiC material per wafer (to correct saw damage and subsurface crystal damage from wafer slicing), a 5 nm\/min MRR requires 33\u201367 hours of polishing per wafer \u2014 clearly non-viable for any commercial manufacturing operation.<\/li>\n    <li><strong>Surface scratches from hard abrasive particles:<\/strong> At the contact pressures needed to achieve even 5 nm\/min MRR on SiC with silica, the abrasive particles cause surface scratching because the silica particle hardness is below SiC hardness \u2014 the interaction is dominated by shear and gouging rather than the gentle abrasive cutting that produces smooth silicon surfaces.<\/li>\n    <li><strong>Inadequate surface roughness:<\/strong> Ra after conventional silica CMP on SiC is typically 1\u20135 nm \u2014 an order of magnitude higher than the &lt;0.2 nm Ra required for epi-ready SiC substrates for homoepitaxial SiC layer growth for power device fabrication.<\/li>\n  <\/ul>\n\n  <div class=\"jz-callout gold\">\n    <span class=\"jz-callout-tag\">Core Insight<\/span>\n    <p>The CMP paradigm for SiC must reverse the usual silicon approach: instead of relying on mechanical abrasion enhanced by mild chemistry, SiC CMP must rely on <strong>chemistry to rapidly soften\/convert the surface to a more easily abraded compound<\/strong>, with mechanical abrasion as the secondary removal step. This is the key principle behind all successful advanced SiC CMP chemistries.<\/p>\n  <\/div>\n<\/section>\n\n\n<section id=\"fenton\">\n  <h2><span class=\"jz-sn\">05<\/span>Fenton Chemistry for SiC CMP<\/h2>\n  <p>The Fenton reaction \u2014 discovered by H.J.H. Fenton in 1894 \u2014 involves the catalytic decomposition of hydrogen peroxide (H\u2082O\u2082) by ferrous iron (Fe\u00b2\u207a) to generate highly reactive hydroxyl radicals (\u00b7OH):<\/p>\n  <p style=\"text-align:center;font-style:italic;margin:16px 0;font-weight:500\">Fe\u00b2\u207a + H\u2082O\u2082 \u2192 Fe\u00b3\u207a + \u00b7OH + OH\u207b<\/p>\n  <p>Hydroxyl radicals are among the most powerful oxidizing species known (standard reduction potential: +2.80 V vs. SHE), substantially more reactive than H\u2082O\u2082 alone (+1.77 V). When applied to SiC CMP, the \u00b7OH radicals rapidly oxidize the SiC surface, converting it to a thin SiO\u2082 and carbon-oxide surface layer that is substantially softer than bulk SiC and significantly more amenable to mechanical removal by colloidal silica abrasive.<\/p>\n\n  <h3>Fenton CMP Performance for SiC<\/h3>\n  <p>Fenton-reagent CMP slurries for SiC typically consist of:<\/p>\n  <ul>\n    <li>Colloidal silica (20\u201380 nm, 5\u201315 wt%) \u2014 provides mechanical abrasion of the oxidized surface<\/li>\n    <li>H\u2082O\u2082 (0.5\u20135 wt%) \u2014 Fenton oxidant precursor<\/li>\n    <li>FeSO\u2084 or Fe(NO\u2083)\u2083 (0.001\u20130.1 wt% Fe\u00b2\u207a\/Fe\u00b3\u207a) \u2014 Fenton catalyst<\/li>\n    <li>pH 3\u20135 (acidic) \u2014 required for efficient Fe\u00b2\u207a\/Fe\u00b3\u207a cycling and \u00b7OH generation; H\u2082O\u2082 stability is also better at acidic pH<\/li>\n  <\/ul>\n  <p>Compared to conventional alkaline silica CMP on SiC, Fenton chemistry achieves MRR improvements of 3\u20138\u00d7, bringing SiC MRR to 30\u2013100 nm\/min \u2014 still significantly lower than silicon, but commercially viable with appropriate polishing tool and recipe optimization. Critically, post-Fenton CMP surface roughness (Ra 0.1\u20130.3 nm) meets the epi-ready specification for 4H-SiC substrates, enabling direct use of Fenton-polished wafers for SiC epitaxial layer growth without a separate final-polish step.<\/p>\n\n  <h3>Limitations and Challenges of Fenton CMP<\/h3>\n  <ul>\n    <li><strong>Iron contamination:<\/strong> Fe\u00b2\u207a\/Fe\u00b3\u207a ions from the Fenton catalyst can become embedded in the SiC surface or the growing SiO\u2082 surface oxide layer. Residual iron is a deep-level trap in SiC (and in subsequent SiO\u2082 gate dielectric grown on SiC) that degrades minority carrier lifetime and gate oxide reliability. Rigorous post-CMP cleaning (dilute HCl, SC2) and post-cleaning surface iron monitoring by TXRF (total reflection X-ray fluorescence) are mandatory.<\/li>\n    <li><strong>H\u2082O\u2082 stability:<\/strong> The combination of Fe\u00b2\u207a and H\u2082O\u2082 accelerates H\u2082O\u2082 decomposition. Point-of-use mixing and close monitoring of H\u2082O\u2082 concentration are required to maintain consistent MRR throughout the polishing run.<\/li>\n    <li><strong>Equipment compatibility:<\/strong> Acidic pH (3\u20135) with H\u2082O\u2082 and iron salts is corrosive to standard stainless steel CMP tool components. Tool materials of construction (pad platen, slurry delivery lines, carrier head materials) must be selected for compatibility with Fenton chemistry.<\/li>\n  <\/ul>\n<\/section>\n\n\n<section id=\"kmnO4\">\n  <h2><span class=\"jz-sn\">06<\/span>KMnO\u2084-Based and Other Advanced SiC CMP Slurries<\/h2>\n\n  <h3>Potassium Permanganate (KMnO\u2084) Slurries<\/h3>\n  <p>KMnO\u2084 is a strong oxidizer (standard reduction potential +1.51 V vs. SHE) that oxidizes SiC surfaces in a different mechanism from Fenton chemistry: permanganate ions (MnO\u2084\u207b) directly oxidize the SiC surface, forming MnO\u2082 and SiO\u2082 compounds that are more easily abraded by subsequent mechanical polishing. KMnO\u2084-based SiC CMP slurries operate at near-neutral pH (pH 5\u20138), offering better compatibility with standard CMP tool materials and reduced corrosion compared to acidic Fenton chemistry.<\/p>\n  <p>KMnO\u2084 slurry performance on SiC: MRR typically 20\u201360 nm\/min (Si-face), surface roughness Ra 0.2\u20130.5 nm after polishing. The primary limitation is MnO\u2082 particle contamination on the wafer surface \u2014 MnO\u2082 precipitates from reduced permanganate and must be removed by post-CMP SC1 or dilute HNO\u2083 cleaning. Residual Mn is monitored by TXRF for compliance with epi-ready wafer specifications.<\/p>\n\n  <h3>UV-Assisted CMP<\/h3>\n  <p>UV-assisted CMP combines ultraviolet light irradiation of the polishing slurry or the wafer surface with standard CMP processing. UV photons generate oxidizing species (ozone, singlet oxygen, \u00b7OH) from H\u2082O\u2082 or O\u2082 in the slurry, enhancing the SiC surface oxidation rate without metal ion contamination from Fenton or permanganate chemistries. Demonstrated MRR improvements of 2\u20134\u00d7 over standard alkaline silica CMP have been reported, with the advantage of essentially no metal contamination concern. Scale-up to 150 mm and 200 mm production SiC wafer processing is under active development as of June 2026.<\/p>\n\n  <h3>Diamond Abrasive Slurries (Lapping)<\/h3>\n  <p>Diamond abrasive slurries (0.1\u20135 \u00b5m diamond particles in oil or water suspension) are used for the initial coarse lapping of SiC wafers after crystal growth and slicing, removing the bulk of the saw damage. Diamond lapping is too aggressive for final polishing \u2014 the large, hard particles produce subsurface crystal damage that cannot be removed by subsequent CMP without additional material removal. Diamond lapping is therefore followed by increasingly fine CMP steps (from roughing CMP with 1\u20133 \u00b5m Al\u2082O\u2083 slurry through final polishing with Fenton or KMnO\u2084 chemistry) to progressively reduce roughness and sub-surface damage to epi-ready specifications.<\/p>\n<\/section>\n\n\n<section id=\"gan-planarization\">\n  <h2><span class=\"jz-sn\">07<\/span>GaN Substrate and Epitaxial Layer Planarization<\/h2>\n  <p>Gallium nitride (GaN) presents CMP challenges similar to SiC \u2014 high hardness (Mohs 8.5\u20139.0), chemical stability, and strong Ga\u2013N bonds (bond energy: 1.93 eV\/bond) \u2014 combined with additional complexity from the commonly used substrate configurations: GaN-on-silicon (GaN grown epitaxially on 200 mm silicon wafers), GaN-on-SiC, and native GaN substrates from ammonothermal or hydride vapor phase epitaxy (HVPE) growth.<\/p>\n\n  <h3>GaN CMP Applications<\/h3>\n  <ul>\n    <li><strong>Native GaN wafer preparation:<\/strong> Ammonothermal or HVPE-grown GaN boules, when sliced into wafers, require the same multi-step lapping and polishing sequence as SiC to produce epi-ready surfaces. MRR challenges are comparable to SiC, and similar advanced oxidizing chemistries (KMnO\u2084, Fenton, or Cl\u2082-based) are under development.<\/li>\n    <li><strong>GaN-on-Si wafer planarization:<\/strong> In integrated circuit applications (GaN-on-Si for power ICs and RF amplifiers), the GaN epitaxial layer is planarized between process steps in a flow similar to silicon CMOS, using standard silicon-compatible CMP tools. The GaN layer hardness still presents challenges \u2014 slurry chemistries adapted from silicon CMP (alkaline silica with ClO\u207b or periodate additives) provide moderate MRR improvement over bare silica.<\/li>\n    <li><strong>Isolation trench CMP:<\/strong> Mesa isolation and trench filling in GaN device fabrication requires SiO\u2082 ILD planarization steps similar to silicon CMOS, using standard oxide CMP slurries.<\/li>\n  <\/ul>\n<\/section>\n\n\n<section id=\"diamond-cmp\">\n  <h2><span class=\"jz-sn\">08<\/span>Diamond Semiconductor CMP<\/h2>\n  <p>Diamond (Mohs hardness 10, bandgap 5.47 eV) is the ultimate wide bandgap semiconductor \u2014 with theoretical performance superior to both SiC and GaN for extreme environment and ultra-high-voltage applications. Diamond CMP for semiconductor substrate preparation is at a much earlier stage than SiC or GaN CMP, with development confined largely to research fabs and specialized pilot lines.<\/p>\n  <p>Current diamond polishing approaches use: (1) mechanical polishing on a rotating cast iron scaife impregnated with diamond powder \u2014 a purely mechanical process achieving MRR of 1\u201310 nm\/min but producing deep subsurface damage; (2) thermochemical polishing, where a heated transition metal plate (Ni, Fe, Co) reacts with carbon at the diamond surface, converting it to metal carbide that is mechanically removed; and (3) plasma-assisted CMP, where reactive plasma species (O\u2082 plasma or H\u2082 plasma) modify the diamond surface chemistry before mechanical abrasion. All three approaches remain too slow and damage-prone for high-volume commercial wafer processing. Diamond semiconductor CMP remains an open research problem as of June 2026.<\/p>\n<\/section>\n\n\n<section id=\"metrology\">\n  <h2><span class=\"jz-sn\">09<\/span>SiC CMP Metrology and Quality<\/h2>\n  <p>The quality requirements for epi-ready SiC substrates are among the most stringent in semiconductor manufacturing. The specifications ensure that the SiC surface is free of polishing-induced damage, chemical contamination, and morphological features that would propagate into the SiC epitaxial layer grown on top:<\/p>\n\n  <div class=\"jz-table-wrap\">\n    <table>\n      <thead>\n        <tr><th>Param\u00e8tres<\/th><th>Specification (Epi-Ready 4H-SiC)<\/th><th>Measurement Method<\/th><\/tr>\n      <\/thead>\n      <tbody>\n        <tr><td>Surface roughness Ra<\/td><td>&lt;0.2 nm (Si-face)<\/td><td>AFM, 5\u00d75 \u00b5m scan<\/td><\/tr>\n        <tr><td>Surface roughness Rq<\/td><td>&lt;0.3 nm (Si-face)<\/td><td>AFM<\/td><\/tr>\n        <tr><td>TTV (Total Thickness Variation)<\/td><td>&lt;5 \u00b5m (150 mm wafer)<\/td><td>Capacitance or optical mapping<\/td><\/tr>\n        <tr><td>BOW \/ WARP<\/td><td>&lt;15 \u00b5m \/ &lt;25 \u00b5m (150 mm)<\/td><td>Optical flatness metrology<\/td><\/tr>\n        <tr><td>Profondeur des dommages souterrains<\/td><td>&lt;5 nm<\/td><td>Cross-section TEM, X-ray diffraction rocking curve<\/td><\/tr>\n        <tr><td>Metal contamination (Fe, Ni, Cr)<\/td><td>&lt;1\u00d710\u00b9\u2070 atoms\/cm\u00b2<\/td><td>TXRF (total reflection XRF)<\/td><\/tr>\n        <tr><td>Particle density<\/td><td>&lt;0.1 \/cm\u00b2 for particles &gt;0.5 \u00b5m<\/td><td>Laser surface scanning (KLA Surfscan)<\/td><\/tr>\n      <\/tbody>\n    <\/table>\n  <\/div>\n\n  <a class=\"jz-more\" href=\"https:\/\/jeez-semicon.com\/fr\/blog\/Post-CMP-Cleaning-Planarization-Metrology-Ensuring-Surface-Quality\/\" target=\"_blank\" rel=\"noopener noreferrer\">\n    <span>Related: Post-CMP Cleaning &amp; Planarization Metrology \u2014 Ensuring Surface Quality<\/span>\n    <span class=\"jz-more-arrow\">\u2192<\/span>\n  <\/a>\n<\/section>\n\n\n<section id=\"market\">\n  <h2><span class=\"jz-sn\">10<\/span>Market Context and Future Outlook<\/h2>\n  <p>The SiC power device market has expanded dramatically through the early 2020s, driven by the electric vehicle (EV) traction inverter market \u2014 where SiC MOSFETs offer significant efficiency advantages over silicon IGBT-based designs at the 650\u20131700 V operating voltages typical of automotive powertrains. As of June 2026, the global SiC device market exceeds $3 billion annually and is growing at approximately 25\u201330% per year, with EV applications representing ~60% of demand. This growth is driving demand for: larger SiC wafer diameters (the industry transition from 150 mm to 200 mm SiC is ongoing); higher wafer throughput per polishing tool; and tighter epi-ready surface specifications to support next-generation 650 V, 1200 V, and 3300 V SiC device generations.<\/p>\n  <p>The transition from 150 mm to 200 mm SiC wafers creates new CMP challenges: the larger wafer diameter amplifies the uniformity demands on polishing tools, requiring carrier heads, pads, and slurry delivery systems designed for 200 mm operation. The SiC CMP consumable market \u2014 slurries, polishing pads, lapping films \u2014 is therefore one of the fastest-growing segments of the semiconductor CMP consumables industry in 2026.<\/p>\n<\/section>\n\n\n<div class=\"jz-cta-box\">\n  <h3>SiC and WBG CMP Consumables from JEEZ<\/h3>\n  <p>JEEZ specializes in CMP consumables for compound semiconductor and wide bandgap device manufacturing, including SiC substrate polishing applications. Contact us to discuss slurry formulation, pad selection, and process qualification for your SiC CMP module.<\/p>\n  <a class=\"jz-btn\" href=\"https:\/\/jeez-semicon.com\/fr\/contact\/\" target=\"_blank\" rel=\"noopener noreferrer\">Contact JEEZ \u2192<\/a>\n<\/div>\n\n\n<section id=\"faq\">\n  <h2><span class=\"jz-sn\">FAQ<\/span>Questions fr\u00e9quemment pos\u00e9es<\/h2>\n  <div class=\"jz-faq-list\">\n    <div class=\"jz-faq-item\">\n      <div class=\"jz-faq-q\">Why is CMP so much more difficult for SiC than for silicon?<\/div>\n      <div class=\"jz-faq-a\">SiC presents three fundamental challenges compared to silicon: (1) Extreme hardness (Mohs 9.2\u20139.5 vs. 6.5 for Si) means that conventional silica abrasives are too soft to mechanically cut SiC at useful rates; (2) High chemical stability \u2014 the strong Si\u2013C bond (451 kJ\/mol vs. 368 kJ\/mol for Si\u2013O) resists the alkaline chemistry that drives silicon CMP; and (3) Low oxidation rate \u2014 the native SiO\u2082 that forms on SiC surfaces is thin and grows slowly, limiting how fast the chemical step in CMP can operate. Together, these properties reduce CMP MRR on SiC to 10\u201350\u00d7 lower than silicon oxide CMP, requiring advanced oxidizing chemistries (Fenton, KMnO\u2084) to achieve commercially viable throughput.<\/div>\n    <\/div>\n    <div class=\"jz-faq-item\">\n      <div class=\"jz-faq-q\">What is Fenton chemistry and why is it used for SiC CMP?<\/div>\n      <div class=\"jz-faq-a\">Fenton chemistry uses the reaction of hydrogen peroxide (H\u2082O\u2082) with ferrous iron (Fe\u00b2\u207a) to generate highly reactive hydroxyl radicals (\u00b7OH). These radicals have a standard reduction potential of +2.80 V \u2014 far higher than H\u2082O\u2082 alone (+1.77 V) \u2014 enabling them to rapidly oxidize the SiC surface to a softer SiO\u2082\/carbon-oxide layer that colloidal silica particles can then mechanically remove. Fenton CMP achieves 3\u20138\u00d7 higher MRR on SiC compared to conventional alkaline silica CMP, while producing surface roughness Ra below 0.2 nm \u2014 meeting epi-ready specifications for SiC wafers used in power device fabrication.<\/div>\n    <\/div>\n    <div class=\"jz-faq-item\">\n      <div class=\"jz-faq-q\">What surface roughness is required for an epi-ready SiC wafer?<\/div>\n      <div class=\"jz-faq-a\">An epi-ready 4H-SiC substrate must have Ra below 0.2 nm (Si-face) and Rq below 0.3 nm, as measured by AFM over a 5\u00d75 \u00b5m scan area. These specifications ensure that the SiC homoepitaxial layer grown on the substrate will replicate the substrate surface quality without amplifying surface roughness into device-critical epi-layer defects (stacking faults, morphological steps). Additional specifications include subsurface damage depth below 5 nm and metal contamination below 1\u00d710\u00b9\u2070 atoms\/cm\u00b2 for transition metals (Fe, Ni, Cr) that create deep traps in SiC.<\/div>\n    <\/div>\n    <div class=\"jz-faq-item\">\n      <div class=\"jz-faq-q\">What is the difference between SiC CMP and silicon CMP?<\/div>\n      <div class=\"jz-faq-a\">The fundamental difference is in the relative roles of chemistry and mechanical abrasion. Silicon CMP uses alkaline chemistry (pH 10\u201311) to break Si\u2013O bonds on an oxidized silicon surface, with mechanical abrasion from soft colloidal silica particles providing efficient removal of the chemically softened material. SiC CMP cannot rely on this mechanism because SiC&#8217;s chemical stability resists alkaline etching and its hardness exceeds that of standard abrasives. Instead, SiC CMP requires aggressive oxidizing agents (Fenton \u00b7OH radicals, KMnO\u2084) to chemically convert the hard SiC surface to a softer oxide layer, which is then removed by mechanical abrasion. This chemistry-first approach is the defining feature of all advanced SiC CMP processes.<\/div>\n    <\/div>\n  <\/div>\n<\/section>\n\n<\/div>\n\n<script type=\"application\/ld+json\">\n{\n  \"@context\": \"https:\/\/schema.org\",\n  \"@type\": \"FAQPage\",\n  \"mainEntity\": [\n    {\"@type\":\"Question\",\"name\":\"Why is CMP so much more difficult for SiC than for silicon?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"SiC's Mohs hardness of 9.2\u20139.5 makes conventional silica abrasives too soft for mechanical cutting; its chemical stability resists alkaline chemistry; and its low oxidation rate limits the chemical step speed. Together these reduce SiC CMP MRR to 10\u201350\u00d7 lower than silicon, requiring advanced oxidizing chemistries (Fenton, KMnO4) for commercially viable throughput.\"}},\n    {\"@type\":\"Question\",\"name\":\"What is Fenton chemistry and why is it used for SiC CMP?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"Fenton chemistry uses Fe2+ + H2O2 to generate highly reactive hydroxyl radicals (\u00b7OH, +2.80 V oxidation potential), which rapidly oxidize the SiC surface to a softer SiO2 layer removable by colloidal silica abrasive. Fenton CMP achieves 3\u20138\u00d7 higher MRR than conventional alkaline silica CMP on SiC, with Ra below 0.2 nm meeting epi-ready specifications.\"}},\n    {\"@type\":\"Question\",\"name\":\"What surface roughness is required for an epi-ready SiC wafer?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"Epi-ready 4H-SiC requires Ra <0.2 nm (Si-face) and Rq <0.3 nm by AFM (5\u00d75 \u00b5m). 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