CMP in Advanced Nodes: Challenges at 7 nm and Beyond

Why CMP Becomes Harder at Every Node

The relentless progression of Moore’s Law scaling — halving transistor dimensions roughly every two years — does not merely require CMP to polish smaller features. It fundamentally changes the nature of what CMP must accomplish, the materials it must process, and the performance specifications it must meet. Each new process node generation introduces new challenges that cannot be solved simply by scaling the existing process linearly.

Three independent scaling trends converge to make advanced-node CMP progressively more demanding: dimensional scaling (narrower lines require tighter dishing and uniformity specs), material innovation (new metals and dielectrics with new CMP requirements replace familiar, well-characterized materials), and structural complexity (3D transistor architectures and multi-chip integration schemes introduce entirely new CMP applications with no historical precedent).

Ultra-Low-k Dielectric CMP

One of the most technically demanding challenges in advanced-node CMP is the polishing of ultra-low-k (ULK) dielectric materials. As copper interconnects scale to finer pitches, the capacitive coupling between adjacent lines increases, slowing signal propagation and increasing power consumption. Reducing the dielectric constant (k) of the insulating material between copper lines lowers this capacitance — but every method of reducing k (introducing porosity into the SiO₂ matrix, substituting carbon for oxygen in the backbone, or using aromatic organic polymer dielectrics) also reduces the material’s mechanical strength, thermal conductivity, and chemical resistance.

Mechanical Fragility: The Core Challenge

A fully dense SiO₂ TEOS oxide has a Young’s modulus of ~70 GPa and a hardness of ~9 GPa. A porous carbon-doped oxide ULK film with k = 2.2 may have a Young’s modulus of only 5–8 GPa and a hardness below 1 GPa — roughly 10× weaker. Under the compressive and shear stresses of CMP polishing, this mechanical weakness manifests as:

• Cohesive failure (cracking): The film fractures internally when localized stress from abrasive particle contact exceeds the film’s cohesive strength. Visible as radial or circular cracks in the ULK layer that propagate to neighboring structures.
• Adhesive failure (delamination): The interface between the ULK film and its underlying liner (SiCN, SiC) or etch stop layer separates under tangential polishing stress. Delaminated areas are often not visible until metallization of the next level reveals the failed interface as a void defect.
• Densification: Mechanical compression from polishing forces can locally densify (collapse the pores of) the ULK film, increasing its local dielectric constant and creating spatial variation in the electrical properties of the insulator.

Process Solutions for ULK CMP

• Ultra-low downforce protocols: <1 psi for k <2.5; <0.5 psi for k <2.2. Requires tools with precisely calibrated low-pressure pneumatic systems.
• Soft CMP pads with large contact area — distribute force over larger effective contact area per unit pad area.
• Low-abrasive-concentration slurry with soft colloidal silica abrasives (avoid alumina or large-particle ceria).
• Aqueous amine-based slurry chemistry (avoid strong acids that hydrolyze the SiO₂ backbone of CDO films).
• Pre-CMP UV curing or annealing to maximize ULK film density and interface adhesion before polishing.

Cobalt and Ruthenium: New Liner and Conductor CMP

From the 28 nm node down to 10 nm, the standard BEOL barrier/liner stack was TaN (diffusion barrier) + Ta (adhesion layer). Starting at 7 nm, cobalt (Co) replaced Ta as the liner material and subsequently as the tungsten contact plug fill material. At 5 nm and below, ruthenium (Ru) is emerging as both a liner and, in some architectures, as the bulk conductor at the lowest metal levels (M0–M1) where line widths approach 5–8 nm and copper’s grain boundary scattering raises its effective resistivity above Ru’s.

Why Co and Ru Need New Slurry Chemistry

Cobalt and ruthenium have electrochemical properties quite different from tantalum and copper, requiring dedicated slurry formulations:

• Cobalt is susceptible to galvanic corrosion in the presence of copper under acidic, oxidizing conditions — the standard Cu CMP slurry environment. Without Co-specific corrosion inhibitors, the Co liner is preferentially dissolved at the Cu-Co interface, creating void defects at via bottoms.
• Ruthenium forms volatile oxide species (RuO₄) under strongly oxidizing conditions at elevated temperatures — a known gas-phase contamination hazard that limits the use of high-H₂O₂ concentrations in Ru CMP slurries.
• Both metals require pH and oxidizer conditions that balance reasonable removal rate against corrosion inhibition — a narrower process window than the well-characterized Cu/Ta chemistry.

JEEZ is actively developing Co/Ru-compatible barrier CMP slurry formulations for customers working at 5 nm and below. Contact our applications engineering team to discuss your specific requirements: jeez-semicon.com/contact.

Gate-All-Around (GAA) Nanosheet CMP

Gate-All-Around (GAA) nanosheet transistors — in high-volume manufacturing at TSMC’s N2 and Samsung’s SF3 as of 2026 — require CMP at critical FEOL steps that did not exist in the FinFET process generation. The GAA nanosheet stack (alternating Si and SiGe layers, each 4–8 nm thick, grown by epitaxy on the silicon substrate) must be planarized after initial shallow trench formation and gate oxide deposition with sub-nanometer uniformity — because any CMP-induced height variation across the nanosheet stack will change the number of nanosheets exposed above the STI isolation level from die to die, directly varying the transistor’s effective channel width and drive current.

Nanosheet-Specific CMP Requirements

• Extreme selectivity: Gate CMP at the GAA node must stop on the Si nanosheet channel without consuming any of the 4–8 nm thick Si layer. Selectivity requirements of 300:1 to 500:1 between the target dielectric and the Si channel are not uncommon.
• Atomic-level planarity: CMP-induced height variation of even 1–2 nm across a nanosheet array is significant when the total channel height is only 20–30 nm (3–5 nanosheets × 6 nm each). This requires endpoint detection with <0.5 nm precision.
• Low defect density at FEOL: A scratch or particle-induced defect at the GAA FEOL CMP stage occurs before gate oxide and work function metal deposition — defects introduced here cannot be corrected and cause gate oxide integrity failures in every transistor they affect.

EUV Integration and Post-CMP Surface Cleanliness

Extreme Ultraviolet Lithography (EUV) at 13.5 nm wavelength has been in high-volume manufacturing for logic chips since the 7 nm generation and is now used for multiple critical layers at 3 nm and 2 nm. EUV imposes the most stringent post-CMP surface cleanliness requirements of any patterning technology, because EUV photons interact with any material on the wafer surface — particles, residues, and topographic features all create local exposure variations that translate directly into CD errors and overlay failures in the patterned layer.

For CMP steps that are immediately upstream of an EUV lithography layer, post-CMP wafer cleanliness specifications typically require: particle count <0.05 particles/cm² at ≥20 nm size; surface roughness Ra <0.15 nm; zero residual organic film detectable by XPS; and metal contamination <5 × 10⁹ atoms/cm². Achieving these specifications requires the combination of optimized megasonic cleaning, Marangoni IPA drying, and — critically — slurry formulations that minimize particle agglomeration in the delivery system to prevent scratch generation that would persist through the post-CMP clean.

3D-IC and Through-Silicon Via (TSV) CMP

The semiconductor industry’s response to slowing transistor scaling has been aggressive adoption of 3D integration — stacking multiple chips vertically and connecting them through Through-Silicon Vias (TSVs). TSVs are copper-filled via structures that penetrate entirely through the silicon wafer substrate, enabling high-bandwidth vertical data transfer between stacked chips. CMP is required at two points in the TSV process flow: after copper TSV plating (to remove overburden from the front side, identical to standard Cu Damascene CMP) and after backside wafer thinning (to reveal and planarize the TSV tips on the wafer backside).

TSV reveal CMP on the wafer backside is a particularly challenging application because it combines wafer thinning (removing 100–700 µm of silicon from the wafer backside) with simultaneous planarization and TSV tip reveal. The wafer must be thinned uniformly to within ±1 µm across 300 mm while revealing thousands to millions of TSV tips to a consistent protrusion height (typically 2–5 µm above the silicon backside surface). This requires dedicated back-grinding followed by CMP using silicon-compatible slurry, followed by dry polishing for final surface finish.

HBM and Advanced Packaging CMP

High Bandwidth Memory (HBM) stacks — used in AI accelerators, HPC chips, and advanced networking ASICs — combine multiple DRAM dies vertically using TSV interconnects and micro-bumps. The HBM manufacturing process requires multiple CMP steps for TSV formation, die bonding surface preparation, and interposer fabrication. As HBM generations have advanced from HBM (2013) to HBM3E (2024) to HBM4 (in development in 2026), the TSV density and interconnect pitch have increased dramatically, placing tighter requirements on CMP uniformity and surface quality at each successive generation.

Beyond HBM, advanced packaging platforms such as Intel’s EMIB, TSMC’s CoWoS, and Samsung’s I-Cube use silicon interposers with dense copper redistribution layers (RDL) that require oxide and metal CMP comparable to front-end BEOL processing. As chiplet architectures proliferate across AI, automotive, and consumer electronics applications in 2026, advanced packaging CMP is one of the fastest-growing application segments for CMP consumable demand.

Advanced Node Metrology Demands

Meeting the CMP performance specifications at 3 nm and 2 nm requires metrology capabilities that were research-grade instruments a decade ago. Within-wafer uniformity specs of ±1% require thickness maps with 0.1 nm precision at hundreds of measurement sites per wafer. Dishing specs of <2 nm require AFM measurement on test structures at multiple die positions. Metal contamination specs of <5 × 10⁹ atoms/cm² require TXRF (Total Reflection X-ray Fluorescence) with detection limits at the 10⁸ atoms/cm² level.

For a full discussion of CMP metrology techniques and how they are integrated into advanced node process control strategies, see our dedicated guide: CMP Metrology and Process Control: Yield Optimization.

Node-by-Node CMP Challenge Summary

よくある質問