{"id":1664,"date":"2026-03-13T09:16:44","date_gmt":"2026-03-13T01:16:44","guid":{"rendered":"https:\/\/jeez-semicon.com\/?p=1664"},"modified":"2026-03-13T09:53:47","modified_gmt":"2026-03-13T01:53:47","slug":"polishing-templates-for-glass-wafers-ceramic-substrates-key-considerations","status":"publish","type":"post","link":"https:\/\/jeez-semicon.com\/ja\/blog\/polishing-templates-for-glass-wafers-ceramic-substrates-key-considerations\/","title":{"rendered":"\u30ac\u30e9\u30b9\u30a6\u30a7\u30fc\u30cf\u3068\u30bb\u30e9\u30df\u30c3\u30af\u57fa\u677f\u306e\u7814\u78e8\u30c6\u30f3\u30d7\u30ec\u30fc\u30c8\uff1a\u4e3b\u306a\u691c\u8a0e\u4e8b\u9805"},"content":{"rendered":"<!DOCTYPE html>\n<html lang=\"en\">\n<head>\n<meta charset=\"UTF-8\" \/>\n<meta name=\"viewport\" content=\"width=device-width, initial-scale=1.0\" \/>\n\n<meta name=\"description\" content=\"Engineering guide to polishing templates for glass wafers and ceramic substrates. Covers borosilicate, fused silica, alumina, AlN, and LTCC polishing \u2014 including non-standard thickness handling, pH compatibility, backing pad selection, and EER design.\" \/>\n<meta name=\"keywords\" content=\"glass wafer polishing template, ceramic substrate polishing template, fused silica polishing template, borosilicate glass polishing fixture, alumina polishing template, AlN substrate polishing, LTCC polishing template, glass substrate polishing fixture, ceramic wafer polishing\" \/>\n<link rel=\"canonical\" href=\"https:\/\/jeez-semicon.com\/blog\/Polishing-Templates-for-Glass-Wafers-Ceramic-Substrates-Key-Considerations\" \/>\n\n<meta property=\"og:title\" content=\"Polishing Templates for Glass Wafers &#038; Ceramic Substrates: Key Considerations\" \/>\n<meta property=\"og:description\" content=\"Template engineering for glass wafers and ceramic substrates: non-standard thickness, borosilicate vs fused silica slurry compatibility, alumina and AlN hardness challenges, LTCC polishing, and custom work-hole depth specification.\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:url\" content=\"https:\/\/jeez-semicon.com\/blog\/Polishing-Templates-for-Glass-Wafers-Ceramic-Substrates-Key-Considerations\" \/>\n\n<script type=\"application\/ld+json\">\n{\n  \"@context\": \"https:\/\/schema.org\",\n  \"@graph\": [\n    {\n      \"@type\": \"Article\",\n      \"headline\": \"Polishing Templates for Glass Wafers & Ceramic Substrates: Key Considerations\",\n      \"description\": \"Engineering guide to polishing template design for glass wafers and ceramic substrates, covering borosilicate, fused silica, alumina, AlN, and LTCC substrates with non-standard thickness handling, slurry compatibility, and EER design.\",\n      \"author\": { \"@type\": \"Organization\", \"name\": \"Jizhi Electronic Technology Co., Ltd.\", \"url\": \"https:\/\/jeez-semicon.com\" },\n      \"publisher\": { \"@type\": \"Organization\", \"name\": \"Jizhi Electronic Technology Co., Ltd.\", \"url\": \"https:\/\/jeez-semicon.com\" },\n      \"mainEntityOfPage\": { \"@type\": \"WebPage\", \"@id\": \"https:\/\/jeez-semicon.com\/blog\/Polishing-Templates-for-Glass-Wafers-Ceramic-Substrates-Key-Considerations\" }\n    },\n    {\n      \"@type\": \"FAQPage\",\n      \"mainEntity\": [\n        {\n          \"@type\": \"Question\",\n          \"name\": \"What makes polishing templates for glass wafers different from semiconductor wafer templates?\",\n          \"acceptedAnswer\": {\n            \"@type\": \"Answer\",\n            \"text\": \"Glass wafers differ from semiconductor wafers in three key ways that affect template design: non-standard thicknesses (0.3\u20132.0 mm versus the 0.5\u20130.8 mm typical for Si), wider incoming thickness variation (\u00b125\u201350 \u00b5m for glass vs \u00b15\u201310 \u00b5m for Si prime wafers), and a much wider range of chemical compositions with different polishing chemistry requirements. The most consequential difference for templates is non-standard thickness \u2014 every glass wafer polishing template requires custom work-hole depth calculation based on the specific incoming thickness, target final thickness, and expected backing pad compression, rather than using a standard depth from a catalog.\"\n          }\n        },\n        {\n          \"@type\": \"Question\",\n          \"name\": \"Can standard FR-4 polishing templates be used for glass wafer polishing?\",\n          \"acceptedAnswer\": {\n            \"@type\": \"Answer\",\n            \"text\": \"FR-4 is acceptable for borosilicate glass polishing using alkaline colloidal silica slurry (pH 9\u201312) where no HF-containing chemistry is used. However, fused silica polishing often uses mildly acidic slurries (pH 4\u20137) where FR-4 provides marginal service life. Any glass polishing process using HF, NH\u2084F, or fluoride-containing chemistry requires CXT-grade templates \u2014 HF attacks both FR-4 and G-10 rapidly and completely, dissolving the epoxy matrix within a few cycles. For production applications at any pH below 8, G-10 minimum is recommended even without fluoride chemistry.\"\n          }\n        },\n        {\n          \"@type\": \"Question\",\n          \"name\": \"What polishing template is used for alumina (Al\u2082O\u2083) ceramic substrates?\",\n          \"acceptedAnswer\": {\n            \"@type\": \"Answer\",\n            \"text\": \"Alumina ceramic substrate polishing typically uses diamond abrasive slurry at pH 4\u20138, which requires G-10 or CXT-grade carrier plate material. Alumina's hardness (Mohs 9.0, same as sapphire) demands harder backing pads (Shore A 65\u201380) and higher process pressures (3\u20136 psi) than silicon polishing. The irregular non-circular geometries common in ceramic substrate applications (rectangles, squares, custom shapes) require custom work-hole geometry machined to the specific substrate shape rather than a circular work-hole, which is a standard capability for custom polishing templates.\"\n          }\n        },\n        {\n          \"@type\": \"Question\",\n          \"name\": \"How is work-hole depth specified for glass wafers with non-standard thickness?\",\n          \"acceptedAnswer\": {\n            \"@type\": \"Answer\",\n            \"text\": \"Work-hole depth for glass wafers is calculated as: target final thickness + backing pad compression offset + template face recession (if applicable) - process-specific overpolish allowance. Because glass wafers have wider incoming thickness variation than semiconductor wafers, the work-hole depth must be calculated based on the nominal incoming thickness for the specific glass lot, and the polishing process recipe adjusted for each lot to account for lot-to-lot thickness variation. Providing your glass supplier's incoming thickness specification (nominal + tolerance) when ordering templates allows the work-hole depth to be correctly calculated for your process.\"\n          }\n        }\n      ]\n    }\n  ]\n}\n<\/script>\n\n<style>\n  @import url('https:\/\/fonts.googleapis.com\/css2?family=DM+Serif+Display:ital@0;1&family=DM+Sans:opsz,wght@9..40,300;9..40,400;9..40,500;9..40,600&family=JetBrains+Mono:wght@400;500&display=swap');\n\n  :root {\n    --navy:      #0a1628;\n    --navy-mid:  #112240;\n    --blue:      #1a56db;\n    --blue-lite: #3b82f6;\n    --cyan:      #06b6d4;\n    --slate:     #334155;\n    --muted:     #64748b;\n    --border:    #e2e8f0;\n    --bg:        #f8fafc;\n    --white:     #ffffff;\n    --accent:    #f59e0b;\n    --green:     #10b981;\n    --teal:      #0f766e;\n    --red:       #ef4444;\n    --glass:     #0369a1;   \/* sky blue for glass *\/\n    --ceramic:   #b45309;   \/* amber-brown for ceramic *\/\n    --fused:     #4f46e5;   \/* indigo for fused silica *\/\n    --radius:    10px;\n    --shadow:    0 4px 24px rgba(10,22,40,.08);\n    --shadow-lg: 0 12px 48px rgba(10,22,40,.14);\n  }\n\n  *, *::before, *::after { box-sizing: border-box; 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gap: 8px; background: var(--bg); border: 1px solid var(--border); color: var(--slate); text-decoration: none; font-size: 13.5px; font-weight: 500; padding: 10px 18px; border-radius: 8px; margin: 40px 0 0; transition: border-color .2s, color .2s; }\n  .back-to-pillar::before { content: '\u2190'; color: var(--blue); }\n  .back-to-pillar:hover { border-color: var(--blue); color: var(--blue); }\n<\/style>\n<\/head>\n<body>\n\n<div class=\"hero\">\n  <div class=\"hero-eyebrow\">Glass &amp; Ceramic Substrates<\/div>\n  <p class=\"hero-sub\">Glass and ceramic substrates span the widest thickness range, the most varied chemistries, and the most diverse geometries of any substrate category. Getting the polishing template right requires understanding exactly which material you are polishing \u2014 and why a single &#8220;glass template&#8221; specification cannot serve all applications.<\/p>\n  <p class=\"hero-meta\">\n    <span>Jizhi Electronic Technology Co, Ltd.\u306b\u3088\u308b\u3002.<\/span>\n    <span>\u00b7<\/span>\n    <span>\u534a\u5c0e\u4f53\u7814\u78e8\u306e\u30b9\u30da\u30b7\u30e3\u30ea\u30b9\u30c8<\/span>\n    <span>\u00b7<\/span>\n    <span>13 min read<\/span>\n  <\/p>\n<\/div>\n\n<div class=\"page-wrap\">\n\n  <nav class=\"breadcrumb\">\n    <a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/Polishing-Templates-for-Semiconductor-Silicon-Wafer-Processing\/\" target=\"_blank\">\u2190 Polishing Templates: Complete Guide<\/a>\n    <span>\/<\/span>\n    Glass &amp; Ceramic Polishing Templates\n  <\/nav>\n\n  <nav class=\"toc-box\">\n    <h2>\u76ee\u6b21<\/h2>\n    <ol class=\"toc-list\">\n      <li><a href=\"#why-different\">Glass &amp; Ceramic: The Widest Template Variable Range<\/a><\/li>\n      <li><a href=\"#thickness-challenge\">The Non-Standard Thickness Challenge<\/a><\/li>\n      <li><a href=\"#work-hole-formula\">Work-Hole Depth Formula for Glass Substrates<\/a><\/li>\n      <li><a href=\"#borosilicate\">Borosilicate Glass Wafers<\/a><\/li>\n      <li><a href=\"#fused-silica\">Fused Silica Wafers<\/a><\/li>\n      <li><a href=\"#alumina\">Alumina (Al\u2082O\u2083) Ceramic Substrates<\/a><\/li>\n      <li><a href=\"#aln\">Aluminum Nitride (AlN) Substrates<\/a><\/li>\n      <li><a href=\"#ltcc\">LTCC &amp; Thick-Film Ceramic Substrates<\/a><\/li>\n      <li><a href=\"#non-circular\">Non-Circular &amp; Custom-Shape Substrates<\/a><\/li>\n      <li><a href=\"#slurry-table\">Slurry Chemistry &amp; Template Material Selection Table<\/a><\/li>\n      <li><a href=\"#comparison\">Full Specification Comparison<\/a><\/li>\n      <li><a href=\"#faq\">\u3088\u304f\u3042\u308b\u8cea\u554f<\/a><\/li>\n    <\/ol>\n  <\/nav>\n\n  <!-- \u2550\u2550\u2550 SECTION 1 \u2550\u2550\u2550 -->\n  <h2 id=\"why-different\">Glass &amp; Ceramic: The Widest Template Variable Range<\/h2>\n\n  <p>Every substrate category discussed in this series \u2014 silicon, SiC, GaAs, InP, sapphire \u2014 involves at least one sharply defined polishing challenge. Silicon templates need tight TTV control. SiC needs chemical resistance. GaAs and InP need fracture protection. In each case, a clear primary engineering requirement drives the template specification.<\/p>\n\n  <p>Glass and ceramic substrates do not have a single primary challenge. They have the most diverse range of physical properties, chemical compositions, and geometric forms of any substrate category, and the relevant template parameters shift significantly from one material to the next. Borosilicate glass polishes at nearly the same conditions as silicon. Fused silica requires acidic slurry and chemical-resistant carrier plates. Alumina ceramic is nearly as hard as sapphire. AlN has unusual thermal sensitivity. LTCC is a composite material with different polishing dynamics entirely. And ceramic substrates frequently come in non-circular shapes that require custom work-hole geometry rather than the standard circular pocket used for wafers.<\/p>\n\n  <p>The unifying theme \u2014 and the reason this entire category merits dedicated treatment \u2014 is that glass and ceramic substrates almost always arrive with non-standard thicknesses and dimensional specifications that differ from semiconductor wafer standards, making custom work-hole depth calculation unavoidable. Understanding <a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/How-to-Specify-a-Polishing-Template-6-Parameters-Engineers-Must-Define\/\" target=\"_blank\" class=\"text-link-pill\">the 6-parameter specification process<\/a> is especially important for glass and ceramic applications precisely because every order is effectively custom.<\/p>\n\n  <hr class=\"divider\" \/>\n\n  <!-- \u2550\u2550\u2550 SECTION 2 \u2550\u2550\u2550 -->\n  <h2 id=\"thickness-challenge\">The Non-Standard Thickness Challenge<\/h2>\n\n  <p>Semiconductor silicon wafers are produced to tightly standardized thicknesses defined by SEMI standards: 725 \u00b5m for 200 mm wafers, 775 \u00b5m for 300 mm wafers, with incoming thickness tolerance of \u00b125 \u00b5m for prime wafers. These standards make it possible to design template work-hole depths from a catalog, with minor adjustments for the specific carrier head and polishing conditions.<\/p>\n\n  <p>Glass wafers are not produced to these standards. They come from a different supply chain \u2014 glass manufacturers working to optical or MEMS specifications rather than SEMI standards \u2014 with thicknesses ranging from 0.3 mm to 2.0 mm and incoming tolerances of \u00b125 \u00b5m to \u00b1100 \u00b5m depending on the glass type and manufacturer. Ceramic substrates are even more variable: green-state sintered ceramics arrive with post-sinter thickness variation of \u00b150\u2013150 \u00b5m that must be accounted for in the template design.<\/p>\n\n  <p>The consequence is that every glass and ceramic polishing template is effectively a custom order. There is no standard work-hole depth that works for &#8220;glass wafers&#8221; \u2014 the depth must be calculated specifically for the combination of incoming substrate thickness, target final thickness, backing pad compression, and process conditions for that specific application. This is not a complexity to be managed around; it is a fundamental characteristic of the category that requires providing accurate substrate dimensional data when ordering templates.<\/p>\n\n  <div class=\"callout warning\">\n    <span class=\"callout-icon\">\u26a0\ufe0f<\/span>\n    <div class=\"callout-body\">\n      <strong>Always Provide Incoming Thickness Specification When Ordering<\/strong>\n      For glass and ceramic polishing templates, the single most important piece of information to provide at time of order is the incoming substrate thickness: nominal value, tolerance, and measurement method (total thickness variation or single-point). Without this data, the work-hole depth cannot be correctly specified. A work-hole depth error of 20 \u00b5m in a glass template \u2014 easily caused by using the wrong nominal thickness \u2014 produces systematic TTV errors across the full wafer area that cannot be corrected by recipe adjustment alone.\n    <\/div>\n  <\/div>\n\n  <hr class=\"divider\" \/>\n\n  <!-- \u2550\u2550\u2550 SECTION 3 \u2550\u2550\u2550 -->\n  <h2 id=\"work-hole-formula\">Work-Hole Depth Formula for Glass &amp; Ceramic Substrates<\/h2>\n\n  <p>The work-hole depth calculation for glass and ceramic substrates follows the same fundamental relationship as all polishing templates, but the larger thickness variability of these substrates makes each term in the formula more consequential \u2014 and getting the calculation wrong has a larger impact than it would for standardized silicon wafers.<\/p>\n\n  <div class=\"thickness-diagram\">\n    <div class=\"td-title\">Work-Hole Depth Calculation \u2014 Glass &amp; Ceramic<\/div>\n    <div class=\"td-formula\">\n      <span class=\"term term-depth\">Work-Hole Depth<\/span>\n      <span class=\"td-eq\">=<\/span>\n      <span class=\"term term-final\">Target Final Thickness<\/span>\n      <span class=\"td-eq\">+<\/span>\n      <span class=\"term term-comp\">Pad Compression Offset<\/span>\n      <span class=\"td-eq\">\u2212<\/span>\n      <span class=\"term term-over\">Overpolish Allowance<\/span>\n    <\/div>\n    <div class=\"td-note\">\n      Pad compression offset: measure backing pad thickness loss at process pressure after 10-minute soak \u2014 typically 5\u201320 \u00b5m for medium-hard pads at 3\u20135 psi.<br>\n      Overpolish allowance: amount of material removed past target thickness to reach surface quality spec \u2014 typically 0\u20135 \u00b5m for glass final polish.\n    <\/div>\n  <\/div>\n\n  <h3>Practical Calculation Example<\/h3>\n  <p>Consider a 150 mm borosilicate glass wafer with incoming nominal thickness 700 \u00b5m (tolerance \u00b150 \u00b5m), target final thickness 500 \u00b5m, backing pad compression of 12 \u00b5m at 3 psi, and overpolish allowance of 3 \u00b5m for surface finish:<\/p>\n\n  <p><strong>Work-hole depth = 500 + 12 \u2212 3 = 509 \u00b5m<\/strong><\/p>\n\n  <p>The incoming thickness of 700 \u00b5m enters the calculation indirectly: the polishing recipe removes 700 \u2212 500 = 200 \u00b5m of material. The template work-hole depth of 509 \u00b5m ensures the wafer sits at the correct mechanical position relative to the polishing pad for the final 500 \u00b5m target thickness. The \u00b150 \u00b5m incoming thickness tolerance means that lot-to-lot thickness variation must be tracked \u2014 if an incoming lot arrives nominally 30 \u00b5m thinner than spec (670 \u00b5m), the same template will remove only 161 \u00b5m instead of 200 \u00b5m to reach the 509 \u00b5m mechanical stop, requiring recipe time adjustment to compensate.<\/p>\n\n  <hr class=\"divider\" \/>\n\n  <!-- \u2550\u2550\u2550 SECTION 4 \u2014 Borosilicate \u2550\u2550\u2550 -->\n  <h2 id=\"borosilicate\">Borosilicate Glass Wafers<\/h2>\n\n  <div class=\"sub-block\">\n    <div class=\"sub-block-head glass-head\">\n      <h3>Borosilicate Glass (e.g., Schott D263, Corning 7740 \/ Pyrex)<\/h3>\n      <div class=\"sub-apps\">Applications: MEMS substrates, microfluidics, wafer-level packaging, through-glass via (TGV) substrates<\/div>\n    <\/div>\n    <div class=\"sub-block-body\">\n\n      <div class=\"prop-grid\">\n        <div class=\"prop-item\"><div class=\"prop-label\">Mohs hardness<\/div><div class=\"prop-value\">~6.0<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">Fracture toughness<\/div><div class=\"prop-value caution\">0.7\u20130.9 MPa\u00b7m\u00bd<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">CTE<\/div><div class=\"prop-value\">3.3\u20134.0 \u00d7 10\u207b\u2076\/\u00b0C<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">Typical thickness range<\/div><div class=\"prop-value caution\">0.3\u20131.1 mm (non-standard)<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">Incoming TTV typical<\/div><div class=\"prop-value caution\">\u00b125\u201350 \u00b5m<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">Polishing slurry pH<\/div><div class=\"prop-value ok\">9\u201312 (alkaline silica)<\/div><\/div>\n      <\/div>\n\n      <p>Borosilicate glass is the most forgiving of the glass\/ceramic substrates from a template design perspective. Its hardness is comparable to silicon, its fracture toughness is similar to silicon prime wafers, and its primary polishing slurry \u2014 alkaline colloidal silica at pH 9\u201312 \u2014 is compatible with FR-4 carrier plates at moderate cycle counts and fully compatible with G-10 and CXT for extended production use.<\/p>\n\n      <p>The primary template engineering challenge for borosilicate glass is not chemistry or fracture risk but <strong>thickness diversity<\/strong>. Borosilicate glass wafers for MEMS applications arrive at thicknesses from 300 \u00b5m (for thinned substrates) to 1,100 \u00b5m (for rigid carrier applications), compared to the 625\u2013775 \u00b5m range typical for semiconductor wafers. Each thickness requires a custom work-hole depth calculation. Additionally, through-glass via (TGV) substrates often have a target post-polish thickness specified to \u00b15 \u00b5m tolerance for via depth control \u2014 a flatness requirement that demands the same work-hole depth precision as advanced semiconductor applications.<\/p>\n\n      <div class=\"spec-mini\">\n        <div class=\"spec-mini-title title-glass\">Borosilicate Glass \u2014 Template Specification Summary<\/div>\n        <div class=\"spec-mini-grid\">\n          <div class=\"spec-mini-item\"><div class=\"sl\">Carrier material<\/div><div class=\"sv\">FR-4 (alkaline only) \/ G-10<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Backing pad Shore A<\/div><div class=\"sv\">55\u201370<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Process pressure<\/div><div class=\"sv\">2\u20134 psi<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Work-hole clearance<\/div><div class=\"sv\">0.30\u20130.50 mm<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">EER recommended?<\/div><div class=\"sv\">Yes for EE &lt; 3 mm<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Slurry pH tolerance<\/div><div class=\"sv\">8\u201312 (FR-4) \/ 6\u201312 (G-10)<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Key custom input<\/div><div class=\"sv\">Incoming thickness \u00b1 tolerance<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Typical cycle life<\/div><div class=\"sv\">100\u2013200 cycles<\/div><\/div>\n        <\/div>\n      <\/div>\n\n    <\/div>\n  <\/div>\n\n  <!-- \u2550\u2550\u2550 SECTION 5 \u2014 Fused Silica \u2550\u2550\u2550 -->\n  <h2 id=\"fused-silica\">Fused Silica Wafers<\/h2>\n\n  <div class=\"sub-block\">\n    <div class=\"sub-block-head fused-head\">\n      <h3>Fused Silica \/ Fused Quartz (SiO\u2082 amorphous)<\/h3>\n      <div class=\"sub-apps\">Applications: photomask blanks, UV optics, EUV lithography components, precision optical windows, semiconductor process chambers<\/div>\n    <\/div>\n    <div class=\"sub-block-body\">\n\n      <div class=\"prop-grid\">\n        <div class=\"prop-item\"><div class=\"prop-label\">Mohs hardness<\/div><div class=\"prop-value\">~7.0<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">Fracture toughness<\/div><div class=\"prop-value caution\">0.75 MPa\u00b7m\u00bd<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">CTE<\/div><div class=\"prop-value ok\">0.55 \u00d7 10\u207b\u2076\/\u00b0C (very low)<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">Typical thickness range<\/div><div class=\"prop-value caution\">3\u201310 mm (photomask)<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">Surface roughness target<\/div><div class=\"prop-value\">Ra &lt; 0.1 nm (photomask)<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">Polishing slurry pH<\/div><div class=\"prop-value caution\">4\u20138 (CeO\u2082 \/ SiO\u2082)<\/div><\/div>\n      <\/div>\n\n      <p>Fused silica presents a different set of template challenges than borosilicate glass. Its extremely low CTE (0.55 \u00d7 10\u207b\u2076\/\u00b0C, compared to 3.3 \u00d7 10\u207b\u2076\/\u00b0C for borosilicate) makes it dimensionally ultra-stable \u2014 which is exactly why it is used for photomask blanks and EUV lithography components where sub-nm flatness must be maintained across thermal cycling. This low CTE also means that fused silica substrates are extremely sensitive to thermally-induced stress during polishing: any temperature gradient across the substrate during polishing creates differential expansion stress that can exceed the fracture toughness locally and produce subsurface cracking invisible to visual inspection but detectable in post-polish interferometric flatness measurements.<\/p>\n\n      <p>Fused silica polishing \u2014 particularly for photomask blank applications \u2014 uses cerium oxide (CeO\u2082) slurry or mixed CeO\u2082\/SiO\u2082 slurry at mildly acidic to near-neutral pH (4\u20137). This pH range is marginal for FR-4 carrier plates in extended production use and requires G-10 minimum. The surface roughness targets for photomask blank polishing (Ra &lt; 0.1 nm, comparable to silicon prime wafer spec) impose the same demanding template flatness requirements as advanced semiconductor CMP. Work-hole depth precision of \u00b13 \u00b5m and carrier plate bow of \u22645 \u00b5m are required to meet these surface specifications.<\/p>\n\n      <div class=\"callout info\">\n        <span class=\"callout-icon\">\u2139\ufe0f<\/span>\n        <div class=\"callout-body\">\n          <strong>Photomask Blank Thickness: Non-Standard by Design<\/strong>\n          Standard photomask blanks are 6025 format: 152.4 \u00d7 152.4 mm \u00d7 6.35 mm thick. This 6.35 mm (\u00bc inch) thickness is far thicker than any semiconductor wafer and requires a work-hole depth specification that no standard semiconductor polishing template provides. Photomask blank polishing templates are purpose-designed for this format, with deep work holes and stiffer backing pads appropriate for the greater substrate mass under polishing load.\n        <\/div>\n      <\/div>\n\n      <div class=\"spec-mini\">\n        <div class=\"spec-mini-title title-fused\">Fused Silica \u2014 Template Specification Summary<\/div>\n        <div class=\"spec-mini-grid\">\n          <div class=\"spec-mini-item\"><div class=\"sl\">Carrier material<\/div><div class=\"sv\">G-10 or CXT<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Backing pad Shore A<\/div><div class=\"sv\">60\u201375<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Process pressure<\/div><div class=\"sv\">1.5\u20134 psi<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Carrier plate bow<\/div><div class=\"sv\">\u2264 5 \u00b5m (photomask grade)<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Work-hole depth tol.<\/div><div class=\"sv\">\u00b1 3 \u00b5m<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Slurry pH tolerance<\/div><div class=\"sv\">4-8<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Temperature sensitivity<\/div><div class=\"sv\">High \u2014 pad controls critical<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Typical cycle life<\/div><div class=\"sv\">80\u2013150 cycles<\/div><\/div>\n        <\/div>\n      <\/div>\n\n    <\/div>\n  <\/div>\n\n  <!-- \u2550\u2550\u2550 SECTION 6 \u2014 Alumina \u2550\u2550\u2550 -->\n  <h2 id=\"alumina\">Alumina (Al\u2082O\u2083) Ceramic Substrates<\/h2>\n\n  <div class=\"sub-block\">\n    <div class=\"sub-block-head ceramic-head\">\n      <h3>Alumina Ceramic (96\u201399.6% Al\u2082O\u2083)<\/h3>\n      <div class=\"sub-apps\">Applications: power module substrates, microwave circuit boards, LED packages, thick-film hybrid circuits, sensor housings<\/div>\n    <\/div>\n    <div class=\"sub-block-body\">\n\n      <div class=\"prop-grid\">\n        <div class=\"prop-item\"><div class=\"prop-label\">Mohs hardness<\/div><div class=\"prop-value danger\">9.0 (same as sapphire)<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">Fracture toughness<\/div><div class=\"prop-value caution\">3\u20134 MPa\u00b7m\u00bd<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">CTE<\/div><div class=\"prop-value\">6.5\u20138.0 \u00d7 10\u207b\u2076\/\u00b0C<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">Typical size<\/div><div class=\"prop-value caution\">25\u00d725 mm to 100\u00d7100 mm<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">Post-sinter TTV<\/div><div class=\"prop-value danger\">\u00b150\u2013150 \u00b5m (wide)<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">Polishing slurry<\/div><div class=\"prop-value caution\">Diamond, pH 4\u20138<\/div><\/div>\n      <\/div>\n\n      <p>Alumina ceramic substrates are among the hardest materials routinely polished in the electronic substrate market, with Mohs hardness of 9.0 \u2014 equal to sapphire and exceeded only by SiC and diamond. This hardness has direct consequences for template specification: backing pad hardness must be high enough to maintain pressure uniformity under the elevated process pressures (3\u20136 psi) required to achieve acceptable removal rates with diamond abrasive slurry, and carrier plate material must resist the acidic diamond slurry chemistry that FR-4 cannot tolerate.<\/p>\n\n      <p>Alumina ceramics arrive from sintering with relatively wide thickness variation \u2014 \u00b150\u2013150 \u00b5m is typical for standard-grade substrates \u2014 compared to the \u00b15\u201310 \u00b5m of semiconductor prime wafers. This variation must be measured and accounted for in work-hole depth specification. Many alumina polishing applications require a target post-polish TTV of \u226410\u201320 \u00b5m, which is achievable only if the template work-hole depth is correctly matched to the actual incoming substrate thickness distribution. Using a nominal work-hole depth without lot-specific thickness adjustment produces systematic TTV patterns correlated to the thickness variation within the lot.<\/p>\n\n      <p>Alumina substrates also frequently have <strong>non-circular geometries<\/strong> \u2014 squares, rectangles, and custom shapes \u2014 which require custom work-hole shapes rather than circular pockets. This is covered in detail in Section 9.<\/p>\n\n      <div class=\"spec-mini\">\n        <div class=\"spec-mini-title title-ceramic\">Alumina Ceramic \u2014 Template Specification Summary<\/div>\n        <div class=\"spec-mini-grid\">\n          <div class=\"spec-mini-item\"><div class=\"sl\">Carrier material<\/div><div class=\"sv\">G-10 or CXT<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Backing pad Shore A<\/div><div class=\"sv\">65\u201380<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Process pressure<\/div><div class=\"sv\">3\u20136 psi<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Work-hole shape<\/div><div class=\"sv\">Custom (often non-circular)<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Post-sinter TTV input<\/div><div class=\"sv\">Required at order<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Slurry pH tolerance<\/div><div class=\"sv\">4\u20139<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">EER recommended?<\/div><div class=\"sv\">Yes if circular substrate<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Typical cycle life<\/div><div class=\"sv\">60\u2013120 cycles<\/div><\/div>\n        <\/div>\n      <\/div>\n\n    <\/div>\n  <\/div>\n\n  <!-- \u2550\u2550\u2550 SECTION 7 \u2014 AlN \u2550\u2550\u2550 -->\n  <h2 id=\"aln\">Aluminum Nitride (AlN) Substrates<\/h2>\n\n  <div class=\"sub-block\">\n    <div class=\"sub-block-head aln-head\">\n      <h3>Aluminum Nitride (AlN)<\/h3>\n      <div class=\"sub-apps\">Applications: high-power LED packages, RF power amplifier substrates, laser diode heat spreaders, SiC power module carriers<\/div>\n    <\/div>\n    <div class=\"sub-block-body\">\n\n      <div class=\"prop-grid\">\n        <div class=\"prop-item\"><div class=\"prop-label\">Mohs hardness<\/div><div class=\"prop-value caution\">~7.0<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">Thermal conductivity<\/div><div class=\"prop-value ok\">170\u2013230 W\/m\u00b7K (very high)<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">Fracture toughness<\/div><div class=\"prop-value caution\">2.5\u20133.5 MPa\u00b7m\u00bd<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">CTE<\/div><div class=\"prop-value ok\">4.5 \u00d7 10\u207b\u2076\/\u00b0C<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">Hydrolysis sensitivity<\/div><div class=\"prop-value danger\">High \u2014 reacts with water<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">Polishing slurry<\/div><div class=\"prop-value caution\">Non-aqueous or low-water<\/div><\/div>\n      <\/div>\n\n      <p>Aluminum nitride is selected for its exceptional thermal conductivity \u2014 the highest of any practical electronic substrate at 170\u2013230 W\/m\u00b7K \u2014 which makes it essential for high-power LED packages and RF power amplifiers where heat dissipation is the primary design constraint. Its polishing requirements are unlike any other substrate in this guide because of a critical chemical property: AlN reacts with water through hydrolysis \u2014 <em>AlN + 3H\u2082O \u2192 Al(OH)\u2083 + NH\u2083<\/em> \u2014 producing ammonia gas and consuming the substrate surface in any aqueous polishing environment. This hydrolysis reaction is not a slow corrosion process; it is fast enough to cause measurable surface damage within minutes in standard aqueous slurry at room temperature.<\/p>\n\n      <p>AlN polishing therefore requires either <strong>non-aqueous polishing media<\/strong> (organic-solvent-based diamond suspensions) or <strong>passivated aqueous slurry<\/strong> with pH adjustment and inhibitor chemistry that minimizes water activity at the substrate surface. This chemistry requirement dictates the carrier plate material: standard aqueous slurry inhibitor systems often use organic acid passivants at pH 4\u20136, which are incompatible with FR-4. Non-aqueous polishing media may be compatible with G-10 but require verification; CXT-grade is the safe choice for production AlN polishing regardless of the specific slurry chemistry.<\/p>\n\n      <p>Template design for AlN also benefits from minimizing the time the substrate spends wetted after polishing. AlN polishing templates should be specified with a smooth, non-porous carrier plate surface (CXT satisfies this; G-10 has slightly higher surface porosity from exposed fiber) to minimize slurry retention at the template surface that would extend AlN hydrolysis exposure after the polishing cycle ends.<\/p>\n\n      <div class=\"spec-mini\">\n        <div class=\"spec-mini-title title-aln\">AlN Substrate \u2014 Template Specification Summary<\/div>\n        <div class=\"spec-mini-grid\">\n          <div class=\"spec-mini-item\"><div class=\"sl\">Carrier material<\/div><div class=\"sv\">CXT (strongly recommended)<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Backing pad Shore A<\/div><div class=\"sv\">55\u201370<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Process pressure<\/div><div class=\"sv\">2\u20134 psi<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Slurry type<\/div><div class=\"sv\">Non-aqueous or passivated<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Surface texture req.<\/div><div class=\"sv\">Low-porosity carrier face<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Post-polish protocol<\/div><div class=\"sv\">Immediate rinse critical<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Work-hole shape<\/div><div class=\"sv\">Custom (often rectangular)<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Typical cycle life<\/div><div class=\"sv\">80\u2013150 cycles<\/div><\/div>\n        <\/div>\n      <\/div>\n\n    <\/div>\n  <\/div>\n\n  <!-- \u2550\u2550\u2550 SECTION 8 \u2014 LTCC \u2550\u2550\u2550 -->\n  <h2 id=\"ltcc\">LTCC &amp; Thick-Film Ceramic Substrates<\/h2>\n\n  <div class=\"sub-block\">\n    <div class=\"sub-block-head ltcc-head\">\n      <h3>LTCC &amp; Thick-Film Ceramics (Low-Temperature Co-fired Ceramic)<\/h3>\n      <div class=\"sub-apps\">Applications: RF modules, antenna-in-package, 5G front-end modules, multilayer microwave circuits, automotive radar<\/div>\n    <\/div>\n    <div class=\"sub-block-body\">\n\n      <div class=\"prop-grid\">\n        <div class=\"prop-item\"><div class=\"prop-label\">Mohs hardness<\/div><div class=\"prop-value ok\">~5.0\u20136.0 (softer ceramic)<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">Composition<\/div><div class=\"prop-value\">Glass-ceramic composite<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">Metallization layers<\/div><div class=\"prop-value caution\">Ag or Au buried conductors<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">Post-fire shrinkage<\/div><div class=\"prop-value danger\">\u00b10.1\u20130.5% variation<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">Typical panel size<\/div><div class=\"prop-value\">114\u00d7114 mm standard<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">Polish target<\/div><div class=\"prop-value\">Surface planarity for bonding<\/div><\/div>\n      <\/div>\n\n      <p>LTCC substrates are co-fired glass-ceramic composites with buried metal conductors (typically silver or gold), produced in panel form that is then singulated. Their polishing requirements differ from the other ceramics in this guide because LTCC contains both a glass-ceramic matrix <em>\u305d\u3057\u3066<\/em> metal conductors, and polishing must achieve surface planarity without preferentially removing either the ceramic or the metal \u2014 a selective polishing problem similar to CMP damascene metal planarization.<\/p>\n\n      <p>Post-fire LTCC panels arrive with surface topography arising from the differential sintering shrinkage of the glass-ceramic matrix versus the embedded metal layers. The polishing goal is to planarize this topography to within \u00b15\u201310 \u00b5m across the panel for reliable die bonding and interconnect processes. Because LTCC is softer than pure alumina (Mohs ~5\u20136 vs 9 for alumina), lower process pressures (1.5\u20133 psi) and softer backing pads (Shore A 50\u201365) are appropriate \u2014 harder pads at higher pressure cause preferential removal of the softer glass-ceramic matrix relative to the metal conductors, worsening the planarity problem rather than solving it.<\/p>\n\n      <p>LTCC panel formats (114 \u00d7 114 mm or custom sizes) are non-circular and non-standard, requiring custom rectangular work-hole geometry in the polishing template. The work-hole depth must be specified based on the post-fire panel thickness, which itself varies with the number of co-fired layers and firing batch conditions. Obtaining a post-fire thickness measurement from at least 5 sample panels per production lot is the recommended input for work-hole depth specification.<\/p>\n\n      <div class=\"spec-mini\">\n        <div class=\"spec-mini-title title-ltcc\">LTCC \u2014 Template Specification Summary<\/div>\n        <div class=\"spec-mini-grid\">\n          <div class=\"spec-mini-item\"><div class=\"sl\">Carrier material<\/div><div class=\"sv\">G-10 or FR-4 (pH 7\u201310)<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Backing pad Shore A<\/div><div class=\"sv\">50-65<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Process pressure<\/div><div class=\"sv\">1.5\u20133 psi<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Work-hole shape<\/div><div class=\"sv\">Rectangular (custom)<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Thickness input<\/div><div class=\"sv\">Post-fire measurement required<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Slurry pH<\/div><div class=\"sv\">7\u201310 (near-neutral)<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Key metric<\/div><div class=\"sv\">Surface planarity \u2264 \u00b110 \u00b5m<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Typical cycle life<\/div><div class=\"sv\">100\u2013200 cycles<\/div><\/div>\n        <\/div>\n      <\/div>\n\n    <\/div>\n  <\/div>\n\n  <!-- \u2550\u2550\u2550 SECTION 9 \u2550\u2550\u2550 -->\n  <h2 id=\"non-circular\">Non-Circular &amp; Custom-Shape Substrates<\/h2>\n\n  <p>One of the most frequent template engineering questions from glass and ceramic polishing customers concerns non-circular substrate shapes. Semiconductor wafers are circular by definition, and the entire standard polishing template ecosystem is built around circular work holes. But glass and ceramic substrates routinely come in squares, rectangles, and custom polygonal shapes \u2014 and these require custom work-hole geometry that is standard practice for specialized template manufacturers but unavailable from suppliers whose product line covers only semiconductor wafers.<\/p>\n\n  <div class=\"shape-grid\">\n    <div class=\"shape-card\">\n      <div class=\"shape-icon\">\u2b1c<\/div>\n      <div class=\"shape-name\">Square<\/div>\n      <div class=\"shape-note\">Common for ceramic substrates, LTCC panels<\/div>\n    <\/div>\n    <div class=\"shape-card\">\n      <div class=\"shape-icon\">\u25ac<\/div>\n      <div class=\"shape-name\">Rectangle<\/div>\n      <div class=\"shape-note\">LTCC, power module substrates<\/div>\n    <\/div>\n    <div class=\"shape-card\">\n      <div class=\"shape-icon\">\u2b21<\/div>\n      <div class=\"shape-name\">Hexagonal<\/div>\n      <div class=\"shape-note\">Optical windows, specialty components<\/div>\n    <\/div>\n    <div class=\"shape-card\">\n      <div class=\"shape-icon\">\ud83d\udd32<\/div>\n      <div class=\"shape-name\">Multi-cavity<\/div>\n      <div class=\"shape-note\">Multiple small ceramics per carrier<\/div>\n    <\/div>\n    <div class=\"shape-card\">\n      <div class=\"shape-icon\">\u2b55<\/div>\n      <div class=\"shape-name\">Circular<\/div>\n      <div class=\"shape-note\">Standard \u2014 all substrates<\/div>\n    <\/div>\n    <div class=\"shape-card\">\n      <div class=\"shape-icon\">\ud83d\udd37<\/div>\n      <div class=\"shape-name\">\u30ab\u30b9\u30bf\u30e0<\/div>\n      <div class=\"shape-note\">Any shape from engineering drawing<\/div>\n    <\/div>\n  <\/div>\n\n  <h3>Engineering Requirements for Non-Circular Work Holes<\/h3>\n  <p>Non-circular work holes require the same clearance engineering as circular ones \u2014 the gap between the substrate perimeter and the work-hole wall must be 0.25\u20130.50 mm to prevent edge contact during polishing while constraining the substrate from lateral movement. For rectangular substrates, this means specifying the work-hole dimensions as substrate length + 0.50 mm \u00d7 substrate width + 0.50 mm. Corner geometry requires a radius (typically 0.5\u20131.0 mm) to match the substrate&#8217;s corner chamfer or to prevent stress concentration at sharp internal corners that could initiate carrier plate cracking under cyclic polishing load.<\/p>\n\n  <p>Multi-cavity templates for small ceramic substrates \u2014 for example, a carrier holding six 25 \u00d7 25 mm alumina substrates simultaneously \u2014 require precise inter-cavity spacing and equal work-hole depth across all cavities. The depth uniformity across cavities (\u22645 \u00b5m variation between the deepest and shallowest cavity on a single carrier) directly controls the TTV uniformity between substrates polished simultaneously, and is verified by CMM measurement of each cavity before dispatch. For non-circular multi-cavity templates, providing a dimensioned engineering drawing of the substrate and the desired cavity layout at time of order is the most efficient way to specify the template geometry.<\/p>\n\n  <hr class=\"divider\" \/>\n\n  <!-- \u2550\u2550\u2550 SECTION 10 \u2550\u2550\u2550 -->\n  <h2 id=\"slurry-table\">Slurry Chemistry &amp; Template Material Selection Table<\/h2>\n\n  <div class=\"table-wrap\">\n    <table>\n      <thead>\n        <tr>\n          <th>Substrate<\/th>\n          <th>Slurry Chemistry<\/th>\n          <th>pH\u7bc4\u56f2<\/th>\n          <th>FR-4<\/th>\n          <th>G-10<\/th>\n          <th>CXT<\/th>\n        <\/tr>\n      <\/thead>\n      <tbody>\n        <tr class=\"row-green\">\n          <td><strong>Borosilicate glass<\/strong><\/td>\n          <td>Colloidal silica, alkaline<\/td>\n          <td>9-12<\/td>\n          <td><span class=\"badge badge-green\">Acceptable<\/span><\/td>\n          <td><span class=\"badge badge-green\">\u30b0\u30c3\u30c9<\/span><\/td>\n          <td><span class=\"badge badge-green\">Recommended<\/span><\/td>\n        <\/tr>\n        <tr>\n          <td><strong>Borosilicate glass<\/strong><\/td>\n          <td>CeO\u2082, mildly acidic<\/td>\n          <td>5\u20138<\/td>\n          <td><span class=\"badge badge-amber\">Marginal<\/span><\/td>\n          <td><span class=\"badge badge-green\">\u30b0\u30c3\u30c9<\/span><\/td>\n          <td><span class=\"badge badge-green\">Recommended<\/span><\/td>\n        <\/tr>\n        <tr class=\"row-warn\">\n          <td><strong>Borosilicate glass<\/strong><\/td>\n          <td>NH\u2084F \/ BHF (etch polish)<\/td>\n          <td>4\u20136<\/td>\n          <td><span class=\"badge badge-red\">Not suitable<\/span><\/td>\n          <td><span class=\"badge badge-red\">Not suitable<\/span><\/td>\n          <td><span class=\"badge badge-green\">Required<\/span><\/td>\n        <\/tr>\n        <tr>\n          <td><strong>Fused silica<\/strong><\/td>\n          <td>CeO\u2082 \/ SiO\u2082 acidic<\/td>\n          <td>4-7<\/td>\n          <td><span class=\"badge badge-amber\">Marginal<\/span><\/td>\n          <td><span class=\"badge badge-green\">\u30b0\u30c3\u30c9<\/span><\/td>\n          <td><span class=\"badge badge-green\">Recommended<\/span><\/td>\n        <\/tr>\n        <tr>\n          <td><strong>Alumina ceramic<\/strong><\/td>\n          <td>Diamond abrasive, acidic<\/td>\n          <td>4-8<\/td>\n          <td><span class=\"badge badge-red\">Not suitable<\/span><\/td>\n          <td><span class=\"badge badge-green\">\u30b0\u30c3\u30c9<\/span><\/td>\n          <td><span class=\"badge badge-green\">Recommended<\/span><\/td>\n        <\/tr>\n        <tr>\n          <td><strong>AlN substrate<\/strong><\/td>\n          <td>Non-aqueous \/ passivated<\/td>\n          <td>4-7<\/td>\n          <td><span class=\"badge badge-red\">Not suitable<\/span><\/td>\n          <td><span class=\"badge badge-amber\">Marginal<\/span><\/td>\n          <td><span class=\"badge badge-green\">Required<\/span><\/td>\n        <\/tr>\n        <tr class=\"row-green\">\n          <td><strong>LTCC \/ thick-film<\/strong><\/td>\n          <td>Near-neutral silica<\/td>\n          <td>7-10<\/td>\n          <td><span class=\"badge badge-green\">Acceptable<\/span><\/td>\n          <td><span class=\"badge badge-green\">\u30b0\u30c3\u30c9<\/span><\/td>\n          <td><span class=\"badge badge-green\">Recommended<\/span><\/td>\n        <\/tr>\n      <\/tbody>\n    <\/table>\n  <\/div>\n\n  <hr class=\"divider\" \/>\n\n  <!-- \u2550\u2550\u2550 SECTION 11 \u2550\u2550\u2550 -->\n  <h2 id=\"comparison\">Full Specification Comparison<\/h2>\n\n  <div class=\"table-wrap\">\n    <table>\n      <thead>\n        <tr>\n          <th>\u30d1\u30e9\u30e1\u30fc\u30bf<\/th>\n          <th>Borosilicate Glass<\/th>\n          <th>Fused Silica<\/th>\n          <th>\u30a2\u30eb\u30df\u30ca<\/th>\n          <th>AlN<\/th>\n          <th>LTCC<\/th>\n        <\/tr>\n      <\/thead>\n      <tbody>\n        <tr>\n          <td><strong>Carrier plate<\/strong><\/td>\n          <td>FR-4 \/ G-10<\/td>\n          <td>G-10 \/ CXT<\/td>\n          <td>G-10 \/ CXT<\/td>\n          <td>CXT<\/td>\n          <td>FR-4 \/ G-10<\/td>\n        <\/tr>\n        <tr class=\"row-highlight\">\n          <td><strong>Backing pad Shore A<\/strong><\/td>\n          <td>55\u201370<\/td>\n          <td>60\u201375<\/td>\n          <td>65\u201380<\/td>\n          <td>55\u201370<\/td>\n          <td>50-65<\/td>\n        <\/tr>\n        <tr>\n          <td><strong>Process pressure<\/strong><\/td>\n          <td>2\u20134 psi<\/td>\n          <td>1.5\u20134 psi<\/td>\n          <td>3\u20136 psi<\/td>\n          <td>2\u20134 psi<\/td>\n          <td>1.5\u20133 psi<\/td>\n        <\/tr>\n        <tr>\n          <td><strong>Work-hole shape<\/strong><\/td>\n          <td>Circular<\/td>\n          <td>Circular \/ square<\/td>\n          <td>Custom required<\/td>\n          <td>Custom required<\/td>\n          <td>Rectangular<\/td>\n        <\/tr>\n        <tr>\n          <td><strong>Thickness input critical?<\/strong><\/td>\n          <td><span class=\"badge badge-red\">Yes \u2014 always<\/span><\/td>\n          <td><span class=\"badge badge-red\">Yes \u2014 always<\/span><\/td>\n          <td><span class=\"badge badge-red\">Yes \u2014 always<\/span><\/td>\n          <td><span class=\"badge badge-red\">Yes \u2014 always<\/span><\/td>\n          <td><span class=\"badge badge-red\">Yes \u2014 post-fire<\/span><\/td>\n        <\/tr>\n        <tr>\n          <td><strong>Fluoride chemistry?<\/strong><\/td>\n          <td>Possible \u2014 CXT only<\/td>\n          <td>Rare<\/td>\n          <td>No<\/td>\n          <td>No<\/td>\n          <td>No<\/td>\n        <\/tr>\n        <tr>\n          <td><strong>Key challenge<\/strong><\/td>\n          <td>Thickness diversity<\/td>\n          <td>Ra &lt; 0.1 nm spec<\/td>\n          <td>Hardness + geometry<\/td>\n          <td>Hydrolysis risk<\/td>\n          <td>Metal + ceramic co-removal<\/td>\n        <\/tr>\n        <tr>\n          <td><strong>Typical cycle life<\/strong><\/td>\n          <td>100\u2013200<\/td>\n          <td>80\u2013150<\/td>\n          <td>60\u2013120<\/td>\n          <td>80\u2013150<\/td>\n          <td>100\u2013200<\/td>\n        <\/tr>\n      <\/tbody>\n    <\/table>\n  <\/div>\n\n  <!-- Related articles -->\n  <div class=\"related-box\">\n    <h3>\ud83d\udcd6 Related Technical Articles<\/h3>\n    <p>Complete your substrate-specific polishing template knowledge with these guides:<\/p>\n    <div class=\"related-links\">\n      <a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/Polishing-Templates-for-Semiconductor-Silicon-Wafer-Processing\/\" target=\"_blank\">Polishing Templates: Complete Guide<\/a>\n      <a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/How-to-Specify-a-Polishing-Template-6-Parameters-Engineers-Must-Define\/\" target=\"_blank\">6\u30d1\u30e9\u30e1\u30fc\u30bf\u4ed5\u69d8\u30ac\u30a4\u30c9<\/a>\n      <a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/FR-4-vs-G-10-Fiberglass-Polishing-Templates-Material-Properties-Selection-Guide\/\" target=\"_blank\">FR-4 vs G-10 vs CXT Materials<\/a>\n      <a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/SiC-Wafer-Polishing-Templates-Chemically-Resistant-Solutions-for-Silicon-Carbide-Processing\/\" target=\"_blank\">SiC Polishing Templates<\/a>\n      <a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/Polishing-Templates-for-Compound-Semiconductor-Wafers-GaAs-InP-Sapphire\/\" target=\"_blank\">GaAs \/ InP \/ \u30b5\u30d5\u30a1\u30a4\u30a2\u30fb\u30c6\u30f3\u30d7\u30ec\u30fc\u30c8<\/a>\n      <a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/How-Polishing-Template-Edge-Design-Controls-Wafer-Edge-Profile-Reduces-Edge-Exclusion\/\" target=\"_blank\">Edge Profile &amp; EER Design<\/a>\n      <a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/Custom-Polishing-Templates-for-Silicon-Wafers-Tailored-to-Your-Carrier-Head-Specs\/\" target=\"_blank\">\u30ab\u30b9\u30bf\u30e0\u30fb\u30c6\u30f3\u30d7\u30ec\u30fc\u30c8\u30fb\u30a8\u30f3\u30b8\u30cb\u30a2\u30ea\u30f3\u30b0<\/a>\n    <\/div>\n  <\/div>\n\n  <hr class=\"divider\" \/>\n\n  <!-- \u2550\u2550\u2550 FAQ \u2550\u2550\u2550 -->\n  <h2 id=\"faq\">\u3088\u304f\u3042\u308b\u8cea\u554f<\/h2>\n\n  <div class=\"faq-item\">\n    <div class=\"faq-q\">What makes polishing templates for glass wafers different from semiconductor wafer templates?<\/div>\n    <div class=\"faq-a\">The most consequential difference is non-standard thickness. Glass wafers arrive at 0.3\u20132.0 mm thickness with \u00b125\u2013100 \u00b5m incoming variation \u2014 far outside the standardized SEMI thicknesses and tight tolerances of semiconductor wafers. Every glass polishing template requires custom work-hole depth calculation based on the specific incoming thickness, target final thickness, and backing pad compression for that application. The second key difference is slurry chemistry: glass polishing spans pH 4\u201312 including fluoride-containing chemistries, requiring carrier plate material selection based on the specific slurry, rather than assuming the standard FR-4 used for silicon.<\/div>\n  <\/div>\n\n  <div class=\"faq-item\">\n    <div class=\"faq-q\">Can standard FR-4 polishing templates be used for glass wafer polishing?<\/div>\n    <div class=\"faq-a\">FR-4 is acceptable only for borosilicate glass polishing using alkaline colloidal silica slurry at pH 9\u201312. Any process using acidic slurry below pH 8, or fluoride-containing chemistry (HF, NH\u2084F, BHF), requires G-10 minimum and CXT-grade for fluoride applications. For alumina ceramic, AlN, and fused silica polishing with diamond or CeO\u2082 acidic slurry, FR-4 is unsuitable. Specifying the slurry chemistry and pH range at time of order is the most reliable way to ensure the correct carrier plate material is selected.<\/div>\n  <\/div>\n\n  <div class=\"faq-item\">\n    <div class=\"faq-q\">What polishing template is used for alumina ceramic substrates?<\/div>\n    <div class=\"faq-a\">Alumina polishing uses diamond abrasive slurry at pH 4\u20138, requiring G-10 or CXT-grade carrier plate material. Its hardness (Mohs 9.0) demands harder backing pads (Shore A 65\u201380) and higher process pressures (3\u20136 psi) than silicon. Alumina substrates frequently come in non-circular shapes (squares, rectangles) requiring custom work-hole geometry. Post-sinter thickness variation (\u00b150\u2013150 \u00b5m) must be measured and provided at order to enable correct work-hole depth calculation.<\/div>\n  <\/div>\n\n  <div class=\"faq-item\">\n    <div class=\"faq-q\">How is work-hole depth specified for glass wafers with non-standard thickness?<\/div>\n    <div class=\"faq-a\">Work-hole depth = Target Final Thickness + Backing Pad Compression Offset \u2212 Overpolish Allowance. The backing pad compression offset (typically 5\u201320 \u00b5m at process pressure) is measured empirically for the specific pad specification. Because glass wafers have wider incoming thickness variation, lot-to-lot thickness measurement is required \u2014 a nominal work-hole depth calculated from the mean incoming thickness will produce systematic TTV errors for lots arriving outside the nominal. Providing the incoming thickness specification (nominal \u00b1 tolerance) at time of order enables correct work-hole depth calculation for your process.<\/div>\n  <\/div>\n\n  <div class=\"faq-item\">\n    <div class=\"faq-q\">Why does AlN require non-aqueous or passivated polishing slurry?<\/div>\n    <div class=\"faq-a\">AlN undergoes hydrolysis in water: AlN + 3H\u2082O \u2192 Al(OH)\u2083 + NH\u2083. This reaction is fast enough to cause measurable surface damage to AlN substrates in standard aqueous slurry within minutes. Non-aqueous polishing media (organic-solvent-based diamond suspensions) avoid the reaction entirely. Passivated aqueous systems use pH control and organic inhibitors to reduce water activity at the substrate surface and slow the hydrolysis rate to acceptable levels. CXT-grade templates are recommended for AlN regardless of slurry choice, as the carrier plate surface texture must minimize post-cycle slurry retention that would extend AlN&#8217;s hydrolysis exposure after polishing ends.<\/div>\n  <\/div>\n\n  <!-- CTA -->\n  <div class=\"cta-banner\">\n    <h2>Get a Quote for Your Glass or Ceramic Polishing Template<\/h2>\n    <p>Share your substrate material, geometry, incoming thickness specification, target final thickness, and slurry chemistry \u2014 our engineering team will calculate the correct work-hole depth and provide a competitive quote within 48 hours.<\/p>\n    <a href=\"https:\/\/jeez-semicon.com\/ja\/contact\/\" class=\"cta-btn\" target=\"_blank\">\n      \u304a\u898b\u7a4d\u3082\u308a\u306f\u3053\u3061\u3089 \u2192 \u304a\u554f\u3044\u5408\u308f\u305b\n    <\/a>\n  <\/div>\n\n  <a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/Polishing-Templates-for-Semiconductor-Silicon-Wafer-Processing\/\" target=\"_blank\" class=\"back-to-pillar\">\n    Back to Polishing Templates: Complete Guide\n  <\/a>\n\n<\/div>\n<\/body>\n<\/html>","protected":false},"excerpt":{"rendered":"<p>Glass &amp; Ceramic Substrates Glass and ceramic substrates span the widest thickness range, the most varied chemistries, and the most diverse geometries of any substrate category. Getting the polishing template  &#8230;<\/p>","protected":false},"author":1,"featured_media":1690,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[9,59],"tags":[],"class_list":["post-1664","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-blog","category-industry"],"acf":[],"_links":{"self":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts\/1664","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/comments?post=1664"}],"version-history":[{"count":2,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts\/1664\/revisions"}],"predecessor-version":[{"id":1666,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts\/1664\/revisions\/1666"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/media\/1690"}],"wp:attachment":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/media?parent=1664"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/categories?post=1664"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/tags?post=1664"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}