{"id":1667,"date":"2026-03-13T09:16:49","date_gmt":"2026-03-13T01:16:49","guid":{"rendered":"https:\/\/jeez-semicon.com\/?p=1667"},"modified":"2026-03-13T09:53:52","modified_gmt":"2026-03-13T01:53:52","slug":"why-is-your-wafer-edge-profile-poor-5-template-related-causes-solutions","status":"publish","type":"post","link":"https:\/\/jeez-semicon.com\/ja\/blog\/why-is-your-wafer-edge-profile-poor-5-template-related-causes-solutions\/","title":{"rendered":"\u306a\u305c\u30a6\u30a7\u30fc\u30cf\u30a8\u30c3\u30b8\u306e\u30d7\u30ed\u30d5\u30a1\u30a4\u30eb\u304c\u60aa\u3044\u306e\u304b\uff1f\u30c6\u30f3\u30d7\u30ec\u30fc\u30c8\u306b\u95a2\u9023\u3059\u308b5\u3064\u306e\u539f\u56e0\u3068\u89e3\u6c7a\u7b56"},"content":{"rendered":"<!DOCTYPE html>\n<html lang=\"en\">\n<head>\n<meta charset=\"UTF-8\" \/>\n<meta name=\"viewport\" content=\"width=device-width, initial-scale=1.0\" \/>\n\n<meta name=\"description\" content=\"Systematic diagnostic guide to the 5 most common template-related causes of poor wafer edge profile: work-hole clearance, EER geometry, backing pad wear, carrier plate bow, and EER height drift. Includes SPC signatures, root cause isolation tests, and corrective actions.\" \/>\n<meta name=\"keywords\" content=\"wafer edge profile problem, polishing template edge defect, edge rolloff cause, wafer edge exclusion too large, polishing template troubleshooting, EER height problem, wafer edge chip polishing, poor edge profile CMP, template edge profile diagnosis\" \/>\n<link rel=\"canonical\" href=\"https:\/\/jeez-semicon.com\/blog\/Why-Is-Your-Wafer-Edge-Profile-Poor-5-Template-Related-Causes-Solutions\" \/>\n\n<meta property=\"og:title\" content=\"Why Is Your Wafer Edge Profile Poor? 5 Template-Related Causes &#038; Solutions\" \/>\n<meta property=\"og:description\" content=\"A structured diagnostic guide to identifying and correcting the 5 most common polishing template causes of poor wafer edge profile \u2014 with distinguishing SPC signatures, isolation tests, and specific corrective actions for each cause.\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:url\" content=\"https:\/\/jeez-semicon.com\/blog\/Why-Is-Your-Wafer-Edge-Profile-Poor-5-Template-Related-Causes-Solutions\" \/>\n\n<script type=\"application\/ld+json\">\n{\n  \"@context\": \"https:\/\/schema.org\",\n  \"@graph\": [\n    {\n      \"@type\": \"Article\",\n      \"headline\": \"Why Is Your Wafer Edge Profile Poor? 5 Template-Related Causes & Solutions\",\n      \"description\": \"Structured diagnostic guide to the 5 most common polishing template causes of poor wafer edge profile, with distinguishing SPC signatures, root cause isolation tests, and corrective actions for each cause.\",\n      \"author\": { \"@type\": \"Organization\", \"name\": \"Jizhi Electronic Technology Co., Ltd.\", \"url\": \"https:\/\/jeez-semicon.com\" },\n      \"publisher\": { \"@type\": \"Organization\", \"name\": \"Jizhi Electronic Technology Co., Ltd.\", \"url\": \"https:\/\/jeez-semicon.com\" },\n      \"mainEntityOfPage\": { \"@type\": \"WebPage\", \"@id\": \"https:\/\/jeez-semicon.com\/blog\/Why-Is-Your-Wafer-Edge-Profile-Poor-5-Template-Related-Causes-Solutions\" }\n    },\n    {\n      \"@type\": \"FAQPage\",\n      \"mainEntity\": [\n        {\n          \"@type\": \"Question\",\n          \"name\": \"How do I know if my wafer edge profile problem is template-related?\",\n          \"acceptedAnswer\": {\n            \"@type\": \"Answer\",\n            \"text\": \"Template-related edge profile problems have three distinguishing characteristics. First, they are reproducible across wafers polished on the same template \u2014 the same edge profile pattern appears on every wafer from a given template lot. Second, they change when the template is swapped for a known-good replacement, while all other process parameters remain constant. Third, they often correlate with template cycle count \u2014 problems that worsen gradually over 20\u201350 cycles suggest backing pad wear, while problems that appear suddenly suggest a dimensional defect in the new template lot. If your edge profile excursion shows any of these characteristics, template isolation testing (a controlled swap with a replacement template) is the definitive diagnostic step.\"\n          }\n        },\n        {\n          \"@type\": \"Question\",\n          \"name\": \"What causes wafer edge rolloff in polishing?\",\n          \"acceptedAnswer\": {\n            \"@type\": \"Answer\",\n            \"text\": \"Wafer edge rolloff occurs when the polishing pad deflects downward at the wafer perimeter, reducing local contact pressure and material removal rate in the annular zone near the wafer edge. Template-related contributions to rolloff include insufficient or absent EER (no mechanical support for the pad in the rolloff zone), worn backing pad (increasing effective work-hole depth which recesses the wafer relative to the ideal contact plane), excessive work-hole radial clearance (allowing the wafer to shift laterally and creating non-uniform edge gap), and carrier plate bow (introducing a long-range pressure gradient that superimposes on the edge rolloff profile).\"\n          }\n        },\n        {\n          \"@type\": \"Question\",\n          \"name\": \"What is the difference between edge rolloff and edge upturn?\",\n          \"acceptedAnswer\": {\n            \"@type\": \"Answer\",\n            \"text\": \"Edge rolloff (also called edge high or edge thick) describes the zone near the wafer perimeter where the polished surface is thicker than the wafer body \u2014 the polishing pad deflects away from the wafer at the edge, reducing removal rate and leaving the edge raised. Edge upturn is the same phenomenon described from the opposite surface perspective in certain measurement conventions. Edge high (edge thick relative to the center) is typically caused by an absent or undersized EER, or by a backing pad that is too stiff for the process conditions. The opposite condition \u2014 edge thin, or over-polished edge \u2014 is caused by an EER that is too tall, which over-corrects the rolloff and creates excessive contact pressure at the wafer perimeter.\"\n          }\n        },\n        {\n          \"@type\": \"Question\",\n          \"name\": \"How often should polishing templates be replaced to maintain edge profile performance?\",\n          \"acceptedAnswer\": {\n            \"@type\": \"Answer\",\n            \"text\": \"There is no universal replacement cycle \u2014 the correct interval is determined by monitoring edge profile performance (specifically, rolloff height at 1 mm and 2 mm from the wafer edge) as a function of template cycle count on a statistical process control chart. For silicon SSP templates with standard backing pads at 3\u20135 psi, edge profile begins degrading measurably between cycle 60 and 100 as the backing pad wears and the effective work-hole depth increases. For SiC CMP templates at higher pressures, degradation begins earlier (cycle 40\u201370). The control chart will show the gradual rolloff increase as the template ages; the replacement trigger is set at the cycle count where rolloff height crosses the upper control limit for the process specification.\"\n          }\n        }\n      ]\n    }\n  ]\n}\n<\/script>\n\n<style>\n  @import url('https:\/\/fonts.googleapis.com\/css2?family=DM+Serif+Display:ital@0;1&family=DM+Sans:opsz,wght@9..40,300;9..40,400;9..40,500;9..40,600&family=JetBrains+Mono:wght@400;500&display=swap');\n\n  :root {\n    --navy:      #0a1628;\n    --navy-mid:  #112240;\n    --blue:      #1a56db;\n    --blue-lite: #3b82f6;\n    --cyan:      #06b6d4;\n    --slate:     #334155;\n    --muted:     #64748b;\n    --border:    #e2e8f0;\n    --bg:        #f8fafc;\n    --white:     #ffffff;\n    --accent:    #f59e0b;\n    --green:     #10b981;\n    --teal:      #0f766e;\n    --red:       #ef4444;\n    --orange:    #ea580c;\n    --radius:    10px;\n    --shadow:    0 4px 24px rgba(10,22,40,.08);\n    --shadow-lg: 0 12px 48px rgba(10,22,40,.14);\n  }\n\n  *, *::before, *::after { box-sizing: border-box; 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}\n  tbody tr.row-highlight td { background: #f0fdf4; }\n  tbody tr.row-warn td { background: #fffbeb; }\n\n  .badge { display: inline-block; padding: 2px 8px; border-radius: 4px; font-size: 11.5px; font-weight: 600; letter-spacing: .04em; text-transform: uppercase; }\n  .badge-green  { background: #d1fae5; color: #065f46; }\n  .badge-blue   { background: #dbeafe; color: #1e40af; }\n  .badge-amber  { background: #fef3c7; color: #92400e; }\n  .badge-red    { background: #fee2e2; color: #991b1b; }\n  .badge-orange { background: #ffedd5; color: #7c2d12; }\n  .badge-slate  { background: #f1f5f9; color: #475569; }\n\n  \/* \u2500\u2500 Cause cards (the 5 main sections) \u2500\u2500 *\/\n  .cause-card {\n    border: 1px solid var(--border); border-radius: var(--radius);\n    overflow: hidden; margin: 32px 0; box-shadow: var(--shadow);\n  }\n  .cause-card-head {\n    display: flex; align-items: center; gap: 16px;\n    padding: 18px 24px;\n    background: linear-gradient(135deg, #1a0f08 0%, #2d1f0f 100%);\n    border-bottom: 1px solid rgba(255,255,255,.08);\n  }\n  .cause-num {\n    width: 42px; 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}\n  .cause-body { padding: 22px 24px; }\n\n  \/* \u2500\u2500 Diagnosis row within cause cards \u2500\u2500 *\/\n  .diag-grid { display: grid; grid-template-columns: 1fr 1fr 1fr; gap: 14px; margin: 18px 0; }\n  @media (max-width: 640px) { .diag-grid { grid-template-columns: 1fr; } }\n  .diag-cell { border-radius: 8px; padding: 14px 16px; }\n  .diag-cell.signature { background: #fef2f2; border: 1px solid #fecaca; }\n  .diag-cell.isolation { background: #eff6ff; border: 1px solid #bfdbfe; }\n  .diag-cell.solution  { background: #f0fdf4; border: 1px solid #bbf7d0; }\n  .diag-cell-label {\n    font-family: 'JetBrains Mono', monospace; font-size: 10px; font-weight: 700;\n    text-transform: uppercase; letter-spacing: .1em; margin-bottom: 7px;\n  }\n  .diag-cell.signature .diag-cell-label { color: #b91c1c; }\n  .diag-cell.isolation .diag-cell-label { color: #1d4ed8; }\n  .diag-cell.solution  .diag-cell-label { color: #065f46; }\n  .diag-cell ul { padding-left: 16px; margin: 0; }\n  .diag-cell li { font-size: 13.5px; margin-bottom: 6px; line-height: 1.5; }\n  .diag-cell li:last-child { margin-bottom: 0; }\n\n  \/* \u2500\u2500 SPC sparkline (CSS-only representation) \u2500\u2500 *\/\n  .spc-strip {\n    background: var(--navy); border-radius: 8px; padding: 14px 18px;\n    margin: 14px 0; display: flex; align-items: center; gap: 14px;\n  }\n  .spc-label { font-family: 'JetBrains Mono', monospace; font-size: 11px; color: rgba(255,255,255,.5); flex-shrink: 0; width: 80px; }\n  .spc-bars { display: flex; align-items: flex-end; gap: 3px; height: 32px; flex: 1; }\n  .spc-bar { flex: 1; border-radius: 2px 2px 0 0; min-height: 4px; }\n  .spc-note { font-size: 12px; color: rgba(255,255,255,.45); flex-shrink: 0; width: 120px; font-family: 'JetBrains Mono', monospace; }\n\n  \/* Flat profile (good) *\/\n  .bar-flat { background: var(--green); height: 60%; }\n\n  \/* Gradual rise (pad wear) *\/\n  .bar-rise-1  { background: var(--green);  height: 30%; }\n  .bar-rise-2  { background: var(--green);  height: 33%; }\n  .bar-rise-3  { background: var(--green);  height: 36%; }\n  .bar-rise-4  { background: var(--accent); height: 42%; }\n  .bar-rise-5  { background: var(--accent); height: 50%; }\n  .bar-rise-6  { background: var(--accent); height: 60%; }\n  .bar-rise-7  { background: var(--red);    height: 75%; }\n  .bar-rise-8  { background: var(--red);    height: 90%; }\n\n  \/* Step change (new lot defect) *\/\n  .bar-step-ok   { background: var(--green); height: 35%; }\n  .bar-step-jump { background: var(--red);   height: 88%; }\n\n  \/* Cycling pattern (EER height instability) *\/\n  .bar-cy-lo { background: var(--green);  height: 30%; }\n  .bar-cy-hi { background: var(--accent); height: 65%; }\n\n  \/* Asymmetric (clearance \/ bow) *\/\n  .bar-asym-lo  { background: var(--green); height: 28%; }\n  .bar-asym-hi  { background: var(--red);   height: 85%; }\n  .bar-asym-mid { background: var(--green); height: 30%; }\n\n  \/* \u2500\u2500 Diagnostic flowchart \u2500\u2500 *\/\n  .flow-chart { background: var(--bg); border: 1px solid var(--border); border-radius: var(--radius); padding: 24px; margin: 28px 0; }\n  .flow-chart-title { font-family: 'JetBrains Mono', monospace; font-size: 11px; font-weight: 600; letter-spacing: .1em; text-transform: uppercase; color: var(--orange); margin-bottom: 18px; }\n  .flow-row { display: flex; align-items: center; gap: 0; margin-bottom: 8px; flex-wrap: wrap; gap: 8px; }\n  .flow-q {\n    background: var(--navy); color: var(--white);\n    border-radius: 6px; padding: 8px 14px;\n    font-size: 13.5px; font-weight: 500;\n  }\n  .flow-arrow { color: var(--muted); font-size: 18px; margin: 0 4px; }\n  .flow-yes { background: #d1fae5; color: #065f46; border-radius: 5px; padding: 6px 12px; font-size: 13px; font-weight: 600; }\n  .flow-no  { background: #fee2e2; color: #991b1b; border-radius: 5px; padding: 6px 12px; font-size: 13px; font-weight: 600; }\n  .flow-cause { background: var(--orange); color: var(--white); border-radius: 5px; padding: 6px 12px; font-size: 12.5px; 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border-radius: 4px; padding: 2px 6px; flex-shrink: 0; margin-top: 1px; }\n  .faq-a { font-size: 15px; color: var(--slate); padding-left: 32px; }\n\n  \/* \u2500\u2500 CTA \u2500\u2500 *\/\n  .cta-banner { background: linear-gradient(135deg, #1a0808 0%, #0a1628 100%); border-radius: var(--radius); padding: 44px 40px; text-align: center; color: var(--white); margin: 56px 0 0; box-shadow: var(--shadow-lg); position: relative; overflow: hidden; }\n  .cta-banner::before { content: ''; position: absolute; inset: 0; background: radial-gradient(ellipse at 65% 40%, rgba(234,88,12,.15) 0%, transparent 60%); pointer-events: none; }\n  .cta-banner h2 { font-family: 'DM Serif Display', serif; font-size: clamp(22px, 3.5vw, 30px); color: var(--white); margin: 0 0 12px; }\n  .cta-banner p { color: rgba(255,255,255,.72); font-size: 16px; max-width: 520px; margin: 0 auto 28px; }\n  .cta-btn { display: inline-flex; align-items: center; gap: 8px; background: #fdba74; color: var(--navy); text-decoration: none; font-weight: 600; font-size: 15px; padding: 14px 32px; border-radius: 8px; transition: opacity .2s, transform .15s; }\n  .cta-btn:hover { opacity: .9; transform: translateY(-1px); color: var(--navy); }\n\n  .back-to-pillar { display: inline-flex; align-items: center; gap: 8px; background: var(--bg); border: 1px solid var(--border); color: var(--slate); text-decoration: none; font-size: 13.5px; font-weight: 500; padding: 10px 18px; border-radius: 8px; margin: 40px 0 0; transition: border-color .2s, color .2s; }\n  .back-to-pillar::before { content: '\u2190'; color: var(--blue); }\n  .back-to-pillar:hover { border-color: var(--blue); color: var(--blue); }\n<\/style>\n<\/head>\n<body>\n\n<div class=\"hero\">\n  <div class=\"hero-eyebrow\">Troubleshooting Guide<\/div>\n  <p class=\"hero-sub\">Before adjusting your process recipe, check the template. Five specific template conditions account for the majority of edge profile excursions in production \u2014 and each one has a distinct SPC signature, a definitive isolation test, and a targeted corrective action.<\/p>\n  <p class=\"hero-meta\">\n    <span>Jizhi Electronic Technology Co, Ltd.\u306b\u3088\u308b\u3002.<\/span>\n    <span>\u00b7<\/span>\n    <span>\u534a\u5c0e\u4f53\u7814\u78e8\u306e\u30b9\u30da\u30b7\u30e3\u30ea\u30b9\u30c8<\/span>\n    <span>\u00b7<\/span>\n    <span>12 min read<\/span>\n  <\/p>\n<\/div>\n\n<div class=\"page-wrap\">\n\n  <nav class=\"breadcrumb\">\n    <a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/Polishing-Templates-for-Semiconductor-Silicon-Wafer-Processing\/\" target=\"_blank\">\u2190 Polishing Templates: Complete Guide<\/a>\n    <span>\/<\/span>\n    \u30a8\u30c3\u30b8\u30fb\u30d7\u30ed\u30d5\u30a1\u30a4\u30eb\u306e\u30c8\u30e9\u30d6\u30eb\u30b7\u30e5\u30fc\u30c6\u30a3\u30f3\u30b0\n  <\/nav>\n\n  <nav class=\"toc-box\">\n    <h2>\u76ee\u6b21<\/h2>\n    <ol class=\"toc-list\">\n      <li><a href=\"#when-template\">When to Suspect the Template First<\/a><\/li>\n      <li><a href=\"#diagnostic-flow\">Diagnostic Flowchart: Isolating Edge Profile Root Cause<\/a><\/li>\n      <li><a href=\"#cause1\">Cause 1 \u2014 Absent or Undersized EER<\/a><\/li>\n      <li><a href=\"#cause2\">Cause 2 \u2014 Worn Backing Pad (Cycle-Count-Linked Drift)<\/a><\/li>\n      <li><a href=\"#cause3\">Cause 3 \u2014 Excessive Work-Hole Radial Clearance<\/a><\/li>\n      <li><a href=\"#cause4\">Cause 4 \u2014 Carrier Plate Bow<\/a><\/li>\n      <li><a href=\"#cause5\">Cause 5 \u2014 EER Height Over-Correction<\/a><\/li>\n      <li><a href=\"#non-template\">When the Problem Is Not the Template<\/a><\/li>\n      <li><a href=\"#spc-guide\">SPC Chart Interpretation Guide<\/a><\/li>\n      <li><a href=\"#faq\">\u3088\u304f\u3042\u308b\u8cea\u554f<\/a><\/li>\n    <\/ol>\n  <\/nav>\n\n  <!-- \u2550\u2550\u2550 SECTION 1 \u2550\u2550\u2550 -->\n  <h2 id=\"when-template\">When to Suspect the Template First<\/h2>\n\n  <p>Edge profile excursions have many possible sources \u2014 carrier head membrane wear, polishing pad conditioning state, slurry concentration, platen temperature \u2014 and it is tempting to investigate all of them simultaneously when an excursion appears. A more efficient approach is to first determine whether the pattern has the characteristics of a template-related problem, because template causes have specific and distinctive signatures that distinguish them from other sources before any hardware is changed.<\/p>\n\n  <p>Suspect the template first when any of the following apply:<\/p>\n\n  <ul>\n    <li><strong>The edge profile excursion is wafer-to-wafer reproducible on the same template.<\/strong> Template-related problems appear on every wafer polished by a given template lot because the template&#8217;s dimensional characteristics (EER height, work-hole depth, carrier plate bow) are constant across all wafers from that template. A process-related excursion typically shows more within-lot variation.<\/li>\n    <li><strong>The excursion correlates with a template lot change.<\/strong> If the edge profile degraded after a new template lot was introduced and improved with the previous lot, the new lot has a dimensional non-conformance. This is a template incoming inspection failure, not a process drift.<\/li>\n    <li><strong>Edge rolloff height increases gradually over template cycle count.<\/strong> Backing pad wear is the most common template-related cause of progressive edge rolloff increase and is a predictable, cycle-count-correlated drift that no process recipe adjustment can permanently correct.<\/li>\n    <li><strong>Edge profile is asymmetric \u2014 one side of the wafer shows more rolloff than the other.<\/strong> Asymmetric edge profile is almost never a process cause (process conditions are symmetric by design) and is characteristic of template causes: excessive work-hole clearance (allowing the wafer to shift off-center), carrier plate bow with a directional component, or an EER with non-uniform height around its circumference.<\/li>\n  <\/ul>\n\n  <p>The physics of edge rolloff \u2014 why the polishing pad deflects at the wafer perimeter and how template design controls that deflection \u2014 is covered in depth in our guide to <a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/How-Polishing-Template-Edge-Design-Controls-Wafer-Edge-Profile-Reduces-Edge-Exclusion\/\" target=\"_blank\" class=\"text-link-pill\">edge design and edge exclusion engineering<\/a>. This troubleshooting guide assumes familiarity with that mechanism and focuses on the diagnostic and corrective steps.<\/p>\n\n  <hr class=\"divider\" \/>\n\n  <!-- \u2550\u2550\u2550 SECTION 2 \u2550\u2550\u2550 -->\n  <h2 id=\"diagnostic-flow\">Diagnostic Flowchart: Isolating Edge Profile Root Cause<\/h2>\n\n  <div class=\"flow-chart\">\n    <div class=\"flow-chart-title\">\ud83d\udd0d Edge Profile Excursion \u2014 First-Pass Triage<\/div>\n\n    <div class=\"flow-row\">\n      <div class=\"flow-q\">Is rolloff symmetric around the wafer perimeter?<\/div>\n      <div class=\"flow-arrow\">\u2192<\/div>\n      <div class=\"flow-yes\">YES \u2192 Causes 1, 2, 4, or 5<\/div>\n      <div class=\"flow-arrow\">|<\/div>\n      <div class=\"flow-no\">NO \u2192 Suspect Cause 3 (clearance) or carrier head asymmetry<\/div>\n    <\/div>\n\n    <div class=\"flow-row flow-indent\">\n      <div class=\"flow-q\">Did excursion begin gradually over many cycles?<\/div>\n      <div class=\"flow-arrow\">\u2192<\/div>\n      <div class=\"flow-yes\">YES \u2192 Cause 2: Backing Pad Wear<\/div>\n      <div class=\"flow-arrow\">|<\/div>\n      <div class=\"flow-no\">NO \u2192 Continue<\/div>\n    <\/div>\n\n    <div class=\"flow-row flow-indent\">\n      <div class=\"flow-q\">Did excursion appear suddenly after a new template lot?<\/div>\n      <div class=\"flow-arrow\">\u2192<\/div>\n      <div class=\"flow-yes\">YES \u2192 Cause 1 (no\/small EER) or Cause 4 (bow in new lot)<\/div>\n      <div class=\"flow-arrow\">|<\/div>\n      <div class=\"flow-no\">NO \u2192 Continue<\/div>\n    <\/div>\n\n    <div class=\"flow-row flow-indent\">\n      <div class=\"flow-q\">Is the edge OVER-polished (edge thin, not thick)?<\/div>\n      <div class=\"flow-arrow\">\u2192<\/div>\n      <div class=\"flow-yes\">YES \u2192 Cause 5: EER Over-Correction<\/div>\n      <div class=\"flow-arrow\">|<\/div>\n      <div class=\"flow-no\">NO \u2192 Run template swap test to confirm template cause<\/div>\n    <\/div>\n\n    <div style=\"margin-top:14px; padding: 12px 16px; background: var(--navy); border-radius: 8px; font-size: 13px; color: rgba(255,255,255,.7);\">\n      <span style=\"color: #fdba74; font-weight: 600;\">Template swap test:<\/span> Replace suspect template with a known-good unit. Hold all other parameters constant. If excursion disappears \u2192 template confirmed as root cause. If excursion persists \u2192 investigate carrier head, polishing pad, or slurry.\n    <\/div>\n  <\/div>\n\n  <hr class=\"divider\" \/>\n\n  <!-- \u2550\u2550\u2550 CAUSE 1 \u2550\u2550\u2550 -->\n  <h2 id=\"cause1\">The 5 Template-Related Causes<\/h2>\n\n  <div class=\"cause-card\">\n    <div class=\"cause-card-head\">\n      <div class=\"cause-num c1\">1<\/div>\n      <div class=\"cause-title\">\n        <h3>Absent or Undersized Edge Enhancement Ring<\/h3>\n        <div class=\"cause-sub\">Profile type: Edge high (thick) \/ Rolloff too wide \/ EE zone exceeds spec<\/div>\n      <\/div>\n    <\/div>\n    <div class=\"cause-body\">\n\n      <p>The most common cause of edge profile non-conformance in new template lots is an absent or insufficiently specified EER \u2014 either the template was ordered without an EER when one is required, or the EER geometry (particularly height) was under-specified during the design phase and does not provide enough support to reduce rolloff to the target level.<\/p>\n\n      <p>This cause is distinguished from backing pad wear (Cause 2) by its <em>onset timing<\/em>: an absent or undersized EER produces the same edge profile on Cycle 1 as on Cycle 50. There is no progressive worsening \u2014 the excursion is present from the first wafer polished on the template lot and remains constant throughout the template&#8217;s service life. This &#8220;constant from first cycle&#8221; characteristic is the signature that differentiates an EER geometry deficiency from a wear-related cause.<\/p>\n\n      <div class=\"spc-strip\">\n        <span class=\"spc-label\">Rolloff at 1 mm<\/span>\n        <div class=\"spc-bars\">\n          <div class=\"spc-bar bar-step-jump\"><\/div>\n          <div class=\"spc-bar bar-step-jump\"><\/div>\n          <div class=\"spc-bar bar-step-jump\"><\/div>\n          <div class=\"spc-bar bar-step-jump\"><\/div>\n          <div class=\"spc-bar bar-step-jump\"><\/div>\n          <div class=\"spc-bar bar-step-jump\"><\/div>\n          <div class=\"spc-bar bar-step-jump\"><\/div>\n          <div class=\"spc-bar bar-step-jump\"><\/div>\n        <\/div>\n        <span class=\"spc-note\">Flat at spec violation \u2014 all cycles above UCL from cycle 1<\/span>\n      <\/div>\n\n      <div class=\"diag-grid\">\n        <div class=\"diag-cell signature\">\n          <div class=\"diag-cell-label\">\ud83d\udd34 SPC Signature<\/div>\n          <ul>\n            <li>Rolloff above UCL from first cycle of new lot<\/li>\n            <li>No correlation to cycle count<\/li>\n            <li>Consistent across all wafers in lot<\/li>\n            <li>Previous template lot was within spec<\/li>\n          <\/ul>\n        <\/div>\n        <div class=\"diag-cell isolation\">\n          <div class=\"diag-cell-label\">\ud83d\udd35 Isolation Test<\/div>\n          <ul>\n            <li>Measure EER height on current lot with dial gauge or CMM<\/li>\n            <li>Compare to engineering drawing specification<\/li>\n            <li>Check for EER presence on carrier plate (visual + tactile)<\/li>\n            <li>Run one wafer on previous good template lot as reference<\/li>\n          <\/ul>\n        <\/div>\n        <div class=\"diag-cell solution\">\n          <div class=\"diag-cell-label\">\u2705 Corrective Action<\/div>\n          <ul>\n            <li>If EER absent: reorder with EER specified (provide rolloff target and process conditions)<\/li>\n            <li>If EER height low: request EER height increase \u2014 typical increment 20\u201350 \u00b5m per iteration<\/li>\n            <li>Issue supplier NCR with CMM data for out-of-spec lots<\/li>\n            <li>Add incoming EER height to IQC measurement plan<\/li>\n          <\/ul>\n        <\/div>\n      <\/div>\n\n    <\/div>\n  <\/div>\n\n  <!-- \u2550\u2550\u2550 CAUSE 2 \u2550\u2550\u2550 -->\n  <div class=\"cause-card\">\n    <div class=\"cause-card-head\">\n      <div class=\"cause-num c2\">2<\/div>\n      <div class=\"cause-title\">\n        <h3>Worn Backing Pad \u2014 Cycle-Count-Linked Edge Rolloff Drift<\/h3>\n        <div class=\"cause-sub\">Profile type: Progressive edge rolloff increase \/ TTV drift correlated to cycle count<\/div>\n      <\/div>\n    <\/div>\n    <div class=\"cause-body\">\n\n      <p>Backing pad wear is the single most common template-related cause of edge profile excursions in production. As the backing pad thins under cyclic polishing load, the effective work-hole depth increases \u2014 the wafer recesses progressively deeper below the template face and further from the optimal contact position relative to the polishing pad. This increasing recess amplifies the pad deflection at the wafer edge, gradually widening the rolloff zone and increasing rolloff height with each additional polishing cycle.<\/p>\n\n      <p>The critical diagnostic feature of this cause is its <em>progressive, cycle-count-correlated nature<\/em>. A rolloff SPC chart showing a gradual upward trend over 30\u201380 cycles \u2014 starting within specification and crossing the UCL after extended use \u2014 is the textbook backing pad wear signature. This trend will appear on every template lot in succession if the replacement interval is set too long, making it a systematic process capability issue rather than a one-time lot problem once identified.<\/p>\n\n      <div class=\"spc-strip\">\n        <span class=\"spc-label\">Rolloff at 1 mm<\/span>\n        <div class=\"spc-bars\">\n          <div class=\"spc-bar bar-rise-1\"><\/div>\n          <div class=\"spc-bar bar-rise-2\"><\/div>\n          <div class=\"spc-bar bar-rise-3\"><\/div>\n          <div class=\"spc-bar bar-rise-4\"><\/div>\n          <div class=\"spc-bar bar-rise-5\"><\/div>\n          <div class=\"spc-bar bar-rise-6\"><\/div>\n          <div class=\"spc-bar bar-rise-7\"><\/div>\n          <div class=\"spc-bar bar-rise-8\"><\/div>\n        <\/div>\n        <span class=\"spc-note\">Monotonic upward trend \u2014 crosses UCL at cycle ~60<\/span>\n      <\/div>\n\n      <div class=\"diag-grid\">\n        <div class=\"diag-cell signature\">\n          <div class=\"diag-cell-label\">\ud83d\udd34 SPC Signature<\/div>\n          <ul>\n            <li>Monotonic rolloff increase correlated to cycle count<\/li>\n            <li>Pattern repeats identically on each successive template lot<\/li>\n            <li>Rolloff within spec at cycle 1\u201320, above UCL at cycle 60\u2013100<\/li>\n            <li>TTV also shows gradual increase (linked cause)<\/li>\n          <\/ul>\n        <\/div>\n        <div class=\"diag-cell isolation\">\n          <div class=\"diag-cell-label\">\ud83d\udd35 Isolation Test<\/div>\n          <ul>\n            <li>Measure backing pad thickness with micrometer at 5-cycle intervals<\/li>\n            <li>Plot pad thickness vs. cycle count \u2014 confirm monotonic decrease<\/li>\n            <li>Install new template; verify rolloff returns to Cycle-1 baseline<\/li>\n            <li>Confirm slope of rolloff increase matches pad wear rate<\/li>\n          <\/ul>\n        <\/div>\n        <div class=\"diag-cell solution\">\n          <div class=\"diag-cell-label\">\u2705 Corrective Action<\/div>\n          <ul>\n            <li>Set template replacement trigger at the cycle count where rolloff UCL is first approached \u2014 not after it is crossed<\/li>\n            <li>Specify harder backing pad (Shore A +5\u201310) to slow wear rate at elevated process pressures<\/li>\n            <li>Implement 5-cycle pad thickness SPC as leading indicator ahead of rolloff SPC<\/li>\n            <li>Review process pressure \u2014 over-pressure accelerates pad wear non-linearly<\/li>\n          <\/ul>\n        <\/div>\n      <\/div>\n\n    <\/div>\n  <\/div>\n\n  <!-- \u2550\u2550\u2550 CAUSE 3 \u2550\u2550\u2550 -->\n  <div class=\"cause-card\">\n    <div class=\"cause-card-head\">\n      <div class=\"cause-num c3\">3<\/div>\n      <div class=\"cause-title\">\n        <h3>Excessive Work-Hole Radial Clearance \u2014 Asymmetric Edge Profile<\/h3>\n        <div class=\"cause-sub\">Profile type: Asymmetric rolloff \/ One-sided edge exclusion zone wider than opposite side<\/div>\n      <\/div>\n    <\/div>\n    <div class=\"cause-body\">\n\n      <p>Work-hole radial clearance \u2014 the gap between the wafer outer diameter and the work-hole wall \u2014 controls lateral wafer positioning in the template during polishing. Standard clearance of 0.25\u20130.50 mm provides enough freedom for easy loading while keeping the wafer near-centered. When this clearance is excessive \u2014 from an over-sized work hole, from wafer-to-work-hole diameter mismatch, or from chemical erosion of the work-hole wall in laminate templates \u2014 the wafer can shift off-center under the lateral forces of polishing pad rotation.<\/p>\n\n      <p>An off-center wafer presents different effective annular gaps on opposite sides of the wafer perimeter: the side toward which the wafer has shifted has a smaller gap (less pad deflection, less rolloff), while the opposite side has a larger gap (more pad deflection, more rolloff). This produces the characteristic <em>asymmetric edge profile<\/em> \u2014 one edge of the wafer meets the edge profile specification while the diametrically opposite edge shows excess rolloff. This left-right asymmetry is the definitive diagnostic signature of a clearance problem and is almost never produced by process-related causes, which tend to be rotationally symmetric.<\/p>\n\n      <div class=\"spc-strip\">\n        <span class=\"spc-label\">Rolloff \u2014 left<\/span>\n        <div class=\"spc-bars\">\n          <div class=\"spc-bar bar-asym-lo\"><\/div>\n          <div class=\"spc-bar bar-asym-lo\"><\/div>\n          <div class=\"spc-bar bar-asym-lo\"><\/div>\n          <div class=\"spc-bar bar-asym-lo\"><\/div>\n          <div class=\"spc-bar bar-asym-lo\"><\/div>\n          <div class=\"spc-bar bar-asym-lo\"><\/div>\n          <div class=\"spc-bar bar-asym-lo\"><\/div>\n          <div class=\"spc-bar bar-asym-lo\"><\/div>\n        <\/div>\n        <span class=\"spc-note\">Left edge within spec<\/span>\n      <\/div>\n      <div class=\"spc-strip\">\n        <span class=\"spc-label\">Rolloff \u2014 right<\/span>\n        <div class=\"spc-bars\">\n          <div class=\"spc-bar bar-asym-hi\"><\/div>\n          <div class=\"spc-bar bar-asym-hi\"><\/div>\n          <div class=\"spc-bar bar-asym-hi\"><\/div>\n          <div class=\"spc-bar bar-asym-hi\"><\/div>\n          <div class=\"spc-bar bar-asym-hi\"><\/div>\n          <div class=\"spc-bar bar-asym-hi\"><\/div>\n          <div class=\"spc-bar bar-asym-hi\"><\/div>\n          <div class=\"spc-bar bar-asym-hi\"><\/div>\n        <\/div>\n        <span class=\"spc-note\">Right edge above UCL \u2014 asymmetric pattern<\/span>\n      <\/div>\n\n      <div class=\"diag-grid\">\n        <div class=\"diag-cell signature\">\n          <div class=\"diag-cell-label\">\ud83d\udd34 SPC Signature<\/div>\n          <ul>\n            <li>Rolloff consistently higher on one side of wafer<\/li>\n            <li>Site map shows asymmetric EE zone \u2014 wider on one side only<\/li>\n            <li>Effect consistent across all wafers in lot; not random<\/li>\n            <li>May correlate to specific polisher rotation direction<\/li>\n          <\/ul>\n        <\/div>\n        <div class=\"diag-cell isolation\">\n          <div class=\"diag-cell-label\">\ud83d\udd35 Isolation Test<\/div>\n          <ul>\n            <li>Measure work-hole diameter with calibrated pin gauge<\/li>\n            <li>Compare to wafer OD + spec clearance (should be +0.25\u20130.50 mm)<\/li>\n            <li>Inspect work-hole wall for chemical erosion (laminate templates)<\/li>\n            <li>Rotate wafer 180\u00b0 in work hole for one lot \u2014 check if asymmetry follows wafer or stays with template orientation<\/li>\n          <\/ul>\n        <\/div>\n        <div class=\"diag-cell solution\">\n          <div class=\"diag-cell-label\">\u2705 Corrective Action<\/div>\n          <ul>\n            <li>If work hole over-sized: replace template lot with correct clearance<\/li>\n            <li>If erosion of laminate wall: switch to CXT-grade template (no chemical attack) or reduce slurry aggressiveness<\/li>\n            <li>Add work-hole diameter to IQC pin-gauge measurement plan<\/li>\n            <li>For III-V substrates: tighten clearance spec to 0.15\u20130.25 mm<\/li>\n          <\/ul>\n        <\/div>\n      <\/div>\n\n    <\/div>\n  <\/div>\n\n  <!-- \u2550\u2550\u2550 CAUSE 4 \u2550\u2550\u2550 -->\n  <div class=\"cause-card\">\n    <div class=\"cause-card-head\">\n      <div class=\"cause-num c4\">4<\/div>\n      <div class=\"cause-title\">\n        <h3>Carrier Plate Bow \u2014 Long-Range Edge and Center Profile Gradient<\/h3>\n        <div class=\"cause-sub\">Profile type: One-side-thick \/ Systematic TTV gradient \/ SFQR degradation across wafer diameter<\/div>\n      <\/div>\n    <\/div>\n    <div class=\"cause-body\">\n\n      <p>Carrier plate bow is a low-spatial-frequency flatness error in the template&#8217;s carrier plate: a gradual deviation from perfect flatness across the working surface that introduces a systematic pressure gradient across the wafer diameter. A bowed carrier plate does not produce the sharp edge rolloff profile associated with Causes 1\u20133; instead, it creates a <em>gradual thickness gradient<\/em> that slopes from one side of the wafer to the other (for directional bow) or from center to edge (for radially symmetric bowl or dome bow).<\/p>\n\n      <p>Carrier plate bow manifests in edge profile data as a site-level SFQR degradation pattern where sites near the high-pressure side of the bow are thinner than nominal and sites near the low-pressure side are thicker. The edge profile measurement at the wafer perimeter on the high-bow side shows apparent over-polishing (thin edge), while the low-bow side shows apparent under-polishing (thick edge). This pattern is frequently misdiagnosed as an EER problem \u2014 and the misdiagnosis leads to EER height adjustments that cannot correct a bow-induced profile because the bow operates at a much longer spatial wavelength than EER correction can address.<\/p>\n\n      <div class=\"spc-strip\">\n        <span class=\"spc-label\">Thickness \u2014 center<\/span>\n        <div class=\"spc-bars\">\n          <div class=\"spc-bar bar-flat\"><\/div>\n          <div class=\"spc-bar bar-flat\"><\/div>\n          <div class=\"spc-bar bar-flat\"><\/div>\n          <div class=\"spc-bar bar-flat\"><\/div>\n          <div class=\"spc-bar bar-flat\"><\/div>\n          <div class=\"spc-bar bar-flat\"><\/div>\n          <div class=\"spc-bar bar-flat\"><\/div>\n          <div class=\"spc-bar bar-flat\"><\/div>\n        <\/div>\n        <span class=\"spc-note\">Center within spec<\/span>\n      <\/div>\n      <div class=\"spc-strip\">\n        <span class=\"spc-label\">Thickness \u2014 edge N<\/span>\n        <div class=\"spc-bars\">\n          <div class=\"spc-bar bar-asym-lo\"><\/div>\n          <div class=\"spc-bar bar-asym-lo\"><\/div>\n          <div class=\"spc-bar bar-asym-lo\"><\/div>\n          <div class=\"spc-bar bar-asym-lo\"><\/div>\n          <div class=\"spc-bar bar-asym-lo\"><\/div>\n          <div class=\"spc-bar bar-asym-lo\"><\/div>\n          <div class=\"spc-bar bar-asym-lo\"><\/div>\n          <div class=\"spc-bar bar-asym-lo\"><\/div>\n        <\/div>\n        <span class=\"spc-note\">North edge thin (over-polished)<\/span>\n      <\/div>\n      <div class=\"spc-strip\">\n        <span class=\"spc-label\">Thickness \u2014 edge S<\/span>\n        <div class=\"spc-bars\">\n          <div class=\"spc-bar bar-asym-hi\"><\/div>\n          <div class=\"spc-bar bar-asym-hi\"><\/div>\n          <div class=\"spc-bar bar-asym-hi\"><\/div>\n          <div class=\"spc-bar bar-asym-hi\"><\/div>\n          <div class=\"spc-bar bar-asym-hi\"><\/div>\n          <div class=\"spc-bar bar-asym-hi\"><\/div>\n          <div class=\"spc-bar bar-asym-hi\"><\/div>\n          <div class=\"spc-bar bar-asym-hi\"><\/div>\n        <\/div>\n        <span class=\"spc-note\">South edge thick \u2014 gradient pattern consistent with bow<\/span>\n      <\/div>\n\n      <div class=\"diag-grid\">\n        <div class=\"diag-cell signature\">\n          <div class=\"diag-cell-label\">\ud83d\udd34 SPC Signature<\/div>\n          <ul>\n            <li>Thickness gradient across wafer diameter \u2014 not sharp rolloff<\/li>\n            <li>Opposite edges show opposite deviations (one thin, one thick)<\/li>\n            <li>SFQR degraded at sites near wafer diameter extremes<\/li>\n            <li>Pattern consistent from cycle 1 \u2014 not progressive<\/li>\n          <\/ul>\n        <\/div>\n        <div class=\"diag-cell isolation\">\n          <div class=\"diag-cell-label\">\ud83d\udd35 Isolation Test<\/div>\n          <ul>\n            <li>Measure carrier plate bow with CMM \u2014 compare to spec (\u226410 \u00b5m standard, \u22645 \u00b5m advanced)<\/li>\n            <li>Rotate carrier plate 90\u00b0 relative to polisher orientation for one lot \u2014 check if thickness gradient rotates with plate<\/li>\n            <li>Replace with confirmed flat carrier; check if gradient disappears<\/li>\n          <\/ul>\n        <\/div>\n        <div class=\"diag-cell solution\">\n          <div class=\"diag-cell-label\">\u2705 Corrective Action<\/div>\n          <ul>\n            <li>Add carrier plate bow to IQC CMM measurement plan (every incoming lot)<\/li>\n            <li>Tighten bow specification to \u22645 \u00b5m for advanced-node applications<\/li>\n            <li>Return out-of-spec lots to supplier with CMM data<\/li>\n            <li>For CXT-grade templates: verify machining temperature control; thermal distortion during machining is primary CXT bow source<\/li>\n          <\/ul>\n        <\/div>\n      <\/div>\n\n    <\/div>\n  <\/div>\n\n  <!-- \u2550\u2550\u2550 CAUSE 5 \u2550\u2550\u2550 -->\n  <div class=\"cause-card\">\n    <div class=\"cause-card-head\">\n      <div class=\"cause-num c5\">5<\/div>\n      <div class=\"cause-title\">\n        <h3>EER Height Over-Correction \u2014 Edge Thin (Over-Polished Perimeter)<\/h3>\n        <div class=\"cause-sub\">Profile type: Edge thin \/ Negative rolloff \/ Edge exclusion zone defined by over-polishing rather than under-polishing<\/div>\n      <\/div>\n    <\/div>\n    <div class=\"cause-body\">\n\n      <p>Over-correction is the less common but equally problematic opposite of Cause 1. An EER that is too tall provides excessive mechanical support to the polishing pad in the annular zone adjacent to the wafer edge, increasing local contact pressure above the nominal value and removing more material at the wafer perimeter than at the center. The result is an edge that is thinner than the wafer body \u2014 an &#8220;edge thin&#8221; or &#8220;negative rolloff&#8221; condition where the polished surface dips at the perimeter rather than rising.<\/p>\n\n      <p>Edge thin is most commonly introduced during EER qualification iterations when the height is increased too aggressively between iterations without sufficient process data to guide the increment size. It also occurs when an EER template qualified at one process pressure is run at a higher pressure \u2014 the higher pressure increases the EER&#8217;s effective support force, which was calibrated for a lower-pressure condition and now over-corrects. EER over-correction produces a characteristically &#8220;bathtub&#8221; edge profile shape \u2014 flat body, thin annular zone at 1\u20133 mm from edge, transitioning to the target thickness at the very edge.<\/p>\n\n      <div class=\"spc-strip\">\n        <span class=\"spc-label\">Thickness \u2014 body<\/span>\n        <div class=\"spc-bars\">\n          <div class=\"spc-bar bar-flat\"><\/div>\n          <div class=\"spc-bar bar-flat\"><\/div>\n          <div class=\"spc-bar bar-flat\"><\/div>\n          <div class=\"spc-bar bar-flat\"><\/div>\n          <div class=\"spc-bar bar-flat\"><\/div>\n          <div class=\"spc-bar bar-flat\"><\/div>\n          <div class=\"spc-bar bar-flat\"><\/div>\n          <div class=\"spc-bar bar-flat\"><\/div>\n        <\/div>\n        <span class=\"spc-note\">Wafer body at target<\/span>\n      <\/div>\n      <div class=\"spc-strip\">\n        <span class=\"spc-label\">Thickness \u2014 1mm edge<\/span>\n        <div class=\"spc-bars\">\n          <div class=\"spc-bar bar-asym-lo\"><\/div>\n          <div class=\"spc-bar bar-asym-lo\"><\/div>\n          <div class=\"spc-bar bar-asym-lo\"><\/div>\n          <div class=\"spc-bar bar-asym-lo\"><\/div>\n          <div class=\"spc-bar bar-asym-lo\"><\/div>\n          <div class=\"spc-bar bar-asym-lo\"><\/div>\n          <div class=\"spc-bar bar-asym-lo\"><\/div>\n          <div class=\"spc-bar bar-asym-lo\"><\/div>\n        <\/div>\n        <span class=\"spc-note\">Edge zone below LCL \u2014 over-polished &#8220;bathtub&#8221; profile<\/span>\n      <\/div>\n\n      <div class=\"diag-grid\">\n        <div class=\"diag-cell signature\">\n          <div class=\"diag-cell-label\">\ud83d\udd34 SPC Signature<\/div>\n          <ul>\n            <li>Thickness at 1\u20132 mm from edge below LCL (not above UCL)<\/li>\n            <li>&#8220;Bathtub&#8221; edge shape on cross-section profile<\/li>\n            <li>Pattern constant from cycle 1 \u2014 not progressive<\/li>\n            <li>Often introduced at transition to a new EER-equipped template lot<\/li>\n          <\/ul>\n        <\/div>\n        <div class=\"diag-cell isolation\">\n          <div class=\"diag-cell-label\">\ud83d\udd35 Isolation Test<\/div>\n          <ul>\n            <li>Confirm EER is present and measure height (should be above nominal)<\/li>\n            <li>Check if process pressure changed since EER was last qualified<\/li>\n            <li>Run one lot on previous EER template lot \u2014 check if edge-thin disappears<\/li>\n          <\/ul>\n        <\/div>\n        <div class=\"diag-cell solution\">\n          <div class=\"diag-cell-label\">\u2705 Corrective Action<\/div>\n          <ul>\n            <li>Reduce EER height by 20\u201340 \u00b5m in next template order<\/li>\n            <li>If caused by pressure increase: re-qualify EER at new nominal pressure before production use<\/li>\n            <li>For future iterations: use 20 \u00b5m EER height increments \u2014 smaller steps reduce over-correction risk<\/li>\n            <li>Document process pressure as part of EER geometry records<\/li>\n          <\/ul>\n        <\/div>\n      <\/div>\n\n    <\/div>\n  <\/div>\n\n  <!-- \u2550\u2550\u2550 SECTION 8 \u2550\u2550\u2550 -->\n  <h2 id=\"non-template\">When the Problem Is Not the Template<\/h2>\n\n  <p>The template swap test is the definitive decision point. If replacing the suspect template with a confirmed-good unit does not change the edge profile excursion, the template is not the root cause. The most common non-template causes of edge profile problems that initially present with template-like characteristics are:<\/p>\n\n  <div class=\"table-wrap\">\n    <table>\n      <thead>\n        <tr>\n          <th>Non-Template Cause<\/th>\n          <th>How It Mimics a Template Problem<\/th>\n          <th>Distinguishing Feature<\/th>\n        <\/tr>\n      <\/thead>\n      <tbody>\n        <tr>\n          <td><strong>Carrier head retaining ring wear<\/strong><\/td>\n          <td>Produces edge rolloff similar to EER deficiency; wafer-to-wafer reproducible<\/td>\n          <td>Persists after template swap; resolved by retaining ring replacement<\/td>\n        <\/tr>\n        <tr class=\"row-warn\">\n          <td><strong>Polishing pad glazing \/ under-conditioning<\/strong><\/td>\n          <td>Increases rolloff width; progressive over time<\/td>\n          <td>Responds to pad conditioning recipe changes; affects all carrier positions<\/td>\n        <\/tr>\n        <tr>\n          <td><strong>Slurry flow non-uniformity<\/strong><\/td>\n          <td>Can produce asymmetric edge profile similar to Cause 3<\/td>\n          <td>Changes with slurry injection point; varies with rotation speed<\/td>\n        <\/tr>\n        <tr>\n          <td><strong>Platen temperature gradient<\/strong><\/td>\n          <td>Produces radially asymmetric removal rate similar to carrier plate bow<\/td>\n          <td>Correlates to platen temperature map; corrected by temperature control adjustment<\/td>\n        <\/tr>\n        <tr class=\"row-highlight\">\n          <td><strong>Carrier head membrane non-uniformity<\/strong><\/td>\n          <td>Produces pressure non-uniformity at wafer scale; can present as edge-high on one sector<\/td>\n          <td>Pattern rotates with carrier head; resolved by membrane replacement or re-inflation<\/td>\n        <\/tr>\n      <\/tbody>\n    <\/table>\n  <\/div>\n\n  <hr class=\"divider\" \/>\n\n  <!-- \u2550\u2550\u2550 SECTION 9 \u2550\u2550\u2550 -->\n  <h2 id=\"spc-guide\">SPC Chart Interpretation Quick Reference<\/h2>\n\n  <p>The following table summarizes the SPC pattern most strongly associated with each of the five template causes, for use as a rapid reference during production monitoring. The &#8220;onset&#8221; column is the most efficient first discriminator when reviewing a new edge profile excursion.<\/p>\n\n  <div class=\"table-wrap\">\n    <table>\n      <thead>\n        <tr>\n          <th>Cause<\/th>\n          <th>Onset<\/th>\n          <th>Pattern Type<\/th>\n          <th>Spatial Character<\/th>\n          <th>Progressive?<\/th>\n        <\/tr>\n      <\/thead>\n      <tbody>\n        <tr>\n          <td><strong>1 \u2014 Absent \/ small EER<\/strong><\/td>\n          <td>Cycle 1 of new lot<\/td>\n          <td>Flat above UCL<\/td>\n          <td>Symmetric \u2014 all edges high<\/td>\n          <td>No<\/td>\n        <\/tr>\n        <tr class=\"row-warn\">\n          <td><strong>2 \u2014 Pad wear<\/strong><\/td>\n          <td>Gradual rise over cycles<\/td>\n          <td>Monotonic upward trend<\/td>\n          <td>Symmetric \u2014 all edges rise equally<\/td>\n          <td>Yes \u2014 linear with cycles<\/td>\n        <\/tr>\n        <tr>\n          <td><strong>3 \u2014 Excessive clearance<\/strong><\/td>\n          <td>Any cycle \u2014 may be new lot or develop with wear<\/td>\n          <td>Asymmetric \u2014 one side high<\/td>\n          <td>180\u00b0 asymmetry \u2014 opposite edges differ<\/td>\n          <td>No (unless erosion-driven)<\/td>\n        <\/tr>\n        <tr>\n          <td><strong>4 \u2014 Carrier plate bow<\/strong><\/td>\n          <td>Cycle 1 of new lot<\/td>\n          <td>Gradient \u2014 one-thick, one-thin<\/td>\n          <td>Directional across diameter<\/td>\n          <td>No<\/td>\n        <\/tr>\n        <tr class=\"row-highlight\">\n          <td><strong>5 \u2014 EER over-correction<\/strong><\/td>\n          <td>Cycle 1 of new lot<\/td>\n          <td>Edge zone below LCL<\/td>\n          <td>Symmetric \u2014 &#8220;bathtub&#8221; at perimeter<\/td>\n          <td>No<\/td>\n        <\/tr>\n      <\/tbody>\n    <\/table>\n  <\/div>\n\n  <div class=\"callout tip\">\n    <span class=\"callout-icon\">\ud83d\udca1<\/span>\n    <div class=\"callout-body\">\n      <strong>Set Up a Template-Specific SPC Stream<\/strong>\n      The most effective implementation of this diagnostic framework is a dedicated SPC stream for template-lot-specific edge profile data \u2014 meaning each template lot gets its own SPC chart rather than all data going into a single process chart. This makes the &#8220;constant from cycle 1 vs. progressive&#8221; pattern immediately visible: a new lot that starts above UCL from its first data point is obvious in a lot-specific chart but may be obscured in a combined process chart if the previous lot ended the spec period in good condition.\n    <\/div>\n  <\/div>\n\n  <!-- Related articles -->\n  <div class=\"related-box\">\n    <h3>\ud83d\udcd6 Related Technical Articles<\/h3>\n    <p>Build the complete picture with these supporting engineering guides:<\/p>\n    <div class=\"related-links\">\n      <a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/Polishing-Templates-for-Semiconductor-Silicon-Wafer-Processing\/\" target=\"_blank\">Polishing Templates: Complete Guide<\/a>\n      <a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/How-Polishing-Template-Edge-Design-Controls-Wafer-Edge-Profile-Reduces-Edge-Exclusion\/\" target=\"_blank\">Edge Profile &amp; EER Design<\/a>\n      <a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/Role-of-Polishing-Templates-in-CMP-How-Fixture-Design-Impacts-Wafer-Flatness\/\" target=\"_blank\">Templates in CMP &amp; Flatness<\/a>\n      <a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/How-to-Extend-Polishing-Template-Lifespan-Best-Practices-for-Semiconductor-Fabs\/\" target=\"_blank\">\u30c6\u30f3\u30d7\u30ec\u30fc\u30c8\u5bff\u547d\u306e\u5ef6\u9577<\/a>\n      <a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/Contamination-Control-in-Polishing-Templates-Clean-Room-Assembly-Particle-Prevention\/\" target=\"_blank\">Contamination Control<\/a>\n      <a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/How-to-Specify-a-Polishing-Template-6-Parameters-Engineers-Must-Define\/\" target=\"_blank\">6\u30d1\u30e9\u30e1\u30fc\u30bf\u4ed5\u69d8\u30ac\u30a4\u30c9<\/a>\n    <\/div>\n  <\/div>\n\n  <hr class=\"divider\" \/>\n\n  <!-- \u2550\u2550\u2550 FAQ \u2550\u2550\u2550 -->\n  <h2 id=\"faq\">\u3088\u304f\u3042\u308b\u8cea\u554f<\/h2>\n\n  <div class=\"faq-item\">\n    <div class=\"faq-q\">How do I know if my wafer edge profile problem is template-related?<\/div>\n    <div class=\"faq-a\">Three characteristics identify template-related edge profile problems: the excursion is reproducible across all wafers from the same template lot; it changes (improves or disappears) when the template is swapped for a known-good replacement while all other parameters are held constant; and it often correlates with template cycle count (progressive problems) or new template lot introduction (dimensional non-conformance). The definitive test is always a controlled template swap \u2014 swap the suspect template, run identical process conditions, and compare edge profiles. If the excursion disappears, the template is the root cause.<\/div>\n  <\/div>\n\n  <div class=\"faq-item\">\n    <div class=\"faq-q\">What causes wafer edge rolloff in polishing?<\/div>\n    <div class=\"faq-a\">Edge rolloff occurs when the polishing pad deflects downward at the wafer perimeter, where it transitions from the rigid wafer-supported zone to the unsupported annular gap between the wafer and the work-hole wall. This deflection reduces local contact pressure, lowering material removal rate at the edge and leaving the perimeter thicker than the wafer body. Template-related contributions include absent or undersized EER (no mechanical support for the pad in the rolloff zone), worn backing pad (increased work-hole depth amplifies pad deflection), excessive radial clearance (off-center wafer creates uneven gap), and carrier plate bow (long-range pressure gradient that superimposes on the rolloff profile).<\/div>\n  <\/div>\n\n  <div class=\"faq-item\">\n    <div class=\"faq-q\">What is the difference between edge rolloff and edge upturn?<\/div>\n    <div class=\"faq-a\">Edge rolloff (edge high or edge thick) means the wafer is thicker near its perimeter than at the center \u2014 the polishing pad deflects away from the wafer at the edge, reducing removal rate and leaving material behind. The opposite condition \u2014 edge thin, or over-polished edge \u2014 is caused by an EER that is too tall, creating excess contact pressure at the perimeter and removing more material there than at the center. This produces a &#8220;bathtub&#8221; profile. Both conditions create an edge exclusion zone, but they require opposite corrective actions: rolloff requires increasing EER height, and edge thin requires decreasing it.<\/div>\n  <\/div>\n\n  <div class=\"faq-item\">\n    <div class=\"faq-q\">How often should polishing templates be replaced to maintain edge profile performance?<\/div>\n    <div class=\"faq-a\">Replacement interval is determined empirically by monitoring edge profile rolloff height as a function of template cycle count on a template-lot-specific SPC chart. For silicon SSP at 3\u20135 psi, edge profile typically begins degrading measurably at cycle 60\u2013100 as the backing pad wears. For SiC CMP at higher pressures, degradation begins earlier (cycle 40\u201370). Set the replacement trigger at the cycle count where rolloff height approaches \u2014 not crosses \u2014 the UCL for your edge profile specification. Backing pad thickness measurement at 5-cycle intervals provides a leading indicator 10\u201315 cycles ahead of the rolloff excursion.<\/div>\n  <\/div>\n\n  <!-- CTA -->\n  <div class=\"cta-banner\">\n    <h2>Still Seeing Edge Profile Issues? Let&#8217;s Diagnose Together.<\/h2>\n    <p>Share your edge profile SPC data, template cycle count, and current template specification \u2014 our engineering team will identify the most likely cause and recommend a targeted corrective action, at no charge.<\/p>\n    <a href=\"https:\/\/jeez-semicon.com\/ja\/contact\/\" class=\"cta-btn\" target=\"_blank\">\n      \u304a\u898b\u7a4d\u3082\u308a\u306f\u3053\u3061\u3089 \u2192 \u304a\u554f\u3044\u5408\u308f\u305b\n    <\/a>\n  <\/div>\n\n  <a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/Polishing-Templates-for-Semiconductor-Silicon-Wafer-Processing\/\" target=\"_blank\" class=\"back-to-pillar\">\n    Back to Polishing Templates: Complete Guide\n  <\/a>\n\n<\/div>\n<\/body>\n<\/html>","protected":false},"excerpt":{"rendered":"<p>Troubleshooting Guide Before adjusting your process recipe, check the template. Five specific template conditions account for the majority of edge profile excursions in production \u2014 and each one has a  &#8230;<\/p>","protected":false},"author":1,"featured_media":1691,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[9,59],"tags":[],"class_list":["post-1667","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-blog","category-industry"],"acf":[],"_links":{"self":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts\/1667","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/comments?post=1667"}],"version-history":[{"count":2,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts\/1667\/revisions"}],"predecessor-version":[{"id":1669,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts\/1667\/revisions\/1669"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/media\/1691"}],"wp:attachment":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/media?parent=1667"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/categories?post=1667"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/tags?post=1667"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}