{"id":1779,"date":"2026-04-07T15:55:26","date_gmt":"2026-04-07T07:55:26","guid":{"rendered":"https:\/\/jeez-semicon.com\/?p=1779"},"modified":"2026-04-07T16:29:14","modified_gmt":"2026-04-07T08:29:14","slug":"cmp-material-removal-rate-and-pad-parameters-a-quantitative-guide","status":"publish","type":"post","link":"https:\/\/jeez-semicon.com\/ja\/blog\/cmp-material-removal-rate-and-pad-parameters-a-quantitative-guide\/","title":{"rendered":"CMP Material Removal Rate and Pad Parameters: A Quantitative Guide"},"content":{"rendered":"<!-- ============================================================\n     CLUSTER 8 \u2014 CMP Material Removal Rate and Pad Parameters\n     Jizhi Electronic Technology Co., Ltd.\n     jeez-semicon.com  |  April 2026\n     URL: \/blog\/CMP-Material-Removal-Rate-and-Pad-Parameters\n     ============================================================ -->\n<style>\n@import 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rgba(255,255,255,.6);margin-left:12px}\n.jz-btn-outline:hover{background:rgba(255,255,255,.12);color:#fff}\n.jz-faq{margin:28px 0}\n.jz-faq-item{border:1px solid var(--c-border);border-radius:var(--radius);margin-bottom:12px;overflow:hidden;background:var(--c-surface)}\n.jz-faq-q{padding:16px 20px;font-weight:600;font-size:15px;color:var(--c-primary-dark);display:flex;justify-content:space-between;align-items:center}\n.jz-faq-q::after{content:'+';font-size:20px;font-weight:300;color:var(--c-accent);flex-shrink:0}\n.jz-faq-a{padding:0 20px 16px;font-size:15px;color:#3a4255;line-height:1.75}\n@media(max-width:640px){.jz-hero{padding:36px 24px 32px}.jz-cta-banner{padding:32px 22px}.jz-related{padding:24px 18px}.jz-btn-outline{margin-left:0;margin-top:10px;display:inline-block}}\n<\/style>\n\n<div class=\"jz-art\">\n<a class=\"jz-back\" href=\"https:\/\/jeez-semicon.com\/ja\/blog\/CMP-Polishing-Pads-The-Complete-Guide\/\" target=\"_blank\">Back to CMP Polishing Pads: The Complete Guide<\/a>\n\n<div class=\"jz-hero\">\n  <div class=\"jz-hero-kicker\">Jizhi Electronic Technology \u2014 Process Series<\/div>\n  <p class=\"jz-hero-lead\">A data-driven analysis of how CMP polishing pad properties \u2014 hardness, porosity, groove geometry, and surface texture \u2014 determine material removal rate, process window width, and wafer-to-wafer repeatability in semiconductor manufacturing.<\/p>\n  <div class=\"jz-hero-meta\">\n    <span>\ud83d\udcc5 April 2026<\/span>\n    <span>\u23f1 14 min read<\/span>\n    <span>\ud83c\udfed Jizhi Electronic Technology Co., Ltd.<\/span>\n  <\/div>\n<\/div>\n\n<div class=\"jz-tags\">\n  <span class=\"jz-tag\">CMP Removal Rate<\/span>\n  <span class=\"jz-tag\">MRR<\/span>\n  <span class=\"jz-tag\">Preston Equation<\/span>\n  <span class=\"jz-tag\">Pad Parameters<\/span>\n  <span class=\"jz-tag\">Kp Coefficient<\/span>\n  <span class=\"jz-tag\">Process Window<\/span>\n  <span class=\"jz-tag\">Within-Wafer Uniformity<\/span>\n<\/div>\n\n<div class=\"jz-trust\">\n  <div class=\"jz-trust-badge\">Lab<br>Data<\/div>\n  <div class=\"jz-trust-text\"><strong>Written by Jizhi Electronic Technology Co., Ltd.<\/strong> \u2014 CMP pad manufacturer with in-house process characterization laboratory. MRR data and process relationships in this article are drawn from our lab measurements on production-representative pad-slurry combinations. April 2026.<\/div>\n<\/div>\n\n<div class=\"jz-toc\">\n  <div class=\"jz-toc-title\">\u76ee\u6b21<\/div>\n  <ol>\n    <li><a href=\"#mrr-defined\">MRR: Definition and Measurement<\/a><\/li>\n    <li><a href=\"#preston\">The Preston Equation in Depth<\/a><\/li>\n    <li><a href=\"#kp-breakdown\">What Determines Kp: Pad Contributions<\/a><\/li>\n    <li><a href=\"#pressure-velocity\">Pressure and Velocity: The Primary Knobs<\/a><\/li>\n    <li><a href=\"#pad-hardness-mrr\">Pad Hardness vs. MRR: Quantitative Relationship<\/a><\/li>\n    <li><a href=\"#porosity-mrr\">Porosity and Slurry Uptake vs. MRR<\/a><\/li>\n    <li><a href=\"#groove-mrr\">Groove Geometry vs. MRR Uniformity<\/a><\/li>\n    <li><a href=\"#mrr-stability\">MRR Stability Over Pad Lifetime<\/a><\/li>\n    <li><a href=\"#process-window\">Process Window Engineering<\/a><\/li>\n    <li><a href=\"#faq\">FAQ<\/a><\/li>\n  <\/ol>\n<\/div>\n\n<p>Material removal rate (MRR) is the central productivity metric of every CMP process. It determines polishing time per wafer, tool throughput, and cost-per-wafer. Yet MRR is not a fixed property of a pad-slurry combination \u2014 it is a complex function of pad physical properties, process recipe parameters, wafer film type, and process history (pad age and conditioning state). Understanding what drives MRR quantitatively allows process engineers to predict recipe changes, diagnose yield excursions, and optimize total cost of ownership.<\/p>\n\n<p>This guide builds from the Preston equation framework to a practical, quantitative understanding of how every major pad parameter contributes to MRR. For the mechanistic context on how pads generate material removal, see first: <a class=\"jz-link-chip\" href=\"https:\/\/jeez-semicon.com\/ja\/blog\/How-CMP-Polishing-Pads-Work\/\" target=\"_blank\">How CMP Polishing Pads Work<\/a>.<\/p>\n\n<div class=\"jz-stats\">\n  <div class=\"jz-stat\"><div class=\"jz-stat-num\">500\u20133,000<\/div><div class=\"jz-stat-label\">\u00c5\/min \u2014 typical MRR range for oxide CMP with hard pad + ceria slurry<\/div><\/div>\n  <div class=\"jz-stat\"><div class=\"jz-stat-num\">200\u2013800<\/div><div class=\"jz-stat-label\">\u00c5\/min \u2014 typical MRR range for Cu CMP Step 1 with soft pad<\/div><\/div>\n  <div class=\"jz-stat\"><div class=\"jz-stat-num\">10\u207b\u2078<\/div><div class=\"jz-stat-label\">Order of magnitude of Preston Kp (Pa\u207b\u00b9) for oxide CMP<\/div><\/div>\n  <div class=\"jz-stat\"><div class=\"jz-stat-num\">&lt;5%<\/div><div class=\"jz-stat-label\">CV target for MRR across a well-managed pad lifetime<\/div><\/div>\n<\/div>\n\n<h2 id=\"mrr-defined\">1. MRR: Definition and How It Is Measured<\/h2>\n<p>Material removal rate in CMP is defined as the thickness of film removed from the wafer surface per unit polishing time, expressed in \u00e5ngstr\u00f6ms per minute (\u00c5\/min) or nanometers per minute (nm\/min). It is measured by comparing pre-polish and post-polish film thickness at multiple points across the wafer using a non-contact optical metrology tool (reflectometer or ellipsometer). The mean removal rate is calculated as: MRR = \u0394Thickness \/ PolishTime, where \u0394Thickness is the mean change in film thickness across the measurement sites and PolishTime is the elapsed polishing time in minutes.<\/p>\n\n<p>Accurate MRR measurement requires consistent pre-polish film thickness, consistent recipe parameters, and a measurement recipe that samples enough sites to give a representative mean (typically 49- or 121-point wafer maps are used). MRR should be measured and logged for every monitor wafer in the conditioning and production sequence \u2014 it is the primary real-time indicator of pad health.<\/p>\n\n<h2 id=\"preston\">2. The Preston Equation in Depth<\/h2>\n\n<div class=\"jz-equation\">\n  <div class=\"jz-equation-formula\">MRR = K<sub>p<\/sub> \u00d7 P \u00d7 V<\/div>\n  <div class=\"jz-equation-caption\">\n    <strong>MRR<\/strong> (\u00c5\/min or nm\/min) &nbsp;|&nbsp; <strong>K<sub>p<\/sub><\/strong> = Preston coefficient (Pa\u207b\u00b9 \u2014 encapsulates all pad + slurry material properties) &nbsp;|&nbsp; <strong>P<\/strong> = Applied pressure (Pa or psi) &nbsp;|&nbsp; <strong>V<\/strong> = Relative velocity between pad and wafer (m\/s)\n  <\/div>\n<\/div>\n\n<p>The Preston equation was originally derived empirically for glass optical polishing in 1927 and adapted to CMP in the 1990s. It captures the first-order behavior of material removal in CMP with remarkable accuracy across a wide operating range. The key insight is that MRR scales linearly with the product P \u00d7 V \u2014 the specific polishing power delivered to the wafer surface per unit area. The Preston coefficient Kp is the proportionality constant that converts specific power to removal rate.<\/p>\n\n<h3>Calculating Velocity in a CMP Tool<\/h3>\n<p>On a rotary CMP tool, the relative velocity V between pad and wafer is not uniform \u2014 it varies with radial position on the wafer. The mean relative velocity at a wafer point at radius r from the wafer center, on a tool with platen angular velocity \u03c9\u2081 and carrier angular velocity \u03c9\u2082, is approximately:<\/p>\n\n<div style=\"background:#f0f4ff;border:1px solid #c8d9f5;border-radius:8px;padding:16px 22px;margin:20px 0;font-family:'IBM Plex Mono',monospace;font-size:14px;color:#1e2435\">\n  V(r) \u2248 |\u03c9\u2081 \u2212 \u03c9\u2082| \u00d7 r_platen_center + contributions from carrier geometry\n<\/div>\n\n<p>In practice, the velocity profile non-uniformity across the wafer is one driver of within-wafer MRR variation \u2014 the wafer edge (larger r from the platen center) experiences higher relative velocity and therefore higher MRR in a simple Preston model. This is one reason that edge-center uniformity is always a concern in large-wafer CMP and why both platen and carrier RPM must be optimized together.<\/p>\n\n<h2 id=\"kp-breakdown\">3. What Determines Kp: Pad Contributions Broken Down<\/h2>\n<p>The Preston coefficient Kp is the most information-dense parameter in CMP \u2014 it encodes all material system properties into a single number. Understanding what pad properties contribute to Kp allows engineers to predict directional MRR changes when pad specifications change.<\/p>\n\n<div class=\"jz-table-wrap\">\n  <table class=\"jz-table\">\n    <thead><tr><th>Pad Property<\/th><th>Direction of Kp Change<\/th><th>Mechanism<\/th><th>Typical Magnitude of Effect<\/th><\/tr><\/thead>\n    <tbody>\n      <tr><td><strong>Hardness \u2191 (Shore D)<\/strong><\/td><td class=\"win\">Kp \u2191<\/td><td>Stiffer asperities generate higher local contact stress, increasing abrasive engagement force<\/td><td>~8\u201315% per 10 Shore D units<\/td><\/tr>\n      <tr><td><strong>Asperity height (Ra) \u2191<\/strong><\/td><td class=\"win\">Kp \u2191<\/td><td>Taller asperities engage more abrasive particles per unit contact area<\/td><td>~5\u201312% per \u00b5m Ra change<\/td><\/tr>\n      <tr><td><strong>Pore density \u2191<\/strong><\/td><td class=\"win\">Kp \u2191 (modest)<\/td><td>More pore-resident slurry delivered to contact interface; higher abrasive particle density at interface<\/td><td>~3\u20138%<\/td><\/tr>\n      <tr><td><strong>Groove pitch \u2193 (finer)<\/strong><\/td><td class=\"win\">Kp \u2191 (uniformity improvement)<\/td><td>More frequent slurry renewal reduces local slurry depletion, maintaining effective abrasive concentration<\/td><td>~5\u201310% on mean MRR; ~10\u201320% on WIWNU<\/td><\/tr>\n      <tr><td><strong>Temperature \u2191 (pad surface)<\/strong><\/td><td class=\"lose\">Kp \u2193<\/td><td>PU softens above ~40\u00b0C; asperity compliance increases, reducing contact stress per asperity<\/td><td>~2\u20135% per 10\u00b0C above 40\u00b0C baseline<\/td><\/tr>\n      <tr><td><strong>Pad age \u2191 (glazing)<\/strong><\/td><td class=\"lose\">Kp \u2193<\/td><td>Glazed asperity tips reduce real contact area and abrasive engagement; recovered by conditioning<\/td><td>~30\u201340% total decline without conditioning<\/td><\/tr>\n    <\/tbody>\n  <\/table>\n<\/div>\n\n<h2 id=\"pressure-velocity\">4. Pressure and Velocity: Manipulating MRR with Recipe Parameters<\/h2>\n<p>Because Preston&#8217;s equation is linear in both P and V, these are the primary recipe knobs for targeting a specific MRR. However, both parameters have non-linear regimes at their extremes that must be understood to avoid process failures.<\/p>\n\n<div class=\"jz-two-col\">\n  <div class=\"jz-col-box\">\n    <h4>\ud83d\udd35 Pressure (P) \u2014 Operating Window<\/h4>\n    <ul>\n      <li><strong>Too low (&lt;1 psi):<\/strong> Hydrodynamic lubrication regime \u2014 slurry film separates pad and wafer; MRR \u2192 0; non-contact polishing<\/li>\n      <li><strong>Optimal (1\u20134 psi for oxide, 0.5\u20132 psi for Cu\/low-k):<\/strong> Mixed lubrication; Preston equation holds; stable, predictable MRR<\/li>\n      <li><strong>Too high (&gt;5\u20136 psi):<\/strong> Pad deformation reduces effective asperity height; thermal softening reduces Kp; defect density spikes; MRR plateaus or declines<\/li>\n    <\/ul>\n  <\/div>\n  <div class=\"jz-col-box\">\n    <h4>\ud83d\udd36 Velocity (V) \u2014 Operating Window<\/h4>\n    <ul>\n      <li><strong>Too low (&lt;0.1 m\/s effective):<\/strong> Insufficient centrifugal slurry delivery; slurry starvation at wafer center; non-uniform removal<\/li>\n      <li><strong>Optimal (0.3\u20131.0 m\/s):<\/strong> Good slurry transport; Preston equation holds; throughput benefit of higher velocity<\/li>\n      <li><strong>Too high (&gt;1.5 m\/s):<\/strong> Centrifugal slurry ejection from under wafer; thermal runaway risk; increased pad-conditioner wear at high heat generation rate<\/li>\n    <\/ul>\n  <\/div>\n<\/div>\n\n<h2 id=\"pad-hardness-mrr\">5. Pad Hardness vs. MRR: A Quantitative Look<\/h2>\n<p>The relationship between pad Shore D hardness and MRR is approximately linear within the production operating range (Shore D 35\u201365), with a proportionality constant that depends on slurry type, abrasive particle size, and film material. Across our in-house characterization database of oxide CMP recipes, we observe the following approximate relationship:<\/p>\n\n<div class=\"jz-callout info\">\n  <div class=\"jz-callout-icon\">\ud83d\udcca<\/div>\n  <div class=\"jz-callout-body\">\n    <strong>Jizhi Laboratory Data \u2014 Oxide CMP (SiO\u2082, Ceria Slurry, Standard Recipe)<\/strong>\n    Measured on our JZ-H series pads at P = 3 psi, V = 0.6 m\/s, slurry flow = 200 mL\/min, in-situ conditioning:<br><br>\n    Shore D 58 pad: MRR = 1,820 \u00b1 65 \u00c5\/min (Kp = 1.01 \u00d7 10\u207b\u2078 Pa\u207b\u00b9)<br>\n    Shore D 62 pad: MRR = 2,110 \u00b1 72 \u00c5\/min (Kp = 1.17 \u00d7 10\u207b\u2078 Pa\u207b\u00b9)<br>\n    Shore D 66 pad: MRR = 2,380 \u00b1 85 \u00c5\/min (Kp = 1.32 \u00d7 10\u207b\u2078 Pa\u207b\u00b9)<br><br>\n    Implied: ~14% MRR increase per 4 Shore D units at this recipe and slurry combination. Extrapolation to other slurry systems requires independent characterization.\n  <\/div>\n<\/div>\n\n<p>This data has a direct practical implication: if you switch from a Shore D 58 to a Shore D 62 pad (within the same product family), you should expect approximately 14% higher removal rate at identical recipe settings. To maintain the same removal rate target, reduce down-force pressure by approximately 12% or adjust platen speed accordingly.<\/p>\n\n<h2 id=\"porosity-mrr\">6. Porosity and Slurry Uptake vs. MRR<\/h2>\n<p>Pore structure affects MRR through the slurry micro-transport mechanism. Higher pore density and larger pore diameter increase the reservoir of slurry available at the pad-wafer interface, raising effective abrasive concentration at the contact zone \u2014 which increases Kp. However, higher porosity also reduces the solid polymer volume fraction, reducing effective hardness and asperity stiffness \u2014 which decreases Kp. These opposing effects create an optimal pore loading that maximizes MRR for a given hardness target.<\/p>\n\n<p>Our characterization data shows that for hard PU oxide CMP pads at constant Shore D hardness (achieved by adjusting NCO\/OH index to compensate for pore volume fraction changes):<\/p>\n<ul>\n  <li>Increasing pore volume fraction from 15% to 25% raises MRR by approximately 8\u201312% at standard recipe conditions<\/li>\n  <li>Increasing pore volume fraction beyond 30% provides diminishing MRR returns while measurably increasing defect density from pore-debris contamination<\/li>\n  <li>The optimal pore volume fraction for production hard oxide CMP pads is 20\u201327%, consistent with the IC1000-type industry standard<\/li>\n<\/ul>\n\n<p>Poreless pads have effectively zero pore-driven slurry micro-transport. Their MRR is slightly lower than equivalent-hardness porous pads at the same recipe settings (typically 5\u201312% lower) but delivers significantly better MRR lot-to-lot consistency. For the full poreless vs. porous trade-off, see: <a class=\"jz-link-chip\" href=\"https:\/\/jeez-semicon.com\/ja\/blog\/Poreless-CMP-Pads-vs-Porous-Structure\/\" target=\"_blank\">Poreless CMP Pads vs. Porous Structure<\/a>.<\/p>\n\n<h2 id=\"groove-mrr\">7. Groove Geometry vs. MRR Uniformity<\/h2>\n<p>Groove design does not significantly affect mean MRR (the average removal rate across the whole wafer), but it strongly affects MRR uniformity \u2014 the radial and azimuthal distribution of removal rate across the 300 mm wafer surface. The key relationship is between groove pitch and the slurry renewal frequency under the wafer.<\/p>\n\n<div class=\"jz-table-wrap\">\n  <table class=\"jz-table\">\n    <thead><tr><th>Groove Pitch<\/th><th>Slurry Renewals per Revolution (@ wafer center)<\/th><th>Expected WIWNU (1\u03c3) Effect<\/th><\/tr><\/thead>\n    <tbody>\n      <tr><td>6.0 mm pitch<\/td><td>~8 renewals\/revolution<\/td><td>Higher center-low profile risk \u2014 slurry starvation at wafer center<\/td><\/tr>\n      <tr><td>3.0 mm pitch<\/td><td>~16 renewals\/revolution<\/td><td>Standard production \u2014 acceptable center-to-edge balance<\/td><\/tr>\n      <tr><td>2.0 mm pitch<\/td><td>~24 renewals\/revolution<\/td><td>Improved center delivery \u2014 better uniformity at cost of higher groove fraction<\/td><\/tr>\n      <tr><td>1.5 mm pitch<\/td><td>~32 renewals\/revolution<\/td><td>Best uniformity \u2014 diminishing returns; groove fraction may be excessive<\/td><\/tr>\n    <\/tbody>\n  <\/table>\n<\/div>\n\n<p>For processes where radial MRR uniformity is the primary concern \u2014 such as final Cu BEOL buff steps where WIWNU targets are below 1% (1\u03c3) \u2014 fine-pitch groove patterns (1.5\u20132.0 mm) are preferred despite their lower mean MRR relative to wide-pitch designs. For the full groove design analysis, see: <a class=\"jz-link-chip\" href=\"https:\/\/jeez-semicon.com\/ja\/blog\/CMP-Pad-Groove-Design-and-Slurry-Distribution\/\" target=\"_blank\">CMP Pad Groove Design and Slurry Distribution<\/a>.<\/p>\n\n<h2 id=\"mrr-stability\">8. MRR Stability Over Pad Lifetime<\/h2>\n<p>Achieving a consistent MRR from wafer to wafer across the full pad lifetime is the operational goal \u2014 it is what enables tight thickness control at end-of-polish and minimizes recipe adjustment frequency. Three regimes of MRR behavior occur over pad lifetime:<\/p>\n\n<div class=\"jz-card-grid\">\n  <div class=\"jz-card\">\n    <div class=\"jz-card-icon\">\ud83d\udcc8<\/div>\n    <h4>Break-In Ramp (Wafers 1\u201350)<\/h4>\n    <p>MRR rises from a low initial value (~60% of stable-state target) as pad skin is removed and pores are opened. High variability (CV &gt;15%). All wafers in this phase should be non-product monitors. Break-in conditioning accelerates this phase.<\/p>\n  <\/div>\n  <div class=\"jz-card\">\n    <div class=\"jz-card-icon\">\u27a1\ufe0f<\/div>\n    <h4>Stable Working Phase (Wafers 50\u20131,800+)<\/h4>\n    <p>MRR stabilized within \u00b18% of target. CV &lt;5% with well-optimized conditioning. All production wafers should be polished in this window. Conditioning maintains stable asperity distribution. Small slow drift (&lt;1% per 100 wafers) is normal and expected.<\/p>\n  <\/div>\n  <div class=\"jz-card\">\n    <div class=\"jz-card-icon\">\ud83d\udcc9<\/div>\n    <h4>End-of-Life Decline (Final 10\u201315% of Lifetime)<\/h4>\n    <p>MRR declines as pad thickness approaches minimum \u2014 reduced bulk compressibility changes macro-contact mechanics. Conditioning cannot fully compensate. Sustained MRR decline &gt;15% from stable baseline triggers pad replacement evaluation.<\/p>\n  <\/div>\n<\/div>\n\n<div class=\"jz-callout success\">\n  <div class=\"jz-callout-icon\">\u2705<\/div>\n  <div class=\"jz-callout-body\">\n    <strong>Jizhi MRR Stability Specification<\/strong>\n    Our production-grade hard oxide CMP pads (JZ-H60 and JZ-H65 series) are characterized to deliver MRR coefficient of variation (CV) below 4.5% across the stable working phase (wafers 50 through end-of-life) under our reference conditioning protocol. This specification is verified on a sample from every production lot and reported on the Certificate of Analysis shipped with each pad order. Customers with APC systems can integrate this data directly into their MRR prediction models.\n  <\/div>\n<\/div>\n\n<h2 id=\"process-window\">9. Process Window Engineering: Maximizing Throughput Within Yield Constraints<\/h2>\n<p>The &#8220;process window&#8221; for a CMP step is the range of recipe parameters (P, V, slurry flow rate, conditioning intensity) over which all yield metrics \u2014 MRR target, WIWNU, defect density \u2014 are simultaneously within specification. Wider process windows provide more robustness against process variation and tool-to-tool differences. Narrower windows require tighter process control and are more sensitive to pad lot changes.<\/p>\n\n<p>Pad parameter choices directly determine process window width:<\/p>\n\n<ul>\n  <li><strong>Higher pad hardness<\/strong> widens the MRR process window (less sensitive to pressure variation) but narrows the defect window (harder asperities increase scratch sensitivity to over-pressure)<\/li>\n  <li><strong>Tighter pore size distribution (CV &lt;15%)<\/strong> widens the MRR window by reducing pad-to-pad Kp variation \u2014 the same recipe delivers the same MRR regardless of which pad in a lot is used<\/li>\n  <li><strong>Optimized groove pitch<\/strong> widens the WIWNU window by reducing the process&#8217;s sensitivity to slurry flow rate variations \u2014 the groove&#8217;s buffering effect smooths out transient flow perturbations<\/li>\n  <li><strong>Poreless pads<\/strong> deliver the widest lot-to-lot Kp consistency (&lt;3% CV) \u2014 widening the recipe transfer window when moving between pad lots or tool platforms<\/li>\n<\/ul>\n\n<p>For guidance on how to select pads that maximize process window for your specific application, see our comprehensive selection guide: <a class=\"jz-link-chip\" href=\"https:\/\/jeez-semicon.com\/ja\/blog\/Hard-vs-Soft-CMP-Polishing-Pads-Selection-Guide\/\" target=\"_blank\">Hard vs. Soft CMP Polishing Pads: Selection Guide<\/a>.<\/p>\n\n<h2>10. Frequently Asked Questions<\/h2>\n<div class=\"jz-faq\">\n  <div class=\"jz-faq-item\">\n    <div class=\"jz-faq-q\">Why does MRR sometimes increase at the start of a polishing run then decrease?<\/div>\n    <div class=\"jz-faq-a\">This &#8220;hump&#8221; behavior is common and has two causes. First, thermal warm-up: at the start of a run, the pad and slurry are at ambient temperature. As polishing progresses, frictional heat raises the interface temperature, which accelerates chemical passivation rates \u2014 temporarily increasing MRR. As temperature continues to rise toward steady state, pad softening partially counteracts this effect, causing MRR to stabilize or slightly decrease. Second, slurry particle activation: some slurry types (particularly ceria) undergo surface chemistry changes during the first 30\u201360 seconds of contact with the wafer film, which can cause an initial MRR spike. Understanding which mechanism dominates in your process determines the appropriate mitigation \u2014 temperature stabilization (longer pre-wet time) for thermal effects, or slurry pre-conditioning (circulating slurry before loading wafer) for chemistry effects.<\/div>\n  <\/div>\n  <div class=\"jz-faq-item\">\n    <div class=\"jz-faq-q\">How do I determine the Preston coefficient Kp for a new pad-slurry combination?<\/div>\n    <div class=\"jz-faq-a\">Kp is determined experimentally by measuring MRR at a minimum of 4\u20136 combinations of P and V that span the intended operating range, then fitting a linear regression through the MRR vs. (P \u00d7 V) data. The slope of this line is Kp. Use at least 3 wafers per (P, V) condition to average out wafer-to-wafer variation. All measurements should be taken on a fully broken-in pad (after the stable working phase is established) to avoid confounding Kp with the break-in ramp. Report Kp with its 95% confidence interval \u2014 the width of this interval quantifies how well the Preston model fits your specific system.<\/div>\n  <\/div>\n  <div class=\"jz-faq-item\">\n    <div class=\"jz-faq-q\">Why does the same pad give different MRR on different tools?<\/div>\n    <div class=\"jz-faq-a\">Tool-to-tool MRR variation from the same pad-slurry combination is common and has several root causes: differences in actual down-force delivered to the wafer (tool-specific retaining ring compliance and carrier head calibration), differences in effective platen and carrier velocity (motor speed calibration), differences in slurry temperature (platen cooling water circuit differences), and differences in conditioner disk wear state. To minimize tool-to-tool variation, calibrate down-force and velocity on each tool independently using reference metrology, and use the same conditioner disk lot across tools. Jizhi provides Kp characterization data measured on an Applied Materials Reflexion reference tool \u2014 conversion factors for other tool platforms are available on request.<\/div>\n  <\/div>\n  <div class=\"jz-faq-item\">\n    <div class=\"jz-faq-q\">Can MRR be increased without changing recipe parameters?<\/div>\n    <div class=\"jz-faq-a\">Yes \u2014 several pad and conditioning adjustments increase Kp (and therefore MRR at constant P \u00d7 V): switching to a harder pad formulation (+8\u201315% MRR), increasing conditioner down-force to generate higher surface Ra (+5\u201315% MRR, at the cost of higher scratch risk), increasing slurry concentration or changing to a more reactive slurry chemistry (not a pad change, but the most effective lever), or switching to a finer groove pitch to improve slurry uniformity and effective abrasive concentration at the center. Each option carries trade-offs in defect density, pad wear rate, and process window width that must be evaluated against the MRR gain.<\/div>\n  <\/div>\n<\/div>\n\n<div class=\"jz-related\">\n  <div class=\"jz-related-title\">\ud83d\udcda Continue Reading \u2014 CMP Pad Deep Dives<\/div>\n  <div class=\"jz-related-grid\">\n    <div class=\"jz-related-item\"><div class=\"jz-related-cat\">PILLAR<\/div><a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/CMP-Polishing-Pads-The-Complete-Guide\/\" target=\"_blank\">CMP Polishing Pads: The Complete Guide<\/a><\/div>\n    <div class=\"jz-related-item\"><div class=\"jz-related-cat\">FUNDAMENTALS<\/div><a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/How-CMP-Polishing-Pads-Work\/\" target=\"_blank\">How CMP Polishing Pads Work<\/a><\/div>\n    <div class=\"jz-related-item\"><div class=\"jz-related-cat\">SELECTION<\/div><a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/Hard-vs-Soft-CMP-Polishing-Pads-Selection-Guide\/\" target=\"_blank\">Hard vs. Soft CMP Polishing Pads: Selection Guide<\/a><\/div>\n    <div class=\"jz-related-item\"><div class=\"jz-related-cat\">ENGINEERING<\/div><a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/CMP-Pad-Groove-Design-and-Slurry-Distribution\/\" target=\"_blank\">CMP Pad Groove Design and Slurry Distribution<\/a><\/div>\n    <div class=\"jz-related-item\"><div class=\"jz-related-cat\">OPERATIONS<\/div><a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/CMP-Pad-Conditioning-and-Lifespan-Management\/\" target=\"_blank\">CMP Pad Conditioning and Lifespan Management<\/a><\/div>\n    <div class=\"jz-related-item\"><div class=\"jz-related-cat\">QUALITY<\/div><a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/CMP-Pad-Defect-Control-Scratches-and-Uniformity\/\" target=\"_blank\">CMP Pad Defect Control: Scratches and Uniformity<\/a><\/div>\n    <div class=\"jz-related-item\"><div class=\"jz-related-cat\">TECHNOLOGY<\/div><a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/Poreless-CMP-Pads-vs-Porous-Structure\/\" target=\"_blank\">Poreless CMP Pads vs. Porous Structure<\/a><\/div>\n    <div class=\"jz-related-item\"><div class=\"jz-related-cat\">SOURCING<\/div><a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/CMP-Polishing-Pad-Brands-Comparison\/\" target=\"_blank\">CMP Polishing Pad Brands Comparison<\/a><\/div>\n    <div class=\"jz-related-item\"><div class=\"jz-related-cat\">PROCUREMENT<\/div><a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/CMP-Polishing-Pad-Price-Factors-and-Buying-Guide\/\" target=\"_blank\">CMP Polishing Pad Price Factors and Buying Guide<\/a><\/div>\n  <\/div>\n<\/div>\n\n<div class=\"jz-cta-banner\">\n  <h2>Know Your Kp Before Installation \u2014 Jizhi Provides It<\/h2>\n  <p>Every Jizhi CMP pad lot ships with measured Preston coefficient (Kp) data from our reference recipe characterization, enabling process engineers to predict recipe adjustments before the first production wafer is polished. Hard pads, soft subpads, and SiC-specific formulations available.<\/p>\n  <a class=\"jz-btn jz-btn-white\" href=\"https:\/\/jeez-semicon.com\/ja\/semi-categories\/polishing-pad\/\" target=\"_blank\">Browse CMP Polishing Pads<\/a>\n  <a class=\"jz-btn jz-btn-outline\" href=\"https:\/\/jeez-semicon.com\/ja\/contact\/\" target=\"_blank\">Request Kp Data Sheet<\/a>\n<\/div>\n<\/div>","protected":false},"excerpt":{"rendered":"<p>Back to CMP Polishing Pads: The Complete Guide Jizhi Electronic Technology \u2014 Process Series A data-driven analysis of how CMP polishing pad properties \u2014 hardness, porosity, groove geometry, and surface  &#8230;<\/p>","protected":false},"author":1,"featured_media":1813,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[9,59],"tags":[],"class_list":["post-1779","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-blog","category-industry"],"acf":[],"_links":{"self":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts\/1779","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/comments?post=1779"}],"version-history":[{"count":2,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts\/1779\/revisions"}],"predecessor-version":[{"id":1781,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts\/1779\/revisions\/1781"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/media\/1813"}],"wp:attachment":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/media?parent=1779"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/categories?post=1779"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/tags?post=1779"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}