{"id":1850,"date":"2026-04-21T09:10:02","date_gmt":"2026-04-21T01:10:02","guid":{"rendered":"https:\/\/jeez-semicon.com\/?p=1850"},"modified":"2026-04-21T09:38:09","modified_gmt":"2026-04-21T01:38:09","slug":"shallow-trench-isolation-sti-cmp-process-and-optimization","status":"publish","type":"post","link":"https:\/\/jeez-semicon.com\/ja\/blog\/shallow-trench-isolation-sti-cmp-process-and-optimization\/","title":{"rendered":"Shallow Trench Isolation (STI) CMP: Process and Optimization"},"content":{"rendered":"<style>\n.jeez-art*,.jeez-art *::before,.jeez-art *::after{box-sizing:border-box;margin:0;padding:0}.jeez-art{font-family:\"Georgia\",\"Times New Roman\",serif;font-size:17px;line-height:1.85;color:#1a1a2e;background:#fff;max-width:900px;margin:0 auto;padding:0 20px 60px}.jeez-art h1{font-family:\"Trebuchet MS\",\"Segoe UI\",sans-serif;font-size:clamp(26px,4vw,40px);font-weight:800;line-height:1.2;color:#0a1628;margin-bottom:18px;letter-spacing:-0.5px}.jeez-art h2{font-family:\"Trebuchet MS\",\"Segoe UI\",sans-serif;font-size:clamp(20px,3vw,28px);font-weight:700;color:#0a1628;margin-top:52px;margin-bottom:16px;padding-bottom:10px;border-bottom:3px solid #0057b8}.jeez-art h2::before{content:\"\";display:inline-block;width:6px;height:26px;background:#0057b8;border-radius:3px;margin-right:12px;vertical-align:middle;position:relative;top:-2px}.jeez-art h3{font-family:\"Trebuchet MS\",\"Segoe UI\",sans-serif;font-size:clamp(16px,2.2vw,21px);font-weight:700;color:#0a1628;margin-top:34px;margin-bottom:12px}.jeez-art h4{font-family:\"Trebuchet MS\",\"Segoe UI\",sans-serif;font-size:15px;font-weight:700;color:#0057b8;margin-top:22px;margin-bottom:8px;text-transform:uppercase;letter-spacing:.6px}.jeez-art p{margin-bottom:18px}.jeez-art a{color:#0057b8;text-decoration:underline;text-underline-offset:3px;transition:color .2s}.jeez-art a:hover{color:#003d82}.jeez-art ul,.jeez-art ol{margin-bottom:20px;padding-left:26px}.jeez-art li{margin-bottom:8px}.jeez-art strong{font-weight:700}\n.ja-hero{background:linear-gradient(135deg,#0a1628 0%,#0057b8 60%,#0a9396 100%);color:#fff;border-radius:12px;padding:48px 40px;margin-bottom:40px;position:relative;overflow:hidden}.ja-hero .hero-badge{display:inline-block;background:rgba(255,255,255,.15);border:1px solid rgba(255,255,255,.3);border-radius:20px;padding:4px 14px;font-size:12px;font-family:\"Trebuchet MS\",sans-serif;letter-spacing:1px;text-transform:uppercase;margin-bottom:14px}.ja-hero h1{color:#fff;margin-bottom:12px}.ja-hero p{font-size:15px;color:rgba(255,255,255,.85);max-width:620px;line-height:1.7;margin-bottom:0}\n.ja-toc{background:#f0f6ff;border:1px solid #c8dcf5;border-left:5px solid #0057b8;border-radius:8px;padding:26px 30px;margin-bottom:40px}.ja-toc-title{font-family:\"Trebuchet MS\",sans-serif;font-size:14px;font-weight:700;text-transform:uppercase;letter-spacing:1.2px;color:#0057b8;margin-bottom:12px}.ja-toc ol{padding-left:20px;margin:0;columns:2;column-gap:28px}.ja-toc li{font-family:\"Trebuchet MS\",sans-serif;font-size:13px;margin-bottom:6px;break-inside:avoid}.ja-toc a{color:#0a1628;text-decoration:none;border-bottom:1px dotted #0057b8;padding-bottom:1px}.ja-toc a:hover{color:#0057b8}@media(max-width:560px){.ja-toc ol{columns:1}.ja-hero{padding:32px 22px}}\n.ja-callout{border-radius:8px;padding:18px 22px;margin:26px 0;display:flex;gap:14px;align-items:flex-start}.ja-callout.blue{background:#e8f2ff;border:1px solid #b3d0f5}.ja-callout.teal{background:#e6f7f7;border:1px solid #9dd4d4}.ja-callout.amber{background:#fff8e6;border:1px solid #f5d98b}.ja-callout-icon{font-size:19px;flex-shrink:0;margin-top:2px}.ja-callout-body{font-size:15px;line-height:1.7}.ja-callout-body strong{display:block;margin-bottom:4px;font-size:15px}\n.ja-table-wrap{overflow-x:auto;margin:26px 0;border-radius:10px;border:1px solid #d0dff0}.ja-table{width:100%;border-collapse:collapse;font-size:15px;min-width:480px}.ja-table th{background:#0a1628;color:#fff;padding:12px 15px;text-align:left;font-family:\"Trebuchet MS\",sans-serif;font-size:12px;text-transform:uppercase;letter-spacing:.8px;font-weight:700}.ja-table td{padding:11px 15px;border-bottom:1px solid #e4edf8;vertical-align:top;line-height:1.55}.ja-table tr:last-child td{border-bottom:none}.ja-table tr:nth-child(even) td{background:#f5f9ff}\n.ja-stats{display:grid;grid-template-columns:repeat(auto-fit,minmax(165px,1fr));gap:14px;margin:28px 0}.ja-stat{background:#0a1628;color:#fff;border-radius:10px;padding:20px 18px;text-align:center}.ja-stat .sn{font-size:28px;font-weight:800;color:#4db8ff;font-family:\"Trebuchet MS\",sans-serif;line-height:1;display:block;margin-bottom:5px}.ja-stat .sl{font-size:13px;color:rgba(255,255,255,.72);font-family:\"Trebuchet MS\",sans-serif;line-height:1.4}\n.ja-grid2{display:grid;grid-template-columns:repeat(auto-fit,minmax(230px,1fr));gap:16px;margin:24px 0}.ja-card{border:1px solid #d0dff0;border-radius:10px;padding:20px 18px;background:#fff;border-top:4px solid #0057b8}.ja-card h4{font-size:14px;margin-top:0;margin-bottom:8px;color:#0a1628;text-transform:none;letter-spacing:0}.ja-card p{font-size:14px;color:#445;margin:0;line-height:1.6}\n.ja-steps{margin:26px 0}.ja-step{display:flex;gap:18px;margin-bottom:22px;align-items:flex-start}.ja-step-num{background:#0057b8;color:#fff;width:36px;height:36px;border-radius:50%;display:flex;align-items:center;justify-content:center;font-weight:800;font-family:\"Trebuchet MS\",sans-serif;font-size:15px;flex-shrink:0;margin-top:3px}.ja-step-body h4{margin-top:0}.ja-step-body p{margin-bottom:0;font-size:15px}\n.ja-related{background:#f5f9ff;border:1px solid #c8dcf5;border-radius:10px;padding:28px 32px;margin:44px 0}.ja-related h3{font-family:\"Trebuchet MS\",sans-serif;font-size:17px;color:#0a1628;margin-top:0;margin-bottom:16px}.ja-related-grid{display:grid;grid-template-columns:repeat(auto-fit,minmax(250px,1fr));gap:10px}.ja-rlink{display:flex;align-items:center;gap:10px;padding:11px 15px;background:#fff;border:1px solid #d0dff0;border-radius:8px;text-decoration:none;color:#0a1628;font-family:\"Trebuchet MS\",sans-serif;font-size:13px;font-weight:600;transition:all .2s;border-left:3px solid #0057b8}.ja-rlink:hover{background:#e8f2ff;color:#0057b8;text-decoration:none;transform:translateX(3px)}.ja-rlink::before{content:\"\u2192\";color:#0057b8;font-size:14px;flex-shrink:0}\n.ja-cta{background:linear-gradient(135deg,#0a1628 0%,#0057b8 100%);border-radius:12px;padding:40px 36px;text-align:center;color:#fff;margin:48px 0 0}.ja-cta h3{font-size:clamp(18px,2.8vw,26px);color:#fff;margin-top:0;margin-bottom:10px;font-family:\"Trebuchet MS\",sans-serif}.ja-cta p{font-size:15px;color:rgba(255,255,255,.82);max-width:520px;margin:0 auto 24px}.ja-cta-btn{display:inline-block;background:#fff;color:#0057b8;text-decoration:none;padding:13px 34px;border-radius:50px;font-family:\"Trebuchet MS\",sans-serif;font-weight:800;font-size:14px;transition:all .2s}.ja-cta-btn:hover{background:#e8f2ff;color:#003d82;text-decoration:none;box-shadow:0 6px 24px rgba(0,0,0,.25)}\n.ja-pillar-back{background:#fff8e6;border:1px solid #f5d98b;border-left:5px solid #f5a623;border-radius:8px;padding:14px 20px;margin-bottom:36px;font-family:\"Trebuchet MS\",sans-serif;font-size:14px;color:#5c4000}.ja-pillar-back a{color:#b8620a;font-weight:700}\n.ja-divider{border:none;border-top:1px solid #e4edf8;margin:38px 0}\n.faq-item{border:1px solid #d0dff0;border-radius:8px;margin-bottom:12px;overflow:hidden}.faq-q{background:#f5f9ff;padding:14px 18px;font-family:\"Trebuchet MS\",sans-serif;font-weight:700;font-size:15px;color:#0a1628}.faq-a{padding:14px 18px;font-size:15px;line-height:1.7;color:#2c3e50;border-top:1px solid #d0dff0}\n<\/style>\n<div class=\"jeez-art\" itemscope itemtype=\"https:\/\/schema.org\/Article\">\n<div class=\"ja-pillar-back\">\ud83d\udcd8 Part of the <strong>JEEZ Complete CMP Guide<\/strong> \u2014 <a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/what-is-chemical-mechanical-planarization-cmp-complete-guide\/\" target=\"_blank\">Read the full overview here<\/a>.<\/div>\n<div class=\"ja-hero\"><div class=\"hero-badge\">JEEZ Technical Guide<\/div><p>A complete technical guide to STI CMP \u2014 covering the role of STI in FEOL device isolation, CMP process sequence, high-selectivity ceria slurry, nitride stop-layer control, dishing prevention, and advanced node scaling.<\/p><\/div>\n<nav class=\"ja-toc\"><div class=\"ja-toc-title\">\u76ee\u6b21<\/div><ol>\n<li><a href=\"#sti-role\">Role of STI in Semiconductor Manufacturing<\/a><\/li>\n<li><a href=\"#sti-flow\">STI Process Flow and CMP Integration<\/a><\/li>\n<li><a href=\"#sti-slurry\">High-Selectivity Ceria Slurry for STI<\/a><\/li>\n<li><a href=\"#sti-endpoint\">Endpoint Detection and Stop-Layer Control<\/a><\/li>\n<li><a href=\"#sti-dishing\">Active Area Dishing and Corner Rounding<\/a><\/li>\n<li><a href=\"#sti-pattern\">Pattern Density Effects and Erosion<\/a><\/li>\n<li><a href=\"#sti-cleaning\">Post-STI CMP Cleaning<\/a><\/li>\n<li><a href=\"#sti-advanced\">STI CMP at Advanced Nodes: FinFET and GAA<\/a><\/li>\n<li><a href=\"#sti-faq\">FAQ<\/a><\/li>\n<\/ol><\/nav>\n\n<section id=\"sti-role\">\n<h2>The Role of Shallow Trench Isolation in Semiconductor Manufacturing<\/h2>\n<p>Shallow Trench Isolation (STI) is the dominant technology for electrically isolating adjacent transistors from one another on a silicon wafer. Without isolation, the electric field from one transistor would extend into neighboring devices, causing parasitic current leakage, latch-up, and device crosstalk that would make reliable circuit operation impossible. STI achieves this isolation by physically surrounding each active transistor area with deep trenches filled with silicon dioxide insulator, creating an impenetrable electrical barrier between devices.<\/p>\n<p>STI replaced the earlier LOCOS (Local Oxidation of Silicon) isolation technique starting at the 250 nm node, driven by three advantages: STI creates a more planar surface (critical for CMP compatibility), consumes less lateral silicon real estate (enabling higher transistor packing density), and avoids the &#8220;bird&#8217;s beak&#8221; encroachment artifact of LOCOS that caused active area reduction and threshold voltage variability. Since its introduction, STI has scaled seamlessly from 250 nm to the 2 nm node in 2026, with process modifications at each generation to accommodate shrinking trench dimensions and new transistor architectures.<\/p>\n<div class=\"ja-stats\">\n<div class=\"ja-stat\"><span class=\"sn\">250 nm<\/span><span class=\"sl\">Node at which STI replaced LOCOS isolation<\/span><\/div>\n<div class=\"ja-stat\"><span class=\"sn\">&gt;100:1<\/span><span class=\"sl\">SiO\u2082:Si\u2083N\u2084 selectivity required in STI CMP<\/span><\/div>\n<div class=\"ja-stat\"><span class=\"sn\">&lt;5 nm<\/span><span class=\"sl\">Active area dishing specification at 7 nm node<\/span><\/div>\n<div class=\"ja-stat\"><span class=\"sn\">1st<\/span><span class=\"sl\">CMP step in the FEOL process sequence<\/span><\/div>\n<\/div>\n<\/section>\n\n<section id=\"sti-flow\">\n<h2>STI Process Flow and CMP Integration<\/h2>\n<p>The STI process is one of the earliest steps in the FEOL fabrication sequence, performed on a bare or lightly processed silicon wafer before any transistor gate structures are formed. Understanding the full process flow is essential for understanding the specific requirements it places on the CMP step.<\/p>\n<div class=\"ja-steps\">\n<div class=\"ja-step\"><div class=\"ja-step-num\">1<\/div><div class=\"ja-step-body\"><h4>Pad Oxide and Nitride Deposition<\/h4><p>A thin pad oxide layer (5\u201310 nm thermal SiO\u2082) is grown on the silicon wafer surface, followed by deposition of a silicon nitride (Si\u2083N\u2084) layer by LPCVD (50\u2013100 nm). This Si\u2083N\u2084\/SiO\u2082 stack serves as the CMP polish stop layer \u2014 the CMP process must remove oxide down to this nitride surface without consuming it, so the nitride must have a dramatically lower removal rate than the oxide being polished.<\/p><\/div><\/div>\n<div class=\"ja-step\"><div class=\"ja-step-num\">2<\/div><div class=\"ja-step-body\"><h4>Active Area Patterning and Trench Etch<\/h4><p>Photolithography defines the active area pattern (the transistor body regions that must be protected) in the nitride layer. A reactive ion etch (RIE) step opens trenches in the silicon substrate, typically 200\u2013400 nm deep and 50\u2013200 nm wide at advanced nodes. The nitride acts as a hard mask, protecting the active areas from the etch.<\/p><\/div><\/div>\n<div class=\"ja-step\"><div class=\"ja-step-num\">3<\/div><div class=\"ja-step-body\"><h4>Liner Oxidation and Oxide Fill<\/h4><p>A brief thermal oxidation step grows a thin liner oxide (3\u20135 nm) on the trench sidewalls to passivate silicon damage from the etch and reduce interface state density. The trench is then filled with high-density plasma CVD (HDP-CVD) or sub-atmospheric TEOS oxide, which deposits conformally to fill the trench without voids. The deposited oxide is substantially thicker than the trench depth, leaving a significant oxide overburden (200\u2013600 nm) above the nitride surface that must be removed by CMP.<\/p><\/div><\/div>\n<div class=\"ja-step\"><div class=\"ja-step-num\">4<\/div><div class=\"ja-step-body\"><h4>STI CMP \u2014 Oxide Planarization to Nitride Stop<\/h4><p>The CMP step removes the oxide overburden and achieves global planarity across the wafer, stopping precisely on the Si\u2083N\u2084 layer. This is the most critical and technically challenging step of the STI process. The polish must remove 200\u2013600 nm of oxide selectively over the nitride, with uniformity sufficient to achieve a globally planar surface across an entire 300 mm wafer that may contain a mix of dense and sparse active area patterns.<\/p><\/div><\/div>\n<div class=\"ja-step\"><div class=\"ja-step-num\">5<\/div><div class=\"ja-step-body\"><h4>Nitride Strip and Post-STI Clean<\/h4><p>After CMP, the Si\u2083N\u2084 polish stop layer is selectively removed by wet phosphoric acid (H\u2083PO\u2084) etching, leaving the oxide-filled trenches elevated slightly above the silicon active areas \u2014 the classic &#8220;recessed oxide&#8221; STI profile. Post-CMP cleaning removes residual ceria particles and CMP byproducts before the next FEOL process step.<\/p><\/div><\/div>\n<\/div>\n<\/section>\n\n<section id=\"sti-slurry\">\n<h2>High-Selectivity Ceria Slurry for STI CMP<\/h2>\n<p>The CMP slurry is the critical enabler of successful STI CMP. STI CMP imposes the most stringent selectivity requirement of any CMP application \u2014 the slurry must remove SiO\u2082 at a rate 100\u2013500\u00d7 faster than it removes Si\u2083N\u2084. This requirement eliminates conventional colloidal silica-based oxide slurries, which achieve SiO\u2082:Si\u2083N\u2084 selectivity of only 4:1 to 10:1 \u2014 far insufficient to stop reliably on the nitride surface across a full 300 mm wafer with 200\u2013600 nm of oxide to be removed.<\/p>\n<h3>Why Ceria Achieves High Selectivity<\/h3>\n<p>Cerium dioxide (CeO\u2082) abrasive achieves high oxide-to-nitride selectivity through a fundamentally different removal mechanism than silica abrasives. Ceria particles react directly with the SiO\u2082 surface through a chemical mechanism involving direct Ce\u2013O\u2013Si bond formation (the &#8220;tooth&#8221; mechanism, proposed by Cook in 1990). This chemical bond formation is highly specific to SiO\u2082 and does not occur readily with Si\u2083N\u2084, which has no reactive Si\u2013O\u2013Si backbone for ceria to attack. The result is that ceria removes SiO\u2082 at rates 5\u201310\u00d7 higher than silica abrasive at the same concentration and pad conditions, while leaving Si\u2083N\u2084 nearly untouched.<\/p>\n<p>Selectivity can be further enhanced by adding amino acid additives (typically L-proline, L-arginine, or similar) to the ceria slurry, which preferentially adsorb onto the Si\u2083N\u2084 surface and passivate it against ceria attack without significantly affecting SiO\u2082 removal rate. With optimized amino acid loading, SiO\u2082:Si\u2083N\u2084 selectivities exceeding 500:1 have been demonstrated in laboratory conditions, with 100\u2013200:1 routinely achieved in production.<\/p>\n<\/section>\n\n<section id=\"sti-endpoint\">\n<h2>Endpoint Detection and Stop-Layer Control<\/h2>\n<p>Endpoint detection for STI CMP faces a unique challenge: the goal is to stop polishing precisely on the Si\u2083N\u2084 surface across the entire wafer \u2014 not to reach a particular film thickness target. This means the endpoint signal must indicate nitride exposure, not just film thickness change.<\/p>\n<h3>Motor Current Endpoint for STI<\/h3>\n<p>The difference in friction coefficient between SiO\u2082 and Si\u2083N\u2084 against the polishing pad creates a measurable change in drive motor current as the polishing surface transitions from oxide-dominant to nitride-dominant contact. The motor current signature for STI CMP typically shows a gradual increase (more of the nitride surface being exposed) followed by a plateau (full nitride exposure). The endpoint is set at the current plateau or at a defined percentage of the current signature transition.<\/p>\n<h3>Optical Interferometry for STI<\/h3>\n<p>Broadband reflectometry can also be used for STI endpoint, using the distinctive difference in optical reflectivity between TEOS oxide and Si\u2083N\u2084. As the oxide overburden is cleared and the nitride surface begins to dominate the reflected spectrum, the interferometric signal changes character \u2014 shifting from periodic oxide interference fringes to the characteristic Si\u2083N\u2084 reflectivity signature. The accuracy of optical endpoint for STI is somewhat lower than for metal CMP due to the complex pattern-dependent topography of the STI surface, but it provides a useful independent confirmation signal when used alongside motor current monitoring.<\/p>\n<\/section>\n\n<section id=\"sti-dishing\">\n<h2>Active Area Dishing and Corner Rounding<\/h2>\n<p>In STI CMP, &#8220;dishing&#8221; takes a different form than in copper CMP: it refers to the over-polishing of the oxide within the isolation trench itself, causing the oxide surface to be recessed below the level of the surrounding silicon active area. This active area dishing affects transistor performance in two ways: it alters the effective height of the STI isolation relative to the gate electrode (affecting fringing field and threshold voltage), and it creates a non-planar surface at the active area-STI boundary that interferes with gate lithography and potentially causes poly-silicon residue at the trench corners.<\/p>\n<p>Corner rounding \u2014 the gradual rounding of the sharp 90\u00b0 corner at the top of the STI trench during polishing \u2014 is actually a partially desired effect in shallow trench isolation (sharp silicon corners cause electric field crowding and premature transistor breakdown), but excessive corner rounding reduces the effective channel width of the transistor. Both dishing and corner rounding are minimized by using high-selectivity ceria slurry (which stops quickly on nitride, limiting overpolish time) and by careful dummy active area placement to equalize local pattern density.<\/p>\n<\/section>\n\n<section id=\"sti-pattern\">\n<h2>Pattern Density Effects and Erosion in STI CMP<\/h2>\n<p>STI CMP pattern density effects are among the most significant in all of semiconductor CMP, because the STI pattern is the first CMP step in the process flow and any planarity deficiency it introduces propagates and potentially amplifies through all subsequent steps. The fundamental issue is that regions of the die with dense active areas (high nitride density, low oxide fill fraction) polish at a different rate than regions with sparse active areas (low nitride density, high oxide fill fraction).<\/p>\n<p>In dense regions, the remaining oxide load per unit area is lower, so the nitride stop is reached earlier \u2014 meaning these regions may be overpolished relative to the endpoint if polishing continues until sparse regions clear. This creates an array erosion profile where the dense-pattern area is at a slightly different height than the sparse-field area. Mitigations include: dummy active area fill (adding non-functional silicon active area tiles in sparse regions), reverse-tone dummy fill (adding non-functional oxide-only tiles in dense STI regions), and pattern-density-aware CMP simulation for recipe optimization.<\/p>\n<\/section>\n\n<section id=\"sti-cleaning\">\n<h2>Post-STI CMP Cleaning: Ceria Particle Removal<\/h2>\n<p>Post-STI CMP cleaning presents a specific challenge not encountered in other CMP applications: ceria (CeO\u2082) particles have a positive surface charge at neutral to slightly alkaline pH (zeta potential ~ +20 to +40 mV at pH 5\u20137), while the SiO\u2082 surface they must be removed from has a negative charge at the same pH. This electrostatic attraction between ceria particles and the oxide surface makes them significantly harder to remove than silica or alumina particles that have the same charge sign as the surface.<\/p>\n<p>The solution is to clean at acidic pH (pH 3\u20135 using dilute citric acid, malic acid, or HCl), which reduces the positive zeta potential of the ceria particles and reduces the magnitude of the electrostatic attraction, allowing PVA brush scrubbing to dislodge them. Alternatively, a dilute EDTA chelating solution can complex the Ce\u00b3\u207a\/Ce\u2074\u207a ions that mediate ceria-SiO\u2082 adhesion, achieving particle lift-off without pH reduction. For a complete post-CMP cleaning methodology, see our guide: <a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/Post-CMP-Cleaning-Methods-Challenges-and-Best-Practices\/\" target=\"_blank\">Post-CMP Cleaning: Methods, Challenges, and Best Practices<\/a>.<\/p>\n<\/section>\n\n<section id=\"sti-advanced\">\n<h2>STI CMP at Advanced Nodes: FinFET and GAA Challenges<\/h2>\n<p>The transition from planar MOSFET transistors (32 nm and above) to three-dimensional FinFET architectures (20 nm and below) fundamentally changed the role and requirements of STI CMP. In a FinFET process, the STI CMP step does not simply fill and planarize isolation trenches \u2014 it also defines the height of the silicon fins that will form the transistor channel. The final STI oxide surface level, set by the CMP stop-on-nitride height, determines the fin height above the oxide \u2014 a dimension that directly controls the transistor&#8217;s drive current and subthreshold slope.<\/p>\n<p>At the 3 nm and 2 nm nodes using Gate-All-Around (GAA) nanosheet transistors, STI CMP requirements evolve further. The nanosheet stacks that form the channel require precisely controlled STI fill at extremely fine pitch, and any CMP-induced planarity non-uniformity across the nanosheet stack will cause variation in the number of nanosheets exposed above the STI oxide \u2014 directly varying the effective channel width and hence the transistor&#8217;s electrical characteristics from die to die. Sub-1 nm STI height uniformity specifications are now required at GAA nodes, pushing ceria slurry formulation, endpoint detection precision, and within-wafer uniformity control to their current limits.<\/p>\n<\/section>\n\n<hr class=\"ja-divider\">\n<section id=\"sti-faq\" itemscope itemtype=\"https:\/\/schema.org\/FAQPage\"><h2>\u3088\u304f\u3042\u308b\u8cea\u554f<\/h2>\n<div style=\"margin-top:20px\">\n<div class=\"faq-item\" itemscope itemprop=\"mainEntity\" itemtype=\"https:\/\/schema.org\/Question\"><div class=\"faq-q\" itemprop=\"name\">Why is silicon nitride used as the CMP stop layer in STI, and not silicon itself?<\/div><div class=\"faq-a\" itemscope itemprop=\"acceptedAnswer\" itemtype=\"https:\/\/schema.org\/Answer\"><p itemprop=\"text\">Silicon nitride is used as the STI CMP stop layer because it has a significantly lower removal rate than silicon dioxide under ceria or silica-based CMP conditions, providing the high selectivity (100:1 or greater) needed to stop polishing reliably on the stop layer surface. Using silicon directly as the stop layer is impractical for two reasons: silicon is also removed by the alkaline CMP chemistry (albeit slowly), and the silicon surface is not the correct level at which to stop \u2014 polishing to the silicon surface would remove the thin pad oxide and begin consuming the active silicon region, increasing junction depth variability and potentially causing direct silicon damage. The nitride layer, deposited at the controlled thickness on the pad oxide, provides a defined, robust, and selectively-stoppable surface at exactly the right depth in the layer stack.<\/p><\/div><\/div>\n<div class=\"faq-item\" itemscope itemprop=\"mainEntity\" itemtype=\"https:\/\/schema.org\/Question\"><div class=\"faq-q\" itemprop=\"name\">What replaced LOCOS isolation and why was STI adopted?<\/div><div class=\"faq-a\" itemscope itemprop=\"acceptedAnswer\" itemtype=\"https:\/\/schema.org\/Answer\"><p itemprop=\"text\">LOCOS (Local Oxidation of Silicon) was the dominant isolation technology from the 1970s through the 250 nm generation. In LOCOS, field oxide is grown thermally through nitride mask openings, but the thermal oxidation process causes lateral oxide encroachment under the nitride mask \u2014 the characteristic &#8220;bird&#8217;s beak&#8221; \u2014 that reduces the effective active device area and causes gradual threshold voltage variation near the active area edges. STI was adopted starting at the 250 nm node because it eliminates the bird&#8217;s beak by using a dry etch to define the trench (no lateral encroachment), achieves better planarity than LOCOS (compatible with CMP), and scales better to sub-100 nm dimensions where the bird&#8217;s beak would have consumed unacceptable active area.<\/p><\/div><\/div>\n<\/div><\/section>\n\n<div class=\"ja-related\"><h3>\ud83d\udcda Related Articles in the JEEZ CMP Knowledge Library<\/h3>\n<div class=\"ja-related-grid\">\n<a class=\"ja-rlink\" href=\"https:\/\/jeez-semicon.com\/ja\/blog\/what-is-chemical-mechanical-planarization-cmp-complete-guide\/\" target=\"_blank\">CMP Complete Guide (Pillar Page)<\/a>\n<a class=\"ja-rlink\" href=\"https:\/\/jeez-semicon.com\/ja\/blog\/CMP-Slurry-Types-Composition-Particle-Size-and-Selection-Guide\/\" target=\"_blank\">CMP Slurry: Types &#038; Selection<\/a>\n<a class=\"ja-rlink\" href=\"https:\/\/jeez-semicon.com\/ja\/blog\/CMP-in-Advanced-Nodes-Challenges-at-7nm-and-Beyond\/\" target=\"_blank\">CMP in Advanced Nodes: 7 nm+<\/a>\n<a class=\"ja-rlink\" href=\"https:\/\/jeez-semicon.com\/ja\/blog\/Post-CMP-Cleaning-Methods-Challenges-and-Best-Practices\/\" target=\"_blank\">Post-CMP Cleaning Best Practices<\/a>\n<a class=\"ja-rlink\" href=\"https:\/\/jeez-semicon.com\/ja\/blog\/CMP-Defects-Types-Root-Causes-and-Prevention-Strategies\/\" target=\"_blank\">CMP Defects: Root Causes &#038; Prevention<\/a>\n<a class=\"ja-rlink\" href=\"https:\/\/jeez-semicon.com\/ja\/blog\/CMP-Process-Steps-How-Chemical-Mechanical-Planarization-Works\/\" target=\"_blank\">CMP Process Steps Guide<\/a>\n<\/div><\/div>\n\n<div class=\"ja-cta\"><h3>Need High-Selectivity STI CMP Slurry?<\/h3><p>JEEZ supplies ceria and ceria-silica hybrid STI slurries engineered for \u2265100:1 SiO\u2082:Si\u2083N\u2084 selectivity and FinFET\/GAA-compatible planarity. Contact us for a qualification kit.<\/p><a class=\"ja-cta-btn\" href=\"https:\/\/jeez-semicon.com\/ja\/contact\/\" target=\"_blank\">Request STI Slurry Samples \u2192<\/a><\/div>\n<\/div>","protected":false},"excerpt":{"rendered":"<p>\ud83d\udcd8 Part of the JEEZ Complete CMP Guide \u2014 Read the full overview here. JEEZ Technical Guide A complete technical guide to STI CMP \u2014 covering the role of STI  &#8230;<\/p>","protected":false},"author":1,"featured_media":1876,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[9,59],"tags":[],"class_list":["post-1850","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-blog","category-industry"],"acf":[],"_links":{"self":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts\/1850","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/comments?post=1850"}],"version-history":[{"count":2,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts\/1850\/revisions"}],"predecessor-version":[{"id":1852,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts\/1850\/revisions\/1852"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/media\/1876"}],"wp:attachment":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/media?parent=1850"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/categories?post=1850"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/tags?post=1850"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}