{"id":2125,"date":"2026-05-19T14:10:27","date_gmt":"2026-05-19T06:10:27","guid":{"rendered":"https:\/\/jeez-semicon.com\/?p=2125"},"modified":"2026-05-19T14:19:12","modified_gmt":"2026-05-19T06:19:12","slug":"cmp-defect-types-root-causes-yield-improvement","status":"publish","type":"post","link":"https:\/\/jeez-semicon.com\/ja\/blog\/cmp-defect-types-root-causes-yield-improvement\/","title":{"rendered":"CMP Defect Types,Root Causes &#038; Yield Improvement"},"content":{"rendered":"<!-- ============================================================\r\n     JEEZ \u2014 Cluster Article 08\r\n     CMP Defect Types, Root Causes & Yield Improvement\r\n     Updated: May 2026\r\n     ============================================================ -->\r\n<p><style>\r\n@import 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.2s}\r\n.jc-related-link:hover{border-color:var(--jeez-sky);box-shadow:var(--shadow-sm)}\r\n.jc-related-link span.ico{font-size:16px;flex-shrink:0}\r\n.jc-cta{background:linear-gradient(135deg,var(--jeez-accent) 0%,#00a884 100%);border-radius:var(--radius-lg);padding:40px 44px;text-align:center;margin:52px 0 20px}\r\n.jc-cta h3{font-family:var(--font-head);font-size:clamp(18px,2.5vw,23px);font-weight:800;color:var(--jeez-navy);margin:0 0 10px}\r\n.jc-cta p{font-size:14px;color:rgba(10,22,40,.72);margin-bottom:20px}\r\n.jc-cta a{display:inline-block;background:var(--jeez-navy);color:#fff;font-size:14px;font-weight:700;padding:12px 30px;border-radius:30px;text-decoration:none;transition:opacity .2s}\r\n.jc-cta a:hover{opacity:.85}\r\n.jc-tag{display:inline-block;font-size:11px;font-weight:600;letter-spacing:.07em;text-transform:uppercase;background:var(--jeez-light);color:var(--jeez-blue);border:1px solid var(--jeez-border);border-radius:4px;padding:3px 8px;margin-right:5px;margin-bottom:4px}\r\n<\/style><\/p>\r\n<div class=\"jc\">\r\n<div class=\"jc-hero\">\r\n<div class=\"jc-hero-label\">Yield Engineering \u00b7 Updated May 2026<\/div>\r\n<p class=\"jc-hero-intro\">A systematic engineering reference for identifying, classifying, and eliminating CMP-induced defects \u2014 covering scratch defects, dishing, erosion, residues, delamination, and corrosion, with root-cause analysis frameworks, detection methods, and proven yield improvement strategies for production CMP modules.<\/p>\r\n<div class=\"jc-hero-meta\">\u23f1 13 min read\ud83d\udccb ~2,900 words\ud83c\udfed By JEEZ Technical Team<\/div>\r\n<\/div>\r\n<div class=\"jc-toc\">\r\n<div class=\"jc-toc-title\">\u76ee\u6b21<\/div>\r\n<ol>\r\n<li><a href=\"#defect-impact\">How CMP Defects Impact Yield<\/a><\/li>\r\n<li><a href=\"#defect-taxonomy\">CMP Defect Taxonomy<\/a><\/li>\r\n<li><a href=\"#scratch-defects\">Scratch Defects<\/a><\/li>\r\n<li><a href=\"#dishing-erosion\">Dishing &amp; Erosion<\/a><\/li>\r\n<li><a href=\"#residues\">Residues &amp; Post-CMP Contamination<\/a><\/li>\r\n<li><a href=\"#delamination\">\u30c7\u30e9\u30df\u30cd\u30fc\u30b7\u30e7\u30f3<\/a><\/li>\r\n<li><a href=\"#corrosion\">Copper Corrosion Defects<\/a><\/li>\r\n<li><a href=\"#detection\">Defect Detection Methods<\/a><\/li>\r\n<li><a href=\"#rca\">Root Cause Analysis Framework<\/a><\/li>\r\n<li><a href=\"#yield-improvement\">Yield Improvement Strategies<\/a><\/li>\r\n<\/ol>\r\n<\/div>\r\n<h2 id=\"defect-impact\">How CMP Defects Impact Yield<\/h2>\r\n<p>CMP-induced defects are one of the leading sources of yield loss in advanced semiconductor manufacturing. Unlike many process defects that are localised and predictable, CMP defects can affect entire wafer regions or manifest as subtle topography changes that only become yield-critical several process steps later \u2014 making root-cause identification particularly challenging.<\/p>\r\n<p>The economic impact is significant. At a leading-edge 300 mm fab producing 50,000 wafers per month, a 1% yield improvement at a single CMP step can be worth USD 5\u201315 million annually in additional revenue from good die. This high leverage makes CMP defect reduction one of the highest-ROI yield engineering activities in the fab. This guide complements the broader CMP context in our <a class=\"jl\" href=\"https:\/\/jeez-semicon.com\/ja\/blog\/cmp-semiconductor-the-complete-guide-to-chemical-mechanical-planarization\/\" target=\"_blank\" rel=\"noopener\">CMP Semiconductor Complete Guide<\/a>.<\/p>\r\n<div class=\"jc-highlight\"><strong>Key principle:<\/strong> CMP defects fall into two categories: <em>particle defects<\/em> (scratches, residues) that are physically visible and detectable by inspection tools, and <em>topography defects<\/em> (dishing, erosion, non-uniformity) that require metrology tools to quantify and that may not manifest as electrical failures until device testing. Both types demand rigorous process control but require different detection and mitigation strategies.<\/div>\r\n<h2 id=\"defect-taxonomy\">CMP Defect Taxonomy<\/h2>\r\n<div class=\"jc-defect-grid\">\r\n<div class=\"jc-defect-card\"><span class=\"jc-defect-sev sev-critical\">\u30af\u30ea\u30c6\u30a3\u30ab\u30eb<\/span>\r\n<h4>Micro-Scratches<\/h4>\r\n<p>Linear surface damage caused by large abrasive particles or agglomerates. Can sever metal lines, damage gate dielectrics, and cause reliability failures.<\/p>\r\n<\/div>\r\n<div class=\"jc-defect-card\"><span class=\"jc-defect-sev sev-critical\">\u30af\u30ea\u30c6\u30a3\u30ab\u30eb<\/span>\r\n<h4>\u30c7\u30e9\u30df\u30cd\u30fc\u30b7\u30e7\u30f3<\/h4>\r\n<p>Film separation at interface due to excessive polishing stress. Catastrophic for low-k dielectric films. Can cause entire die loss and tool contamination.<\/p>\r\n<\/div>\r\n<div class=\"jc-defect-card\"><span class=\"jc-defect-sev sev-high\">\u9ad8\u3044<\/span>\r\n<h4>\u30c7\u30a3\u30c3\u30b7\u30f3\u30b0<\/h4>\r\n<p>Concave recess in wide metal or oxide features after CMP. Degrades electrical resistance of wide metal lines and transistor isolation in wide STI regions.<\/p>\r\n<\/div>\r\n<div class=\"jc-defect-card\"><span class=\"jc-defect-sev sev-high\">\u9ad8\u3044<\/span>\r\n<h4>\u6d78\u98df<\/h4>\r\n<p>Thinning of dielectric field in high-density array regions. Creates topographic variation that propagates to subsequent layers and affects lithography focus budget.<\/p>\r\n<\/div>\r\n<div class=\"jc-defect-card\"><span class=\"jc-defect-sev sev-high\">\u9ad8\u3044<\/span>\r\n<h4>Residues &amp; Particles<\/h4>\r\n<p>Slurry particles, chemical by-products, and metal ions remaining on the surface after post-CMP cleaning. Cause shorts, leakage, and reliability failures.<\/p>\r\n<\/div>\r\n<div class=\"jc-defect-card\"><span class=\"jc-defect-sev sev-medium\">\u30df\u30c7\u30a3\u30a2\u30e0<\/span>\r\n<h4>Copper Corrosion<\/h4>\r\n<p>Electrochemical dissolution of copper lines during or after CMP. Manifests as increased resistance, line thinning, or pitting. Can cause electromigration failures.<\/p>\r\n<\/div>\r\n<\/div>\r\n<h2 id=\"scratch-defects\">Scratch Defects: The Primary CMP Yield Killer<\/h2>\r\n<p>Micro-scratch defects are the single most impactful CMP defect type in terms of yield loss frequency and severity. A micro-scratch is a linear groove or chain of pits on the polished wafer surface, caused by a large abrasive particle, a hard agglomerate, or a foreign particle that becomes trapped between the polishing pad and the wafer surface and is dragged across it under polishing load.<\/p>\r\n<h3>Scratch Mechanism: The Three-Body Wear Model<\/h3>\r\n<p>CMP scratch formation is best understood through the three-body wear model: the wafer (body 1), the polishing pad (body 2), and the abrasive particle (body 3). During normal CMP, abrasive particles roll between the pad and wafer, removing material through a rolling contact mechanism with relatively low surface damage. A scratch occurs when a large particle (typically &gt;1 \u00b5m) becomes embedded in the pad surface and slides rather than rolls, acting as a micro-cutting tool that ploughs a groove across the wafer surface.<\/p>\r\n<p>The critical particle size for scratch formation is application-dependent but generally corresponds to particles larger than the pad asperity height \u2014 typically 0.5\u20132 \u00b5m. This is why the large-particle count (LPC) specification \u2014 defined as the number of particles per mL above 0.5 \u00b5m or 1.0 \u00b5m, measured by single-particle optical sensing (SPOS) \u2014 is the single most important slurry quality parameter for scratch defect control.<\/p>\r\n<h3>Root Causes of Scratch Excursions<\/h3>\r\n<ul class=\"jc-ul\">\r\n<li><strong>Slurry agglomeration:<\/strong> Freeze-thaw cycling, temperature excursions, contamination, or ageing can cause irreversible particle agglomeration, spiking the LPC by 10\u2013100\u00d7. Always the first thing to check in a scratch excursion.<\/li>\r\n<li><strong>POU filter failure or bypass:<\/strong> A clogged, damaged, or accidentally bypassed point-of-use filter allows large particles to reach the wafer. Check filter differential pressure and replace on schedule.<\/li>\r\n<li><strong>Pad surface contamination:<\/strong> Hard particles embedded in pad surface from prior process contamination act as fixed abrasives. Inspect pad surface and condition aggressively to clear contaminated surface layer.<\/li>\r\n<li><strong>Retaining ring debris:<\/strong> Worn retaining ring material (PEEK fragments) entering the polishing interface. Inspect retaining ring wear profile and replace when worn beyond spec.<\/li>\r\n<li><strong>Dried slurry re-introduction:<\/strong> Dried slurry crust from the pad edge or delivery arm falling back onto the active pad surface. Review slurry dispensing arm position and pad rinse procedures.<\/li>\r\n<\/ul>\r\n<h2 id=\"dishing-erosion\">Dishing &amp; Erosion: Topography Defects<\/h2>\r\n<p>Dishing and erosion are topography defects \u2014 they do not appear as particles or surface damage in bright-field inspection but create height variations across the wafer surface that affect electrical performance and propagate to downstream lithography steps. Both phenomena are inherent to the CMP process and cannot be eliminated entirely; they must be controlled within a specification that the downstream process can tolerate.<\/p>\r\n<h3>Dishing: Mechanism and Control<\/h3>\r\n<p><strong>\u30c7\u30a3\u30c3\u30b7\u30f3\u30b0<\/strong> is a concave surface profile at the centre of a wide metal or dielectric feature after CMP, caused by the polishing pad conforming into the recessed feature as the surrounding field material is cleared. The magnitude of dishing scales with feature width: a 1 \u00b5m copper line may dish by 2\u20133 nm, while a 100 \u00b5m dummy copper fill region may dish by 30\u201350 nm under the same polishing conditions. Wide copper bus lines and large metal fill regions in the BEOL stack are the most dishing-sensitive structures.<\/p>\r\n<p>Dishing control strategies:<\/p>\r\n<ul class=\"jc-ul\">\r\n<li>Increase pad hardness \u2014 harder pads span wider features rather than conforming into them<\/li>\r\n<li>Optimise corrosion inhibitor (BTA) concentration \u2014 adequate BTA protects recessed copper from chemical dissolution<\/li>\r\n<li>Reduce over-polish time \u2014 dishing increases linearly with over-polish beyond the endpoint<\/li>\r\n<li>Apply design-for-CMP (DFCMP) rules \u2014 maximum metal feature width limits enforced in layout to keep dishing within spec<\/li>\r\n<\/ul>\r\n<h3>Erosion: Mechanism and Control<\/h3>\r\n<p><strong>\u6d78\u98df<\/strong> describes the excessive thinning of the inter-metal dielectric in regions of high metal pattern density. In dense arrays of copper lines (e.g., memory array bit-line regions), the locally high metal fraction means the polishing pad pressure is distributed over a smaller dielectric area between the metal lines, causing higher local removal rate in the dielectric. The result is that the dielectric in dense regions is thinner after CMP than in sparse regions, creating a systematic height variation that grows with each metal layer and eventually exceeds the lithography focus budget.<\/p>\r\n<p>Erosion is controlled primarily through DFCMP density rules \u2014 enforcing maximum metal pattern density limits and requiring dummy metal fill in sparse areas to homogenise local pattern density and minimise erosion gradients. Slurry formulation changes that improve planarization efficiency (the rate at which raised features polish faster than recessed features) also reduce erosion.<\/p>\r\n<h2 id=\"residues\">Residues &amp; Post-CMP Contamination<\/h2>\r\n<p>Post-CMP surface residues include all non-native materials present on the wafer surface after polishing and cleaning. They represent a direct threat to the next process step \u2014 deposition adhesion failure, gate dielectric integrity loss, or metal interconnect contamination \u2014 and must be reduced below the contamination budget for the next step before the wafer is released from the CMP module.<\/p>\r\n<h3>Particle Residues<\/h3>\r\n<p>Slurry abrasive particles (silica, ceria, alumina) that remain on the surface after post-CMP cleaning are the most common residue type. Their adhesion force depends on particle size (smaller particles adhere more tenaciously per unit mass), surface charge compatibility between particle and wafer surface (zeta potential mismatch promotes adhesion), and drying effects (particles dried onto the surface form much stronger adhesion bonds than wet particles). The particle removal efficiency (PRE) of the post-CMP cleaning process is the primary control metric. For the full treatment of cleaning chemistry and methods, see <a class=\"jl\" href=\"https:\/\/jeez-semicon.com\/ja\/blog\/Post-CMP-Cleaning-Methods-Challenges-Best-Practices\/\" target=\"_blank\" rel=\"noopener\">Post-CMP Cleaning: Methods, Challenges &amp; Best Practices<\/a>.<\/p>\r\n<h3>Metallic Residues<\/h3>\r\n<p>Dissolved metal ions \u2014 particularly copper, iron (from W CMP oxidisers), and cerium (from STI slurries) \u2014 adsorb onto silicon and oxide surfaces during CMP and must be removed by dedicated acidic cleaning steps. Copper surface contamination above 1\u00d710\u00b9\u2070 atoms\/cm\u00b2 on silicon surfaces is sufficient to degrade transistor performance at advanced nodes. Measurement by total-reflection X-ray fluorescence (TXRF) is the standard method for monitoring metallic surface contamination at these trace levels.<\/p>\r\n<h2 id=\"delamination\">\u30c7\u30e9\u30df\u30cd\u30fc\u30b7\u30e7\u30f3<\/h2>\r\n<p>Film delamination during CMP \u2014 the sudden separation of a film from its substrate at an interface \u2014 is the most catastrophic CMP defect mode. A delamination event can expose the bare substrate across an entire device region, contaminate the CMP tool with debris that affects subsequent wafers, and in severe cases require a full tool clean and re-qualification before production can resume.<\/p>\r\n<p>Delamination is primarily a risk for ultra-low-k (ULK) porous dielectric films (k &lt; 2.2) and for thick metallic films with low adhesion energy at the barrier metal interface. The shear stress applied during polishing must be maintained below the critical adhesion energy (Gc) of the weakest interface in the film stack. At advanced nodes where ULK dielectrics are in the BEOL stack, CMP must use low downforce (&lt;2 psi), soft pads, and slurries with reduced abrasive loading and surfactant additives that lower the coefficient of friction at the polishing interface.<\/p>\r\n<p>For the specific challenges of low-k dielectric CMP at advanced nodes, see our article: <a class=\"jl\" href=\"https:\/\/jeez-semicon.com\/ja\/blog\/CMP-in-Advanced-Nodes-Challenges-at-7nm-5nm-Beyond\/\" target=\"_blank\" rel=\"noopener\">CMP in Advanced Nodes: Challenges at 7nm, 5nm &amp; Beyond<\/a>.<\/p>\r\n<h2 id=\"corrosion\">Copper Corrosion Defects<\/h2>\r\n<p>Copper is an electrochemically active metal that undergoes dissolution in acidic environments \u2014 including the pH 2\u20135 conditions of many copper CMP slurries. When the balance between oxidation rate, mechanical removal, and corrosion inhibition is disrupted, copper corrosion defects appear as pitting, line thinning, surface roughening, or in severe cases complete line dissolution in recessed features.<\/p>\r\n<p>The corrosion rate of copper in a CMP slurry environment is governed by the mixed potential between the anodic copper oxidation reaction and the cathodic reduction of the oxidiser (H\u2082O\u2082). At the mixed potential, the net dissolution rate depends on the kinetics of both reactions and is modulated by the surface coverage of the BTA corrosion inhibitor. Understanding and controlling this electrochemical balance is the core challenge of copper CMP slurry formulation. See the detailed discussion in <a class=\"jl\" href=\"https:\/\/jeez-semicon.com\/ja\/blog\/Copper-CMP-vs-Tungsten-CMP-vs-Oxide-CMP-Full-Comparison\/\" target=\"_blank\" rel=\"noopener\">Copper CMP vs Tungsten CMP vs Oxide CMP: Full Comparison<\/a>.<\/p>\r\n<h2 id=\"detection\">Defect Detection Methods<\/h2>\r\n<div class=\"jc-table-wrap\">\r\n<table class=\"jc-table\">\r\n<thead>\r\n<tr>\r\n<th>\u6b20\u9665\u306e\u7a2e\u985e<\/th>\r\n<th>Detection Tool<\/th>\r\n<th>Detection Principle<\/th>\r\n<th>Sensitivity Limit<\/th>\r\n<\/tr>\r\n<\/thead>\r\n<tbody>\r\n<tr>\r\n<td>Micro-scratches, particles<\/td>\r\n<td>KLA-Tencor Surfscan (bright-field)<\/td>\r\n<td>Laser scattering \u2014 particles and surface defects scatter light off-axis<\/td>\r\n<td>&gt;30 nm particles; &gt;50 nm scratches<\/td>\r\n<\/tr>\r\n<tr>\r\n<td>Micro-scratches (buried)<\/td>\r\n<td>Dark-field inspection (e-beam)<\/td>\r\n<td>E-beam scattering sensitive to sub-surface damage<\/td>\r\n<td>&gt;10 nm buried defects<\/td>\r\n<\/tr>\r\n<tr>\r\n<td>Dishing \/ erosion<\/td>\r\n<td>AFM (atomic force microscopy)<\/td>\r\n<td>Contact or tapping-mode surface height measurement<\/td>\r\n<td>Sub-0.1 nm height resolution<\/td>\r\n<\/tr>\r\n<tr>\r\n<td>Film thickness \/ WIWNU<\/td>\r\n<td>Ellipsometry (KLA F5x, Nova T600)<\/td>\r\n<td>Optical polarisation change on reflection<\/td>\r\n<td>~0.1 nm thickness; ~5 mm spatial resolution<\/td>\r\n<\/tr>\r\n<tr>\r\n<td>Metal film thickness<\/td>\r\n<td>4-point probe \/ eddy current<\/td>\r\n<td>Sheet resistance \u2192 film thickness (for metals)<\/td>\r\n<td>~0.1 \u00c5\/sq sheet resistance sensitivity<\/td>\r\n<\/tr>\r\n<tr>\r\n<td>Metallic surface contamination<\/td>\r\n<td>TXRF (total reflection XRF)<\/td>\r\n<td>X-ray fluorescence from surface-adsorbed metal atoms<\/td>\r\n<td>~10\u2079 atoms\/cm\u00b2 for Cu, Fe, Ni<\/td>\r\n<\/tr>\r\n<tr>\r\n<td>\u30c7\u30e9\u30df\u30cd\u30fc\u30b7\u30e7\u30f3<\/td>\r\n<td>Acoustic emission; bright-field wafer inspection<\/td>\r\n<td>Acoustic signal during CMP; large-area optical scan post-CMP<\/td>\r\n<td>Macroscopic delamination detected in real-time<\/td>\r\n<\/tr>\r\n<\/tbody>\r\n<\/table>\r\n<\/div>\r\n<h2 id=\"rca\">Root Cause Analysis Framework<\/h2>\r\n<p>When a CMP defect excursion is detected, a structured root cause analysis (RCA) is essential to identify the correct corrective action. The following framework guides the investigation from symptom to root cause to fix.<\/p>\r\n<div class=\"jc-rca-box\">\r\n<div class=\"jc-rca-head\">CMP Defect RCA Decision Matrix<\/div>\r\n<div class=\"jc-rca-row\" style=\"background: var(--jeez-light);\">\r\n<div><strong>\u75c7\u72b6<\/strong>Sudden scratch excursion (step-change increase in scratch density)<\/div>\r\n<div><strong>First Check<\/strong>Slurry LPC measurement on retained sample; POU filter status; slurry lot change log; tool configuration changes<\/div>\r\n<div><strong>Likely Root Cause<\/strong>Slurry agglomeration (temperature excursion, freeze-thaw, contamination); POU filter bypass or failure; new slurry lot out-of-spec<\/div>\r\n<\/div>\r\n<div class=\"jc-rca-row\">\r\n<div><strong>\u75c7\u72b6<\/strong>Gradual removal rate drift downward<\/div>\r\n<div><strong>First Check<\/strong>Pad conditioning recipe; conditioner disk condition; pad thickness; pad glazing visual inspection<\/div>\r\n<div><strong>Likely Root Cause<\/strong>Pad glazing due to insufficient conditioning; worn conditioner disk; backing film degradation; end of pad life<\/div>\r\n<\/div>\r\n<div class=\"jc-rca-row\" style=\"background: var(--jeez-light);\">\r\n<div><strong>\u75c7\u72b6<\/strong>High centre-to-edge non-uniformity (WIWNU excursion)<\/div>\r\n<div><strong>First Check<\/strong>Carrier head zone pressure calibration; retaining ring inspection; backing film replacement history<\/div>\r\n<div><strong>Likely Root Cause<\/strong>Retaining ring wear (edge effect); carrier head zone pressure drift; backing film hardening with age<\/div>\r\n<\/div>\r\n<div class=\"jc-rca-row\">\r\n<div><strong>\u75c7\u72b6<\/strong>Post-CMP particle residue increase<\/div>\r\n<div><strong>First Check<\/strong>Cleaning chemistry pH; brush condition; DI water quality; wafer transfer time from polish to first rinse<\/div>\r\n<div><strong>Likely Root Cause<\/strong>pH drift in cleaning chemistry; worn\/contaminated brush; DI water quality degradation; wafer drying before clean<\/div>\r\n<\/div>\r\n<div class=\"jc-rca-row\" style=\"background: var(--jeez-light);\">\r\n<div><strong>\u75c7\u72b6<\/strong>Cu dishing above specification<\/div>\r\n<div><strong>First Check<\/strong>BTA concentration in slurry; over-polish time; oxidiser concentration; pad hardness (recent pad change?)<\/div>\r\n<div><strong>Likely Root Cause<\/strong>Insufficient BTA; excessive over-polish; high oxidiser concentration causing chemical dissolution in recessed features<\/div>\r\n<\/div>\r\n<\/div>\r\n<h2 id=\"yield-improvement\">Yield Improvement Strategies<\/h2>\r\n<p>Systematic CMP yield improvement requires a simultaneous focus on defect prevention (through process optimisation and consumable quality), defect detection (through inspection and metrology density), and defect disposition (through the right process response to out-of-spec lots).<\/p>\r\n<div class=\"jc-callout\">\r\n<div class=\"jc-callout-icon\">\ud83d\udcc8<\/div>\r\n<div class=\"jc-callout-body\">\r\n<h4>Proven yield improvement levers<\/h4>\r\n<p><strong>1. Tighten slurry incoming inspection:<\/strong> Implement 100% LPC measurement on incoming slurry lots. Reject lots above LPC spec before they reach the tool. Cost of rejection is a fraction of the yield loss from a scratch excursion.<br \/><br \/><strong>2. Implement SPC on removal rate and WIWNU:<\/strong> Western Electric rules applied to CMP tool SPC charts catch pad glazing and process drift before they cause yield-impacting events. Mean shift of &gt;1.5\u03c3 should trigger immediate engineering review.<br \/><br \/><strong>3. Dual-source qualification for critical slurries:<\/strong> Single-source dependency creates supply-chain-induced process excursion risk. Qualifying a second slurry supplier with equivalent performance is the most robust supply risk mitigation.<br \/><br \/><strong>4. Optimise post-CMP clean PRE:<\/strong> Measure particle removal efficiency (PRE) monthly on monitor wafers. PRE degradation below 95% indicates brush wear, chemistry drift, or DI water quality issue requiring immediate corrective action.<br \/><br \/><strong>5. DFCMP guideline enforcement:<\/strong> Work with design teams to enforce metal density, feature width, and dummy fill rules that keep dishing and erosion within process capability limits. A 5% adjustment to layout density rules can eliminate systematic erosion hotspots entirely.<\/p>\r\n<\/div>\r\n<\/div>\r\n<div class=\"jc-related\">\r\n<div class=\"jc-related-title\">Related Articles in This Series<\/div>\r\n<div class=\"jc-related-grid\"><a class=\"jc-related-link\" href=\"https:\/\/jeez-semicon.com\/ja\/blog\/cmp-semiconductor-the-complete-guide-to-chemical-mechanical-planarization\/\" target=\"_blank\" rel=\"noopener\"><span class=\"ico\">\ud83d\udcd6<\/span>CMP Complete Guide (Pillar)<\/a> <a class=\"jc-related-link\" href=\"https:\/\/jeez-semicon.com\/ja\/blog\/CMP-Slurry-Guide-Types-Selection-Optimization\/\" target=\"_blank\" rel=\"noopener\"><span class=\"ico\">\ud83e\uddea<\/span>CMP Slurry Guide<\/a> <a class=\"jc-related-link\" href=\"https:\/\/jeez-semicon.com\/ja\/blog\/CMP-Polishing-Pad-Types-Selection-Performance-Guide\/\" target=\"_blank\" rel=\"noopener\"><span class=\"ico\">\ud83d\udcbf<\/span>CMP Polishing Pad Guide<\/a> <a class=\"jc-related-link\" href=\"https:\/\/jeez-semicon.com\/ja\/blog\/Post-CMP-Cleaning-Methods-Challenges-Best-Practices\/\" target=\"_blank\" rel=\"noopener\"><span class=\"ico\">\ud83e\udee7<\/span>Post-CMP Cleaning<\/a> <a class=\"jc-related-link\" href=\"https:\/\/jeez-semicon.com\/ja\/blog\/Copper-CMP-vs-Tungsten-CMP-vs-Oxide-CMP-Full-Comparison\/\" target=\"_blank\" rel=\"noopener\"><span class=\"ico\">\u2696\ufe0f<\/span>Cu vs W vs Oxide CMP<\/a> <a class=\"jc-related-link\" href=\"https:\/\/jeez-semicon.com\/ja\/blog\/CMP-in-Advanced-Nodes-Challenges-at-7nm-5nm-Beyond\/\" target=\"_blank\" rel=\"noopener\"><span class=\"ico\">\ud83d\udd2c<\/span>CMP at Advanced Nodes<\/a><\/div>\r\n<\/div>\r\n<div class=\"jc-cta\">\r\n<h3>Struggling with CMP Defects or Yield Loss?<\/h3>\r\n<p>JEEZ supplies low-LPC CMP slurries and qualified polishing pads engineered for defect-sensitive production environments. Our application team supports yield improvement programs worldwide.<\/p>\r\n<a href=\"https:\/\/jeez-semicon.com\/ja\/contact\/\" target=\"_blank\" rel=\"noopener\">Contact JEEZ \u2192<\/a><\/div>\r\n<div style=\"margin-top: 28px;\"><span class=\"jc-tag\">CMP\u306e\u6b20\u9665<\/span> <span class=\"jc-tag\">Micro-Scratch<\/span> <span class=\"jc-tag\">\u30c7\u30a3\u30c3\u30b7\u30f3\u30b0<\/span> <span class=\"jc-tag\">\u6d78\u98df<\/span> <span class=\"jc-tag\">Yield Improvement<\/span> <span class=\"jc-tag\">Root Cause Analysis<\/span> <span class=\"jc-tag\">LPC<\/span><\/div>\r\n<\/div>","protected":false},"excerpt":{"rendered":"<p>Yield Engineering \u00b7 Updated May 2026 A systematic engineering reference for identifying, classifying, and eliminating CMP-induced defects \u2014 covering scratch defects, dishing, erosion, residues, delamination, and corrosion, with root-cause analysis  &#8230;<\/p>","protected":false},"author":1,"featured_media":2127,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[9,59],"tags":[],"class_list":["post-2125","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-blog","category-industry"],"acf":[],"_links":{"self":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts\/2125","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/comments?post=2125"}],"version-history":[{"count":3,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts\/2125\/revisions"}],"predecessor-version":[{"id":2140,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts\/2125\/revisions\/2140"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/media\/2127"}],"wp:attachment":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/media?parent=2125"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/categories?post=2125"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/tags?post=2125"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}