{"id":2285,"date":"2026-06-09T15:53:35","date_gmt":"2026-06-09T07:53:35","guid":{"rendered":"https:\/\/jeez-semicon.com\/?p=2285"},"modified":"2026-06-09T15:53:35","modified_gmt":"2026-06-09T07:53:35","slug":"single-side-vs-double-side-polishing-which-is-right-for-your-wafer","status":"publish","type":"post","link":"https:\/\/jeez-semicon.com\/ja\/blog\/single-side-vs-double-side-polishing-which-is-right-for-your-wafer\/","title":{"rendered":"Single-Side vs. Double-Side Polishing: Which Is Right for Your Wafer?"},"content":{"rendered":"<style>\n@import url('https:\/\/fonts.googleapis.com\/css2?family=Sora:wght@400;500;600;700;800&family=IBM+Plex+Sans:ital,wght@0,300;0,400;0,500;0,600;1,400&display=swap');\n.jeez-pillar*,.jeez-pillar*::before,.jeez-pillar*::after{box-sizing:border-box;margin:0;padding:0}\n.jeez-pillar{font-family:'IBM Plex Sans',-apple-system,BlinkMacSystemFont,sans-serif;font-size:17px;line-height:1.78;color:#1C2B3A;max-width:900px;margin:0 auto;padding:0 0 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h2{font-size:1.4rem}.jp-cta{padding:2rem 1.5rem}}\n.jeez-pillar [id]{scroll-margin-top:90px}\n<\/style>\n<div class=\"jeez-pillar\">\n<a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/The-Complete-Guide-to-Silicon-Wafer-Polishing\/\" target=\"_blank\" class=\"jp-back\">\u2190 Back to: The Complete Guide to Silicon Wafer Polishing<\/a>\n<div class=\"jp-hero\">\n<div class=\"jp-hero-eyebrow\">JEEZ Semiconductor Materials &nbsp;\u00b7&nbsp; Technical Guide &nbsp;\u00b7&nbsp; Updated June 2026<\/div>\n<p class=\"jp-hero-lead\">A complete technical comparison of SSP and DSP polishing architectures \u2014 covering equipment mechanics, surface quality outputs, global flatness control, application selection criteria, and the hybrid DSP+SSP approach used in 300mm prime-grade production.<\/p>\n<div class=\"jp-hero-meta\">~2,300 words &nbsp;\u00b7&nbsp; 9-minute read &nbsp;\u00b7&nbsp; Published by JEEZ<\/div>\n<\/div>\n<div class=\"jp-toc\"><div class=\"jp-toc-title\">\u76ee\u6b21<\/div><ol><li><a href=\"#intro\">The Architecture Decision<\/a><\/li><li><a href=\"#ssp-how\">How SSP Works<\/a><\/li><li><a href=\"#dsp-how\">How DSP Works<\/a><\/li><li><a href=\"#comparison\">SSP vs. DSP Comparison<\/a><\/li><li><a href=\"#when-to-choose\">When to Choose Each Method<\/a><\/li><li><a href=\"#cost\">Equipment and Cost Considerations<\/a><\/li><li><a href=\"#faq\">\u3088\u304f\u3042\u308b\u8cea\u554f<\/a><\/li><\/ol><\/div>\n\n<section id=\"intro\">\n<h2>The Architecture Decision That Defines Wafer Geometry<\/h2>\n<p>Single-side polishing (SSP) and double-side polishing (DSP) are not merely two different ways to achieve the same result \u2014 they are fundamentally different process architectures with complementary strengths. Choosing between them, or combining them, shapes every geometry and surface quality metric on the finished wafer: TTV, bow, SFQR, Ra, and LPD count. For engineers specifying a new polishing process or evaluating an existing one, understanding the physics behind each approach is essential.<\/p>\n<p>This guide from Jizhi Electronic Technology Co., Ltd. (JEEZ) explains how each method works, compares their outputs across all critical metrics, and provides a practical framework for selecting the right method \u2014 or combination \u2014 for your application. For context on where SSP and DSP fit in the complete polishing process, see our <a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/The-Complete-Guide-to-Silicon-Wafer-Polishing\/\" target=\"_blank\">Complete Guide to Silicon Wafer Polishing<\/a>.<\/p>\n<\/section>\n<hr class=\"jp-hr\">\n\n<section id=\"ssp-how\">\n<h2>How Single-Side Polishing (SSP) Works<\/h2>\n<p>In a single-side polishing tool, the wafer is held face-down on a rotating carrier head. Older SSP tools use a wax-bonding technique: the wafer back surface is bonded to a flat ceramic or glass carrier plate using thermoplastic mounting wax. The bonded assembly is pressed against the rotating polishing pad, and polishing proceeds on the front surface only. Wax mounting provides very rigid, flat wafer support, which is beneficial for achieving excellent local planarity (SFQR) in the contact zone.<\/p>\n<p>Modern single-side polishers \u2014 particularly for 200mm and 300mm wafers \u2014 use vacuum chuck or pneumatic membrane carrier heads rather than wax bonding. A flexible membrane applies a controlled, multi-zone pressure profile to the back of the wafer, pressing it against the pad. The retaining ring surrounding the wafer prevents lateral movement and also applies a separate load to the pad surface just outside the wafer edge, which is critical for edge uniformity control.<\/p>\n<h3>SSP Strengths<\/h3>\n<ul>\n<li>Precise front-surface quality control (Ra, haze, LPD) because the process is optimized entirely for the device face<\/li>\n<li>Multi-zone carrier head enables active compensation for removal rate non-uniformity \u2014 excellent SFQR control<\/li>\n<li>Lower equipment cost than DSP for small-batch or R&amp;D applications<\/li>\n<li>Flexible: can process one wafer at a time or in cassette batches<\/li>\n<li>Suitable as a finish step after DSP in a hybrid process flow<\/li>\n<\/ul>\n<h3>SSP Limitations<\/h3>\n<ul>\n<li>Does not polish the back surface \u2014 back surface quality must be acceptable from DSP or etching<\/li>\n<li>Global flatness (TTV, bow, warp) is primarily inherited from earlier steps, not improved by SSP<\/li>\n<li>Wax mounting (older process): wafer can deform slightly under polishing pressure relative to wax shape \u2014 can introduce local flatness errors<\/li>\n<li>Retaining ring effect creates a challenging edge zone (last 2\u20135 mm of radius) where SFQR is harder to control<\/li>\n<\/ul>\n<\/section>\n<hr class=\"jp-hr\">\n\n<section id=\"dsp-how\">\n<h2>How Double-Side Polishing (DSP) Works<\/h2>\n<p>In a double-side polishing machine, wafers are loaded into thin carrier plates \u2014 typically made from precision-ground stainless steel or engineering ceramic, with wafer-sized holes machined with very tight tolerances on hole diameter and parallelism. A DSP tool has upper and lower platens, each carrying a polishing pad. The carrier plate sits between the platens, and wafers ride freely in the carrier holes, polishing on both surfaces simultaneously.<\/p>\n<p>The critical geometric advantage of DSP is the floating wafer constraint. Because the wafer is not rigidly held \u2014 it floats in the carrier plate hole under approximately equal pressure from both pads \u2014 DSP naturally drives toward a wafer geometry that equalizes the removal rate on both surfaces. Thick regions of the wafer receive slightly more pressure from both sides simultaneously, creating a self-planarizing differential removal that converges the wafer toward a flat, uniform geometry. This mechanism cannot be replicated by SSP polishing each side separately, because SSP introduces a reference-surface dependency that DSP does not have.<\/p>\n<h3>DSP Strengths<\/h3>\n<ul>\n<li>Excellent global flatness control: TTV &lt;0.5 \u03bcm achievable on 300mm prime wafers<\/li>\n<li>Simultaneous front and back polishing \u2192 natural flatness correction through self-planarizing mechanism<\/li>\n<li>High throughput: multiple wafers per carrier plate, multiple carriers per machine cycle<\/li>\n<li>Both surfaces polished to mirror quality in one step<\/li>\n<li>Produces very low bow and warp, important for vacuum chuck adhesion in fab tools<\/li>\n<\/ul>\n<h3>DSP Limitations<\/h3>\n<ul>\n<li>Higher equipment cost and mechanical complexity than SSP<\/li>\n<li>Carrier plates require precise machining and periodic flatness recertification<\/li>\n<li>Cannot independently control front vs. back surface quality<\/li>\n<li>Not suitable as a final finish step for ultra-low LPD or sub-0.1 nm Ra applications \u2014 must be followed by SSP finish polish<\/li>\n<\/ul>\n<\/section>\n<hr class=\"jp-hr\">\n\n<section id=\"comparison\">\n<h2>SSP vs. DSP: Side-by-Side Comparison<\/h2>\n<div class=\"jp-table-wrap\">\n<table class=\"jp-table\">\n<thead><tr><th>Criterion<\/th><th>\u7247\u9762\u7814\u78e8\uff08SSP\uff09<\/th><th>Double-Side Polishing (DSP)<\/th><\/tr><\/thead>\n<tbody>\n<tr><td><strong>Surfaces polished<\/strong><\/td><td>Front only<\/td><td>Front and back simultaneously<\/td><\/tr>\n<tr><td><strong>Global flatness (TTV)<\/strong><\/td><td>Inherited from prior steps; limited correction capability<\/td><td>Excellent correction (&lt;0.5 \u03bcm achievable on 300mm)<\/td><\/tr>\n<tr><td><strong>Local flatness (SFQR)<\/strong><\/td><td>Excellent; multi-zone pressure actively controls SFQR<\/td><td>Good; dependent on carrier plate and pad uniformity<\/td><\/tr>\n<tr><td><strong>\u8868\u9762\u7c97\u3055\uff08Ra\uff09<\/strong><\/td><td>Excellent (&lt;0.08 nm) with soft pad + fine slurry<\/td><td>Good (&lt;0.5 nm); not optimized for ultra-low Ra<\/td><\/tr>\n<tr><td><strong>LPD count<\/strong><\/td><td>Very low (&lt;30 @ 35nm) with optimized finish recipe<\/td><td>Moderate; typically requires SSP finish step to hit spec<\/td><\/tr>\n<tr><td><strong>Bow \/ warp control<\/strong><\/td><td>Limited<\/td><td>Excellent, due to symmetric material removal<\/td><\/tr>\n<tr><td><strong>\u30b9\u30eb\u30fc\u30d7\u30c3\u30c8<\/strong><\/td><td>Lower (one or few wafers per batch)<\/td><td>High (multiple wafers per carrier, per cycle)<\/td><\/tr>\n<tr><td><strong>Equipment complexity<\/strong><\/td><td>Lower<\/td><td>Higher<\/td><\/tr>\n<tr><td><strong>Carrier plate requirement<\/strong><\/td><td>Not required<\/td><td>Required (precision-machined, periodic recertification)<\/td><\/tr>\n<tr><td><strong>Typical application<\/strong><\/td><td>Finish polish; R&amp;D; test\/monitor wafers<\/td><td>Stock removal; prime-grade geometry control<\/td><\/tr>\n<\/tbody>\n<\/table>\n<\/div>\n<\/section>\n<hr class=\"jp-hr\">\n\n<section id=\"when-to-choose\">\n<h2>When to Choose SSP, DSP, or the Hybrid Approach<\/h2>\n<h3>Choose SSP When:<\/h3>\n<ul>\n<li>Producing test, monitor, or specialty wafers where back-surface quality is less critical<\/li>\n<li>The global flatness (TTV, bow) is already adequate from a prior DSP or etch step<\/li>\n<li>Ultra-low LPD count (&lt;30) or sub-0.1 nm Ra is required as the final process output<\/li>\n<li>Processing in R&amp;D, pilot, or small-batch production environments where DSP capital cost is not justified<\/li>\n<li>Performing the finish stage in a DSP+SSP hybrid sequence (see below)<\/li>\n<\/ul>\n<h3>Choose DSP When:<\/h3>\n<ul>\n<li>Manufacturing prime-grade 200mm or 300mm production wafers to tight TTV (&lt;1 \u03bcm) and bow (&lt;40 \u03bcm) specifications<\/li>\n<li>Both front and back surfaces must meet surface quality specifications (double-side polished wafers for specific device applications)<\/li>\n<li>High throughput is required \u2014 DSP processes multiple wafers per cycle<\/li>\n<li>Global flatness correction is needed because lapping and etching have not achieved adequate TTV<\/li>\n<\/ul>\n<h3>The Hybrid DSP + SSP Approach: Industry Standard for 300mm Prime<\/h3>\n<p>In virtually all 300mm prime-grade silicon wafer production as of June 2026, the standard process flow combines both polishing methods in sequence: a DSP step for global flatness and stock removal, followed by an SSP finish step on the front surface only. This hybrid architecture leverages the complementary strength of each method:<\/p>\n<ul>\n<li><strong>DSP handles geometry:<\/strong> The self-planarizing mechanism of DSP controls TTV, bow, and warp to production specification. The DSP step removes most of the silicon that needs to be removed (10\u201320 \u03bcm per side), making the SSP step&#8217;s job purely a surface-quality operation.<\/li>\n<li><strong>SSP handles surface quality:<\/strong> The finish SSP step polishes only 0.5\u20131.5 \u03bcm from the front surface, but eliminates all haze, reduces LPD count to &lt;30, and delivers Ra below 0.1 nm \u2014 performance that a DSP step alone cannot achieve because DSP pad and slurry chemistry are optimized for removal rate and flatness, not for ultra-smooth surface quality.<\/li>\n<\/ul>\n<div class=\"jp-callout\">\nFor engineers working on 300mm uniformity challenges specific to the DSP and SSP steps, see our dedicated guide: <a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/300mm-Silicon-Wafer-Polishing-Challenges-and-Uniformity-Control\/\" target=\"_blank\">300mm Silicon Wafer Polishing: Challenges and Uniformity Control<\/a>.\n<\/div>\n<\/section>\n<hr class=\"jp-hr\">\n\n<section id=\"cost\">\n<h2>Equipment and Cost Considerations<\/h2>\n<p>DSP machines are mechanically more complex \u2014 and correspondingly more expensive \u2014 than SSP tools. The precision-machined carrier plates represent a significant ongoing consumable and maintenance cost: plates must be periodically measured for flatness, repaired, or replaced. Carrier plate qualification (using monitor wafers to verify that plate geometry meets specifications after recertification) consumes production capacity.<\/p>\n<p>SSP machines are simpler and lower in capital cost, but for a given throughput target a production facility may need more SSP tools than DSP tools because SSP processes only the front surface and typically polishes fewer wafers per cycle. For a typical 300mm fab producing prime-grade wafers, the DSP + SSP hybrid requires investment in both machine types, but the combination delivers a total cost of ownership that is lower than attempting to achieve all quality targets with SSP alone \u2014 because DSP can achieve the global flatness specification with a single aggressive slurry and pad combination far more efficiently than SSP ever could.<\/p>\n<p>For a detailed analysis of how process choices affect CMP total cost of ownership, see: <a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/CMP-Cost-Optimization-How-to-Reduce-Slurry-Consumption-and-Improve-Yield\/\" target=\"_blank\">CMP Cost Optimization: How to Reduce Slurry Consumption and Improve Yield<\/a>.<\/p>\n<\/section>\n\n<div class=\"jp-related\"><div class=\"jp-related-title\">Related Articles in This Series<\/div><div class=\"jp-related-links\">\n<a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/The-Complete-Guide-to-Silicon-Wafer-Polishing\/\" target=\"_blank\" class=\"jp-rl\"><span class=\"jp-rl-icon\">\ud83d\udcd8<\/span><div><strong>The Complete Guide to Silicon Wafer Polishing<\/strong><span>The full pillar guide \u2014 every dimension of silicon wafer CMP.<\/span><\/div><\/a>\n<a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/Silicon-Wafer-Polishing-Process-Step-by-Step-from-Lapping-to-Final-Polish\/\" target=\"_blank\" class=\"jp-rl\"><span class=\"jp-rl-icon\">\u2699\ufe0f<\/span><div><strong>Silicon Wafer Polishing Process: Step-by-Step from Lapping to Final Polish<\/strong><span>How SSP and DSP fit into the complete polishing sequence from lapping to inspection.<\/span><\/div><\/a>\n<a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/300mm-Silicon-Wafer-Polishing-Challenges-and-Uniformity-Control\/\" target=\"_blank\" class=\"jp-rl\"><span class=\"jp-rl-icon\">\ud83c\udfaf<\/span><div><strong>300mm Silicon Wafer Polishing: Challenges and Uniformity Control<\/strong><span>WIWNU control, multi-zone pressure, and retaining ring optimization for 300mm wafers.<\/span><\/div><\/a>\n<a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/CMP-Cost-Optimization-How-to-Reduce-Slurry-Consumption-and-Improve-Yield\/\" target=\"_blank\" class=\"jp-rl\"><span class=\"jp-rl-icon\">\ud83d\udcb0<\/span><div><strong>CMP Cost Optimization: How to Reduce Slurry Consumption and Improve Yield<\/strong><span>How DSP vs. SSP process architecture affects total CMP cost.<\/span><\/div><\/a>\n<\/div><\/div>\n<hr class=\"jp-hr\">\n<section id=\"faq\">\n<h2>\u3088\u304f\u3042\u308b\u8cea\u554f<\/h2>\n<div class=\"jp-faq\"><div class=\"jp-faq-item\"><div class=\"jp-faq-q\" onclick=\"jeezToggleFaq(this)\">Which is better for 300mm silicon wafer manufacturing \u2014 SSP or DSP?<span class=\"jp-faq-icon\">+<\/span><\/div><div class=\"jp-faq-a\">Neither alone is sufficient for 300mm prime-grade production. DSP provides the global flatness (TTV &lt;1 \u03bcm, bow &lt;40 \u03bcm) required by lithography tools, but cannot achieve the final LPD count and surface roughness specifications that device fabs require. SSP provides the final surface quality (Ra &lt;0.1 nm, LPD &lt;30) but does not correct TTV or bow. The industry standard for 300mm prime is a DSP+SSP hybrid: DSP for geometry, followed by SSP finish polish for surface quality.<\/div><\/div>\n<div class=\"jp-faq-item\"><div class=\"jp-faq-q\" onclick=\"jeezToggleFaq(this)\">Can SSP achieve good TTV (total thickness variation)?<span class=\"jp-faq-icon\">+<\/span><\/div><div class=\"jp-faq-a\">SSP has limited TTV correction capability. Because only one surface is polished and the wafer is held against a carrier head rather than floating freely, SSP removal rate non-uniformity can introduce thickness variation rather than correcting it. SSP is not an effective tool for TTV improvement. TTV control must be achieved in the DSP step or, for moderate correction, through the lapping and etching stages.<\/div><\/div>\n<div class=\"jp-faq-item\"><div class=\"jp-faq-q\" onclick=\"jeezToggleFaq(this)\">What are carrier plates in DSP and why do they need recertification?<span class=\"jp-faq-icon\">+<\/span><\/div><div class=\"jp-faq-a\">Carrier plates are thin, precisely machined discs with wafer-sized holes through which silicon wafers ride during double-side polishing. The plates define the wafer&#8217;s kinematic environment between the upper and lower polishing platens. Over time, the carrier plate holes wear slightly larger, the plate surface develops flatness deviation from polishing loads, and surface contamination builds up. Periodic recertification \u2014 measuring plate flatness, inspecting hole diameters, and cleaning \u2014 ensures that carrier plate geometry does not introduce TTV errors into wafers.<\/div><\/div>\n<div class=\"jp-faq-item\"><div class=\"jp-faq-q\" onclick=\"jeezToggleFaq(this)\">Is wax mounting still used in SSP for production silicon wafers?<span class=\"jp-faq-icon\">+<\/span><\/div><div class=\"jp-faq-a\">Wax mounting \u2014 bonding the wafer back surface to a flat carrier plate with thermoplastic mounting wax \u2014 is largely obsolete for 200mm and 300mm production SSP. It has been replaced by vacuum chuck and pneumatic membrane carrier head technology, which provides more precise, non-contact wafer retention and enables multi-zone pressure control for WIWNU correction. Wax mounting is still used in some R&#038;D, specialty substrate, and very small wafer (&lt;100mm) applications.<\/div><\/div>\n<div class=\"jp-faq-item\"><div class=\"jp-faq-q\" onclick=\"jeezToggleFaq(this)\">How does the retaining ring in SSP affect edge flatness?<span class=\"jp-faq-icon\">+<\/span><\/div><div class=\"jp-faq-a\">The retaining ring surrounds the wafer in the SSP carrier head and applies a separate, independently controllable downforce on the polishing pad just outside the wafer edge. This ring load creates a local variation in pad thickness and contact pressure in the edge zone (typically the outermost 2\u20135 mm of wafer radius), producing either an edge-fast or edge-slow removal rate signature. Proper tuning of retaining ring pressure is critical for SFQR at edge sites and for minimizing the edge exclusion zone.<\/div><\/div>\n<\/div>\n<\/section>\n<hr class=\"jp-hr\">\n<div class=\"jp-cta\"><h2>Selecting the Right CMP Slurry for Your Polishing Architecture<\/h2><p>JEEZ formulates dedicated slurries for both DSP stock-removal and SSP finish-polish stages. Whether you run a DSP-only, SSP-only, or hybrid process, our technical team can recommend the right product and parameters for your equipment and specification.<\/p>\n<a href=\"https:\/\/jeez-semicon.com\/ja\/contact\/\" target=\"_blank\" class=\"jp-cta-btn\">Contact JEEZ Technical Team<\/a>\n<\/div>\n<\/div>\n<script type=\"application\/ld+json\">{\"@context\":\"https:\/\/schema.org\",\"@type\":\"FAQPage\",\"mainEntity\":[{\"@type\":\"Question\",\"name\":\"Which is better for 300mm silicon wafer manufacturing \u2014 SSP or DSP?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"Neither alone is sufficient for 300mm prime-grade production. DSP provides the global flatness (TTV &lt;1 \u03bcm, bow &lt;40 \u03bcm) required by lithography tools, but cannot achieve the final LPD count and surface roughness specifications that device fabs require. SSP provides the final surface quality (Ra &lt;0.1 nm, LPD &lt;30) but does not correct TTV or bow. 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The plates define the wafer's kinematic environment between the upper and lower polishing platens. Over time, the carrier plate holes wear slightly larger, the plate surface develops flatness deviation from polishing loads, and surface contamination builds up. Periodic recertification \u2014 measuring plate flatness, inspecting hole diameters, and cleaning \u2014 ensures that carrier plate geometry does not introduce TTV errors into wafers.\"}},{\"@type\":\"Question\",\"name\":\"Is wax mounting still used in SSP for production silicon wafers?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"Wax mounting \u2014 bonding the wafer back surface to a flat carrier plate with thermoplastic mounting wax \u2014 is largely obsolete for 200mm and 300mm production SSP. It has been replaced by vacuum chuck and pneumatic membrane carrier head technology, which provides more precise, non-contact wafer retention and enables multi-zone pressure control for WIWNU correction. Wax mounting is still used in some R&D, specialty substrate, and very small wafer (&lt;100mm) applications.\"}},{\"@type\":\"Question\",\"name\":\"How does the retaining ring in SSP affect edge flatness?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"The retaining ring surrounds the wafer in the SSP carrier head and applies a separate, independently controllable downforce on the polishing pad just outside the wafer edge. This ring load creates a local variation in pad thickness and contact pressure in the edge zone (typically the outermost 2\u20135 mm of wafer radius), producing either an edge-fast or edge-slow removal rate signature. Proper tuning of retaining ring pressure is critical for SFQR at edge sites and for minimizing the edge exclusion zone.\"}}]}<\/script>\n<script>\nfunction jeezToggleFaq(el){\n  var a=el.nextElementSibling,o=a.classList.contains('jp-open');\n  document.querySelectorAll('.jp-faq-a').forEach(function(x){x.classList.remove('jp-open')});\n  document.querySelectorAll('.jp-faq-q').forEach(function(x){x.classList.remove('jp-open')});\n  if(!o){a.classList.add('jp-open');el.classList.add('jp-open');}\n}\n<\/script>","protected":false},"excerpt":{"rendered":"<p>\u2190 Back to: The Complete Guide to Silicon Wafer Polishing JEEZ Semiconductor Materials &nbsp;\u00b7&nbsp; Technical Guide &nbsp;\u00b7&nbsp; Updated June 2026 A complete technical comparison of SSP and DSP polishing architectures  &#8230;<\/p>","protected":false},"author":1,"featured_media":2287,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[9,59],"tags":[],"class_list":["post-2285","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-blog","category-industry"],"acf":[],"_links":{"self":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts\/2285","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/comments?post=2285"}],"version-history":[{"count":2,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts\/2285\/revisions"}],"predecessor-version":[{"id":2288,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts\/2285\/revisions\/2288"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/media\/2287"}],"wp:attachment":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/media?parent=2285"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/categories?post=2285"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/tags?post=2285"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}