{"id":2297,"date":"2026-06-09T15:53:49","date_gmt":"2026-06-09T07:53:49","guid":{"rendered":"https:\/\/jeez-semicon.com\/?p=2297"},"modified":"2026-06-09T15:53:49","modified_gmt":"2026-06-09T07:53:49","slug":"how-to-achieve-sub-nm-surface-roughness-in-silicon-wafer-cmp","status":"publish","type":"post","link":"https:\/\/jeez-semicon.com\/ja\/blog\/how-to-achieve-sub-nm-surface-roughness-in-silicon-wafer-cmp\/","title":{"rendered":"How to Achieve Sub-nm Surface Roughness in Silicon Wafer CMP"},"content":{"rendered":"<style>\n@import url('https:\/\/fonts.googleapis.com\/css2?family=Sora:wght@400;500;600;700;800&family=IBM+Plex+Sans:ital,wght@0,300;0,400;0,500;0,600;1,400&display=swap');\n.jeez-pillar*,.jeez-pillar*::before,.jeez-pillar*::after{box-sizing:border-box;margin:0;padding:0}\n.jeez-pillar{font-family:'IBM Plex Sans',-apple-system,BlinkMacSystemFont,sans-serif;font-size:17px;line-height:1.78;color:#1C2B3A;max-width:900px;margin:0 auto;padding:0 0 3rem}\n.jeez-pillar h2,.jeez-pillar h3,.jeez-pillar h4{font-family:'Sora',-apple-system,sans-serif;line-height:1.25}\n.jeez-pillar h2{font-size:1.85rem;font-weight:700;color:#07193A;margin:3rem 0 1.1rem;padding-bottom:.65rem;border-bottom:3px solid #1553A0}\n.jeez-pillar h3{font-size:1.2rem;font-weight:600;color:#1553A0;margin:2rem 0 .75rem}\n.jeez-pillar p{margin-bottom:1.3rem}.jeez-pillar p:last-child{margin-bottom:0}\n.jeez-pillar ul,.jeez-pillar ol{padding-left:1.5rem;margin-bottom:1.3rem}\n.jeez-pillar li{margin-bottom:.5rem}\n.jeez-pillar strong{font-weight:600;color:#07193A}\n.jeez-pillar a{color:#1553A0;text-decoration:none;border-bottom:1px solid rgba(21,83,160,.35);transition:color .18s,border-color .18s}\n.jeez-pillar a:hover{color:#007B6E;border-bottom-color:#007B6E}\n.jp-back{display:inline-flex;align-items:center;gap:.5rem;font-family:'Sora',sans-serif;font-size:.82rem;font-weight:600;color:#1553A0;background:#EEF4FF;border:1px solid #C5D6F5;border-radius:6px;padding:.4rem .9rem;text-decoration:none;border-bottom:none;margin-bottom:1.5rem;transition:background .18s}\n.jp-back:hover{background:#1553A0;color:#fff}\n.jp-hero{background:linear-gradient(135deg,#071B40 0%,#1553A0 55%,#0086A0 100%);color:#fff;padding:3rem 2.75rem 2.75rem;border-radius:14px;margin-bottom:2.5rem;position:relative;overflow:hidden}\n.jp-hero::before{content:'';position:absolute;top:-50px;right:-50px;width:240px;height:240px;border:48px solid rgba(255,255,255,.06);border-radius:50%;pointer-events:none}\n.jp-hero::after{content:'';position:absolute;bottom:-70px;right:80px;width:320px;height:320px;border:48px solid rgba(255,255,255,.04);border-radius:50%;pointer-events:none}\n.jp-hero-eyebrow{font-family:'Sora',sans-serif;font-size:.72rem;font-weight:600;letter-spacing:.18em;text-transform:uppercase;color:rgba(255,255,255,.6);margin-bottom:.85rem}\n.jp-hero h1{font-family:'Sora',sans-serif;font-size:2.1rem;font-weight:800;line-height:1.15;color:#fff;margin-bottom:1.1rem}\n.jp-hero-lead{font-size:1rem;color:rgba(255,255,255,.85);max-width:660px;line-height:1.72;margin-bottom:1.5rem}\n.jp-hero-meta{display:flex;gap:1.75rem;flex-wrap:wrap;font-size:.8rem;color:rgba(255,255,255,.55);font-family:'Sora',sans-serif}\n.jp-toc{background:#EEF4FF;border:1px solid #C5D6F5;border-left:5px solid #1553A0;border-radius:0 10px 10px 0;padding:1.6rem 2rem 1.6rem 1.75rem;margin:0 0 2.75rem}\n.jp-toc-title{font-family:'Sora',sans-serif;font-size:.78rem;font-weight:700;letter-spacing:.14em;text-transform:uppercase;color:#07193A;margin-bottom:1rem}\n.jp-toc ol{column-count:2;column-gap:2.5rem;margin:0;padding-left:1.25rem}\n.jp-toc li{margin-bottom:.45rem;break-inside:avoid;font-size:.88rem}\n.jp-toc a{color:#1553A0;border-bottom:none;font-weight:400;line-height:1.5}\n.jp-toc a:hover{text-decoration:underline;color:#007B6E}\n@media(max-width:620px){.jp-toc ol{column-count:1}}\n.jp-stats{display:grid;grid-template-columns:repeat(auto-fit,minmax(170px,1fr));gap:1rem;margin:1.75rem 0}\n.jp-stat{background:#07193A;color:#fff;border-radius:10px;padding:1.35rem 1.25rem;text-align:center}\n.jp-stat-value{font-family:'Sora',sans-serif;font-size:1.9rem;font-weight:700;color:#6DB8FF;display:block;line-height:1;margin-bottom:.45rem}\n.jp-stat-label{font-size:.78rem;color:rgba(255,255,255,.65);line-height:1.45}\n.jp-callout{padding:1.2rem 1.5rem;border-radius:0 10px 10px 0;border-left:4px solid #1553A0;background:#EEF4FF;margin:1.75rem 0;font-size:.93rem;line-height:1.7}\n.jp-callout.teal{background:#E0F5F1;border-color:#007B6E}\n.jp-callout.amber{background:#FFF8E6;border-color:#D97706}\n.jp-callout.slate{background:#F1F5F9;border-color:#475569}\n.jp-steps{list-style:none;padding:0;margin:1.5rem 0;counter-reset:jp-step}\n.jp-steps li{counter-increment:jp-step;position:relative;padding:1.1rem 1.25rem 1.1rem 3.75rem;background:#F7FAFD;border:1px solid #E2EAF4;border-radius:10px;margin-bottom:.85rem}\n.jp-steps li::before{content:counter(jp-step);position:absolute;left:1rem;top:50%;transform:translateY(-50%);width:30px;height:30px;background:#1553A0;color:#fff;border-radius:50%;display:flex;align-items:center;justify-content:center;font-size:.8rem;font-weight:700;font-family:'Sora',sans-serif}\n.jp-steps li strong{display:block;font-family:'Sora',sans-serif;font-size:.95rem;color:#07193A;margin-bottom:.35rem}\n.jp-compare{display:grid;grid-template-columns:1fr 1fr;gap:1.1rem;margin:1.5rem 0}\n@media(max-width:600px){.jp-compare{grid-template-columns:1fr}}\n.jp-compare-box{background:#F7FAFD;border:1px solid #E2EAF4;border-top:4px solid #1553A0;border-radius:0 0 10px 10px;padding:1.25rem}\n.jp-compare-box:nth-child(2){border-top-color:#007B6E}\n.jp-compare-box h4{font-family:'Sora',sans-serif;font-size:.95rem;font-weight:700;color:#07193A;margin-bottom:.85rem}\n.jp-compare-box ul{padding-left:1.15rem;margin:0}\n.jp-compare-box li{font-size:.875rem;color:#334155;margin-bottom:.45rem}\n.jp-table-wrap{overflow-x:auto;margin:1.75rem 0;border-radius:10px;border:1px solid #E2EAF4;box-shadow:0 1px 4px rgba(21,83,160,.06)}\n.jp-table{width:100%;border-collapse:collapse;font-size:.865rem;background:#fff}\n.jp-table thead th{background:#07193A;color:#fff;padding:11px 15px;text-align:left;font-family:'Sora',sans-serif;font-weight:600;font-size:.77rem;letter-spacing:.05em;text-transform:uppercase;white-space:nowrap}\n.jp-table td{padding:10px 15px;border-bottom:1px solid #EEF2F8;vertical-align:top;line-height:1.55}\n.jp-table tr:last-child td{border-bottom:none}\n.jp-table tbody tr:nth-child(even) td{background:#F7FAFD}\n.jp-readmore{display:inline-flex;align-items:center;gap:7px;font-family:'Sora',sans-serif;font-size:.86rem;font-weight:600;color:#1553A0;border:none!important;text-decoration:none;padding:.55rem 1.1rem;background:#EEF4FF;border-radius:6px;margin-top:.75rem;transition:background .18s,color .18s}\n.jp-readmore:hover{background:#1553A0;color:#fff!important}\n.jp-readmore::after{content:'\u2192'}\n.jp-hr{border:none;border-top:1px solid #E2EAF4;margin:2.75rem 0}\n.jp-related{background:#F7FAFD;border:1px solid #E2EAF4;border-radius:12px;padding:1.75rem 2rem;margin:2.5rem 0}\n.jp-related-title{font-family:'Sora',sans-serif;font-size:.78rem;font-weight:700;letter-spacing:.14em;text-transform:uppercase;color:#07193A;margin-bottom:1.1rem}\n.jp-related-links{display:flex;flex-direction:column;gap:.6rem}\n.jp-rl{display:flex;align-items:flex-start;gap:.75rem;padding:.7rem .9rem;background:#fff;border:1px solid #E2EAF4;border-radius:8px;text-decoration:none;border-bottom:none;color:#1C2B3A;transition:border-color .18s,box-shadow .18s}\n.jp-rl:hover{border-color:#1553A0;box-shadow:0 2px 8px rgba(21,83,160,.1)}\n.jp-rl-icon{font-size:1.1rem;flex-shrink:0;margin-top:1px}\n.jp-rl strong{display:block;font-family:'Sora',sans-serif;font-size:.88rem;font-weight:600;color:#07193A;margin-bottom:2px}\n.jp-rl span{font-size:.8rem;color:#5A6A7A}\n.jp-faq{margin:1.5rem 0}\n.jp-faq-item{border:1px solid #E2EAF4;border-radius:10px;margin-bottom:.75rem;overflow:hidden}\n.jp-faq-q{padding:1.05rem 1.35rem;font-family:'Sora',sans-serif;font-size:.93rem;font-weight:600;color:#07193A;background:#F7FAFD;cursor:pointer;display:flex;justify-content:space-between;align-items:center;user-select:none;gap:1rem;transition:background .15s}\n.jp-faq-q:hover{background:#EEF4FF}\n.jp-faq-icon{flex-shrink:0;width:24px;height:24px;background:#1553A0;color:#fff;border-radius:50%;display:flex;align-items:center;justify-content:center;font-size:1.1rem;line-height:1;transition:transform .2s,background .2s}\n.jp-faq-q.jp-open .jp-faq-icon{transform:rotate(45deg);background:#007B6E}\n.jp-faq-a{display:none;padding:1.1rem 1.35rem;font-size:.91rem;line-height:1.75;color:#2D3F50;background:#fff;border-top:1px solid #E2EAF4}\n.jp-faq-a.jp-open{display:block}\n.jp-cta{background:linear-gradient(135deg,#071B40,#1553A0 70%,#006DAB);color:#fff;padding:2.75rem 2.5rem;border-radius:14px;text-align:center;margin:3rem 0 0}\n.jp-cta h2{font-family:'Sora',sans-serif;font-size:1.5rem;font-weight:700;color:#fff;border:none;margin:0 0 .85rem;padding:0}\n.jp-cta p{color:rgba(255,255,255,.82);font-size:1rem;max-width:580px;margin:0 auto 1.75rem}\n.jp-cta-btn{display:inline-block;background:#fff;color:#1553A0!important;padding:.85rem 2.25rem;border-radius:7px;font-family:'Sora',sans-serif;font-weight:700;font-size:.95rem;text-decoration:none;border:none!important;transition:background .2s,transform .2s}\n.jp-cta-btn:hover{background:#D4E7FF;transform:translateY(-2px);color:#07193A!important}\n@media(max-width:640px){.jp-hero{padding:2rem 1.5rem}.jp-hero h1{font-size:1.6rem}.jeez-pillar h2{font-size:1.4rem}.jp-cta{padding:2rem 1.5rem}}\n.jeez-pillar [id]{scroll-margin-top:90px}\n<\/style>\n<div class=\"jeez-pillar\">\n<a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/The-Complete-Guide-to-Silicon-Wafer-Polishing\/\" target=\"_blank\" class=\"jp-back\">\u2190 Back to: The Complete Guide to Silicon Wafer Polishing<\/a>\n<div class=\"jp-hero\">\n<div class=\"jp-hero-eyebrow\">JEEZ Semiconductor Materials &nbsp;\u00b7&nbsp; Technical Guide &nbsp;\u00b7&nbsp; Updated June 2026<\/div>\n<p class=\"jp-hero-lead\">A process engineering guide to reaching Ra below 0.1 nm on polished silicon wafers \u2014 covering the physics of why roughness matters, the five controllable process levers, recipe design principles, measurement methodology, and common mistakes.<\/p>\n<div class=\"jp-hero-meta\">~2,600 words &nbsp;\u00b7&nbsp; 11-minute read &nbsp;\u00b7&nbsp; Published by JEEZ<\/div>\n<\/div>\n<div class=\"jp-toc\"><div class=\"jp-toc-title\">\u76ee\u6b21<\/div><ol><li><a href=\"#intro\">The Atomic-Scale Challenge<\/a><\/li><li><a href=\"#why-it-matters\">Why Sub-nm Roughness Matters<\/a><\/li><li><a href=\"#metrics\">Surface Roughness Metrics<\/a><\/li><li><a href=\"#five-levers\">The Five Process Levers<\/a><\/li><li><a href=\"#recipe\">Finish Polish Recipe Design<\/a><\/li><li><a href=\"#pitfalls\">Common Process Mistakes<\/a><\/li><li><a href=\"#faq\">\u3088\u304f\u3042\u308b\u8cea\u554f<\/a><\/li><\/ol><\/div>\n\n<section id=\"intro\">\n<h2>The Atomic-Scale Challenge in Silicon Wafer Polishing<\/h2>\n<p>Achieving a root-mean-square surface roughness (Rq) below 0.1 nm on a polished silicon wafer front surface is one of the most demanding specifications in all of industrial surface engineering. At this scale, the allowable roughness envelope corresponds to the displacement of fewer than one silicon atomic layer \u2014 the (001) Si lattice spacing is 0.136 nm, and a surface with Rq = 0.1 nm is varying by less than one atomic step on average across its measured area. Reaching this level consistently across an entire 300mm wafer in production, lot after lot, requires simultaneous optimization of at least five interdependent process variables.<\/p>\n<p>This guide from Jizhi Electronic Technology Co., Ltd. (JEEZ) explains why sub-nanometer roughness matters, defines the metrics used to characterize it, identifies the five process levers that control it, and provides guidance on measurement and common process pitfalls. It is part of the JEEZ <a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/The-Complete-Guide-to-Silicon-Wafer-Polishing\/\" target=\"_blank\">Silicon Wafer Polishing knowledge base<\/a>.<\/p>\n<div class=\"jp-stats\">\n<div class=\"jp-stat\"><span class=\"jp-stat-value\">0.136 nm<\/span><span class=\"jp-stat-label\">Si(001) monolayer step height \u2014 the physical scale of sub-nm roughness specification<\/span><\/div>\n<div class=\"jp-stat\"><span class=\"jp-stat-value\">&lt;0.08 nm<\/span><span class=\"jp-stat-label\">Ra target for 300mm prime silicon final polish (JEEZ FP-series slurry)<\/span><\/div>\n<div class=\"jp-stat\"><span class=\"jp-stat-value\">0.5\u20131.0 psi<\/span><span class=\"jp-stat-label\">Typical carrier head pressure range for sub-nm roughness finish CMP<\/span><\/div>\n<\/div>\n<\/section>\n<hr class=\"jp-hr\">\n\n<section id=\"why-it-matters\">\n<h2>Why Sub-Nanometer Surface Roughness Matters for Device Manufacturing<\/h2>\n<p>Surface roughness on a silicon wafer is not merely an aesthetic quality metric \u2014 it has direct, measurable consequences for device electrical performance and yield at multiple process steps:<\/p>\n<ul>\n<li><strong>Gate dielectric integrity:<\/strong> When a gate oxide (SiO\u2082 or high-k HfO\u2082) is grown on a rough silicon surface, the oxide thickness varies locally in proportion to the underlying surface topography. At sub-5 nm oxide equivalent thickness (EOT), even 0.2 nm of surface roughness represents a 4% local oxide thickness variation \u2014 enough to shift the local breakdown voltage and generate measurable gate leakage current. The ITRS roadmap has consistently tightened gate oxide specifications as EOT scales downward.<\/li>\n<li><strong>Epitaxial layer defects:<\/strong> For epi-silicon substrates \u2014 wafers that receive a device-quality epitaxial silicon layer before shipment \u2014 the epitaxial layer inherits the roughness of the substrate surface on which it grows. Rough substrate surfaces nucleate misfit dislocations, stacking faults, and local thickness variations in the epi layer. An epi-ready substrate requires Ra below 0.1 nm to support dislocation-free epitaxial growth at industrial rates.<\/li>\n<li><strong>Photolithography and CMP overlay:<\/strong> Roughness at spatial wavelengths in the 1\u201310 \u03bcm range (contributing to haze) scatters alignment laser light and reduces signal-to-noise ratio in overlay metrology. This effect becomes significant when haze exceeds ~0.05 ppm on deep-UV lithography tools.<\/li>\n<li><strong>Surface inspection noise floor:<\/strong> Haze \u2014 the diffuse scattered light from micro-roughness \u2014 raises the background signal on laser-scanning surface inspection tools. When haze exceeds ~0.03 ppm, it begins to mask real LPD events below the detection threshold, effectively blinding the inspection to small particles and pits that could cause device failures.<\/li>\n<\/ul>\n<\/section>\n<hr class=\"jp-hr\">\n\n<section id=\"metrics\">\n<h2>Surface Roughness Metrics: Ra, Rq, Rz, and Power Spectral Density<\/h2>\n<p>Four metrics are most relevant to silicon wafer CMP quality control:<\/p>\n<div class=\"jp-table-wrap\">\n<table class=\"jp-table\">\n<thead><tr><th>\u30e1\u30fc\u30c8\u30eb<\/th><th>Definition<\/th><th>Sensitivity<\/th><th>Measurement Tool<\/th><\/tr><\/thead>\n<tbody>\n<tr><td><strong>Ra<\/strong><\/td><td>Arithmetic mean of absolute height deviations from the mean plane<\/td><td>Equal weight to all height events; less sensitive to rare peaks<\/td><td>AFM (1\u00d71 \u03bcm scan), optical profilometer<\/td><\/tr>\n<tr><td><strong>Rq (RMS)<\/strong><\/td><td>Root-mean-square of height deviations; equivalent to 1\u03c3 of the height distribution<\/td><td>More sensitive to rare large peaks than Ra; typically ~25% larger than Ra for Gaussian surfaces<\/td><td>AFM (same scan)<\/td><\/tr>\n<tr><td><strong>Rz<\/strong><\/td><td>Average of the five largest peak-to-valley heights in the measurement area<\/td><td>Sensitive to worst-case events; less commonly specified for silicon CMP<\/td><td>AFM or WLI<\/td><\/tr>\n<tr><td><strong>Power spectral density (PSD)<\/strong><\/td><td>Decomposition of roughness into spatial frequency components; shows which length scales contribute most to total roughness<\/td><td>Full-frequency characterization; identifies whether roughness is atomic-scale or process-scale<\/td><td>AFM + Fourier analysis<\/td><\/tr>\n<tr><td><strong>Haze (ppm)<\/strong><\/td><td>Diffuse scattered light ratio; related to PSD in the 0.1\u201310 \u03bcm wavelength range<\/td><td>Fast, non-contact proxy for mid-spatial-frequency roughness; standard production metric<\/td><td>KLA Surfscan SP3\/SP5<\/td><\/tr>\n<\/tbody>\n<\/table>\n<\/div>\n<p>For silicon wafer prime-grade production, Ra and Rq are the primary roughness specifications, measured by AFM. Haze is the primary in-line production control parameter because it can be measured on every wafer during surface inspection without a separate AFM tool. The relationship between haze (ppm) and Rq (nm) is not fixed \u2014 it depends on the spatial frequency composition of the roughness \u2014 but haze &lt;0.03 ppm typically corresponds to Rq &lt;0.10 nm for standard silicon finish-polish conditions. For a broader treatment of all wafer flatness and roughness metrics, see: <a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/Why-Silicon-Wafer-Flatness-Matters-TTV-SFQR-and-Nanotopography-Explained\/\" target=\"_blank\">Why Silicon Wafer Flatness Matters: TTV, SFQR, and Nanotopography Explained<\/a>.<\/p>\n<\/section>\n<hr class=\"jp-hr\">\n\n<section id=\"five-levers\">\n<h2>The Five Process Levers for Sub-Nanometer Roughness<\/h2>\n<p>Achieving Rq below 0.10 nm consistently requires simultaneous optimization of five interdependent process variables. Improving one in isolation, without adjusting the others, rarely delivers the target roughness.<\/p>\n<h3>Lever 1: Abrasive Concentration \u2014 Less Is More<\/h3>\n<p>Counterintuitively, reducing the abrasive concentration in the finish polish slurry improves surface roughness. At concentrations above ~2 wt%, the mechanical component of material removal (abrasive particles physically contacting and abrading the surface) is significant enough to leave a measurable micro-roughness imprint. As abrasive concentration is reduced below 1 wt%, the chemical component (alkaline dissolution of the SiO\u2082\u00b7nH\u2082O surface layer) increasingly dominates, and chemical dissolution is a far smoother, more isotropic material removal mechanism than mechanical abrasion. The limiting case \u2014 abrasive-free alkaline polishing \u2014 delivers the absolute smoothest surfaces achievable in CMP.<\/p>\n<h3>Lever 2: Particle Size \u2014 Smaller Is Smoother<\/h3>\n<p>Particle size affects roughness through two mechanisms. First, larger particles create larger asperity contacts and leave proportionally larger material removal events per particle-surface interaction. Second, larger particles are more likely to mechanically override the soft SiO\u2082\u00b7nH\u2082O surface layer and contact the hard crystalline silicon beneath, which increases micro-roughness. Final polish slurries with D50 of 20\u201330 nm consistently deliver lower Ra than slurries with D50 of 60\u201380 nm at the same abrasive concentration and process conditions. JEEZ FP-series finish slurries use 25\u201335 nm D50 colloidal silica specifically optimized for Ra performance.<\/p>\n<h3>Lever 3: Soft Polishing Pad \u2014 Conformality Over Flatness<\/h3>\n<p>Pad hardness governs how the load is distributed at the micro-scale. A hard pad (Shore D 65, IC1000-type) distributes load through discrete high asperities that contact the wafer at localized high-pressure points \u2014 creating high local material removal rates at those contact zones that produce micro-roughness. A soft pad (Shore A 50\u201360, Suba-type) conforms to the wafer surface at the micro-scale, distributing load over a much larger number of lower-pressure contacts and enabling the chemical component to dominate. The trade-off is that soft pads sacrifice the planarizing behavior that is needed for TTV and SFQR control \u2014 which is why the finish-polish step uses a soft pad only after DSP has already achieved global flatness with a hard pad.<\/p>\n<h3>Lever 4: Low Applied Pressure \u2014 Chemistry Takes Over<\/h3>\n<p>Applied pressure (the downforce of the carrier head membrane on the wafer against the pad) controls the balance between mechanical and chemical material removal. At high pressure (&gt;3 psi), the Preston equation is dominated by the pressure\u00d7velocity product, and mechanical abrasion is the primary removal mechanism \u2014 which is fast but rough. Reducing pressure to below 1 psi (6.9 kPa) in the finish-polish step slows removal rate substantially but shifts the removal mechanism balance strongly toward chemistry. The rate-limiting step becomes the formation and chemical dissolution of the SiO\u2082\u00b7nH\u2082O layer \u2014 a mechanism that produces atomically smooth removal across the entire surface rather than localized mechanical events.<\/p>\n<h3>Lever 5: pH Optimization \u2014 Narrow Window, High Impact<\/h3>\n<p>The finish-polish slurry pH must be maintained within a narrow optimal window, typically pH 10.0\u201310.5 for (100) silicon. At pH below 9.5, the chemical dissolution rate of silicon is too slow to achieve adequate removal rate even at extended polish times. At pH above 11.0, the hydroxyl ion concentration is high enough to drive anisotropic chemical etching of the silicon crystal \u2014 which etches different crystallographic facets at different rates, creating step-edge roughness and COP pit enlargement that increases Ra. The narrow optimum window also means that pH drift during polishing (from dissolved silicon loading the slurry, from ambient CO\u2082 absorption, or from temperature effects) must be controlled through slurry freshness management and pH monitoring at the tool inlet.<\/p>\n<\/section>\n<hr class=\"jp-hr\">\n\n<section id=\"recipe\">\n<h2>Designing a Finish Polish Recipe for Sub-0.1 nm Ra<\/h2>\n<p>The following parameter set illustrates a representative finish-polish recipe targeting Ra &lt;0.08 nm on (100) silicon, 300mm, using JEEZ FP-series slurry:<\/p>\n<div class=\"jp-table-wrap\">\n<table class=\"jp-table\">\n<thead><tr><th>\u30d1\u30e9\u30e1\u30fc\u30bf<\/th><th>\u4fa1\u5024<\/th><th>\u5099\u8003<\/th><\/tr><\/thead>\n<tbody>\n<tr><td>\u30b9\u30e9\u30ea\u30fc<\/td><td>Colloidal SiO\u2082, D50 = 28 nm, 0.8 wt%<\/td><td>Low concentration, small particles; minimize mechanical component<\/td><\/tr>\n<tr><td>Slurry pH at tool inlet<\/td><td>10.2 \u00b1 0.1<\/td><td>Monitor and control; do not allow &gt;10.5 or &lt;9.8<\/td><\/tr>\n<tr><td>Slurry flow rate<\/td><td>150 ml\/min<\/td><td>Sufficient for full pad coverage; avoid excess that causes turbulence<\/td><\/tr>\n<tr><td>Polishing pad<\/td><td>Soft Suba-type, Shore A 55<\/td><td>Must be fully broken in (\u226520 qualification wafers after new pad installation)<\/td><\/tr>\n<tr><td>Carrier head pressure<\/td><td>0.7 psi (4.8 kPa)<\/td><td>Low pressure: chemistry-dominant regime<\/td><\/tr>\n<tr><td>\u30d7\u30e9\u30c6\u30f3\u901f\u5ea6<\/td><td>40\u56de\u8ee2<\/td><td>Moderate speed; excessive speed raises pad temperature and alters chemical kinetics<\/td><\/tr>\n<tr><td>Carrier head speed<\/td><td>35 rpm (contra-rotation)<\/td><td>Slight differential to ensure uniform surface coverage<\/td><\/tr>\n<tr><td>Polishing time<\/td><td>15\u201320 min<\/td><td>Target removal: 0.8\u20131.2 \u03bcm; adjust based on measured removal rate<\/td><\/tr>\n<tr><td>Pre-polish quench rinse<\/td><td>DI water + 0.1% citric acid, 30 s<\/td><td>Remove rough-polish slurry residue completely before starting finish step<\/td><\/tr>\n<\/tbody>\n<\/table>\n<\/div>\n<\/section>\n<hr class=\"jp-hr\">\n\n<section id=\"pitfalls\">\n<h2>Common Mistakes That Prevent Sub-nm Results<\/h2>\n<ul>\n<li><strong>Over-polishing:<\/strong> The single most common mistake. Once the mechanical damage from the DSP step is fully removed, continuing to polish enters a regime where isotropic alkaline etching roughens different crystallographic facets at different rates \u2014 increasing Ra. The Ra vs. polish time curve is U-shaped; most process engineers optimize the left half but then operate on the right by continuing too long.<\/li>\n<li><strong>Insufficient inter-step quench rinse:<\/strong> Residual rough-polish slurry particles (D50 80\u2013150 nm) carried forward into the finish-polish step immediately dominate the surface finish. Even a few dozen killer particles from the rough-polish step reaching the finish pad can drive Ra from &lt;0.1 nm to &gt;0.3 nm. The inter-step quench rinse must flush both the wafer surface and the delivery lines.<\/li>\n<li><strong>New pad without proper break-in:<\/strong> A freshly installed soft pad has an unstable surface texture with micro-debris and sharp asperities from the manufacturing process. The first 20\u201350 qualification wafers after pad installation gradually smooth the pad surface and stabilize removal rate. Running production wafers on a new pad before break-in completion produces inconsistent Ra results.<\/li>\n<li><strong>pH drift during polishing:<\/strong> As silicon is removed and dissolved into the slurry, the silicic acid load increases, buffering the pH downward. In a long polish cycle or a high-removal-rate process, slurry pH at the pad can drop by 0.3\u20130.5 units below the fresh slurry value. Monitor pH at the tool inlet, not just in the supply tank.<\/li>\n<\/ul>\n<p>For the complete defect context surrounding surface roughness issues, see: <a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/Silicon-Wafer-Surface-Defects-in-CMP-Causes-Detection-Prevention\/\" target=\"_blank\">Silicon Wafer Surface Defects in CMP: Causes, Detection &amp; Prevention<\/a>. For slurry selection guidance, see: <a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/CMP-Slurry-for-Silicon-Wafer-Types-Selection-Best-Practices\/\" target=\"_blank\">CMP Slurry for Silicon Wafer: Types, Selection &amp; Best Practices<\/a>.<\/p>\n<\/section>\n\n<div class=\"jp-related\"><div class=\"jp-related-title\">Related Articles in This Series<\/div><div class=\"jp-related-links\">\n<a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/The-Complete-Guide-to-Silicon-Wafer-Polishing\/\" target=\"_blank\" class=\"jp-rl\"><span class=\"jp-rl-icon\">\ud83d\udcd8<\/span><div><strong>The Complete Guide to Silicon Wafer Polishing<\/strong><span>The comprehensive reference covering all silicon wafer CMP topics.<\/span><\/div><\/a>\n<a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/CMP-Slurry-for-Silicon-Wafer-Types-Selection-Best-Practices\/\" target=\"_blank\" class=\"jp-rl\"><span class=\"jp-rl-icon\">\ud83d\udca7<\/span><div><strong>CMP Slurry for Silicon Wafer: Types, Selection &amp; Best Practices<\/strong><span>How to select and optimize CMP slurry \u2014 the primary lever for surface roughness control.<\/span><\/div><\/a>\n<a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/Silicon-Wafer-Surface-Defects-in-CMP-Causes-Detection-Prevention\/\" target=\"_blank\" class=\"jp-rl\"><span class=\"jp-rl-icon\">\ud83d\udd2c<\/span><div><strong>Silicon Wafer Surface Defects in CMP: Causes, Detection &amp; Prevention<\/strong><span>How haze and roughness relate to the broader defect landscape in CMP.<\/span><\/div><\/a>\n<a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/Why-Silicon-Wafer-Flatness-Matters-TTV-SFQR-and-Nanotopography-Explained\/\" target=\"_blank\" class=\"jp-rl\"><span class=\"jp-rl-icon\">\ud83d\udcd0<\/span><div><strong>Why Silicon Wafer Flatness Matters: TTV, SFQR, and Nanotopography Explained<\/strong><span>Full reference for all wafer surface and geometry quality metrics.<\/span><\/div><\/a>\n<\/div><\/div>\n<hr class=\"jp-hr\">\n<section id=\"faq\">\n<h2>\u3088\u304f\u3042\u308b\u8cea\u554f<\/h2>\n<div class=\"jp-faq\"><div class=\"jp-faq-item\"><div class=\"jp-faq-q\" onclick=\"jeezToggleFaq(this)\">What surface roughness is achievable on polished silicon wafers with CMP?<span class=\"jp-faq-icon\">+<\/span><\/div><div class=\"jp-faq-a\">With optimized colloidal silica finish-polish CMP (low abrasive concentration, soft pad, low pressure, controlled pH), Ra values below 0.08 nm and Rq below 0.10 nm are routinely achievable on (100) 300mm prime-grade silicon wafers in production. The absolute lower limit with abrasive-free alkaline polishing is Ra approximately 0.05\u20130.06 nm. Below this, roughness contributions from the intrinsic crystal surface (atomic steps, vacancies) become the dominant factor rather than the polish process itself.<\/div><\/div>\n<div class=\"jp-faq-item\"><div class=\"jp-faq-q\" onclick=\"jeezToggleFaq(this)\">How is surface roughness measured on silicon wafers?<span class=\"jp-faq-icon\">+<\/span><\/div><div class=\"jp-faq-a\">The standard measurement for Ra and Rq on polished silicon wafers is atomic force microscopy (AFM) with a 1\u00d71 \u03bcm scan area. The AFM tip (typically a silicon cantilever with tip radius ~10 nm) traces the surface topography point by point. The resulting height data are processed to compute Ra, Rq, and optionally the power spectral density (PSD). For in-line production monitoring, haze (in ppm) from laser-scanning surface inspection (Surfscan) serves as a faster proxy for surface roughness, with haze below 0.03 ppm typically corresponding to Rq below 0.10 nm.<\/div><\/div>\n<div class=\"jp-faq-item\"><div class=\"jp-faq-q\" onclick=\"jeezToggleFaq(this)\">Does higher polishing pressure always improve surface roughness?<span class=\"jp-faq-icon\">+<\/span><\/div><div class=\"jp-faq-a\">No \u2014 the relationship between pressure and roughness is not monotonic. At high pressure, mechanical abrasion dominates and produces micro-roughness from individual particle-surface contact events. At low pressure (below 1 psi), the chemical component of CMP dominates and produces smoother surfaces through uniform dissolution. However, at very low pressure the chemical dissolution can become slow enough that the polish time required to remove residual damage from prior steps becomes impractically long. The optimum is typically 0.5\u20131.0 psi for finish-polish applications targeting Ra &lt;0.1 nm.<\/div><\/div>\n<div class=\"jp-faq-item\"><div class=\"jp-faq-q\" onclick=\"jeezToggleFaq(this)\">Why does over-polishing increase surface roughness in the finish CMP step?<span class=\"jp-faq-icon\">+<\/span><\/div><div class=\"jp-faq-a\">In the finish CMP step, once mechanical damage from the prior DSP step has been fully removed, continued polishing enters a regime dominated by alkaline chemical etching of bare crystalline silicon. Unlike the smooth SiO\u2082\u00b7nH\u2082O dissolution mechanism that produces flat surfaces during the effective polishing phase, pure alkaline etching attacks different crystallographic planes and surface features at different rates \u2014 producing step-edge roughness, pit formation, and orientation-dependent texture that increases Ra. The roughness minimum is at the end of the &#8216;effective polishing&#8217; phase, just before this pure-etching regime begins. Endpoint control is critical.<\/div><\/div>\n<div class=\"jp-faq-item\"><div class=\"jp-faq-q\" onclick=\"jeezToggleFaq(this)\">What is the relationship between haze and surface roughness?<span class=\"jp-faq-icon\">+<\/span><\/div><div class=\"jp-faq-a\">Haze (measured in ppm on laser-scanning surface inspectors) is the ratio of diffusely scattered light to incident light and is proportional to the power spectral density (PSD) of surface roughness at spatial wavelengths between approximately 0.1 and 10 \u03bcm. It is not simply proportional to Ra or Rq, which are integrated over all spatial frequencies measured by AFM. In practice, for standard silicon finish-polish processes, haze below 0.03 ppm consistently corresponds to Rq below 0.10 nm. However, a process that produces roughness at spatial wavelengths outside the haze measurement window can have low haze but elevated AFM roughness \u2014 which is why both measurements are typically included in prime-grade silicon specifications.<\/div><\/div>\n<\/div>\n<\/section>\n<hr class=\"jp-hr\">\n<div class=\"jp-cta\"><h2>Achieve Sub-0.1 nm Ra with JEEZ Finish-Polish Slurries<\/h2><p>JEEZ FP-series colloidal silica slurries are formulated specifically for the finish-polish regime \u2014 small particle size (D50 25\u201335 nm), low abrasive concentration, and precisely controlled pH stability \u2014 delivering Ra below 0.08 nm on 300mm prime silicon under production conditions.<\/p>\n<a href=\"https:\/\/jeez-semicon.com\/ja\/contact\/\" target=\"_blank\" class=\"jp-cta-btn\">Contact JEEZ Technical Team<\/a>\n<\/div>\n<\/div>\n<script type=\"application\/ld+json\">{\"@context\":\"https:\/\/schema.org\",\"@type\":\"FAQPage\",\"mainEntity\":[{\"@type\":\"Question\",\"name\":\"What surface roughness is achievable on polished silicon wafers with CMP?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"With optimized colloidal silica finish-polish CMP (low abrasive concentration, soft pad, low pressure, controlled pH), Ra values below 0.08 nm and Rq below 0.10 nm are routinely achievable on (100) 300mm prime-grade silicon wafers in production. The absolute lower limit with abrasive-free alkaline polishing is Ra approximately 0.05\u20130.06 nm. Below this, roughness contributions from the intrinsic crystal surface (atomic steps, vacancies) become the dominant factor rather than the polish process itself.\"}},{\"@type\":\"Question\",\"name\":\"How is surface roughness measured on silicon wafers?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"The standard measurement for Ra and Rq on polished silicon wafers is atomic force microscopy (AFM) with a 1\u00d71 \u03bcm scan area. The AFM tip (typically a silicon cantilever with tip radius ~10 nm) traces the surface topography point by point. The resulting height data are processed to compute Ra, Rq, and optionally the power spectral density (PSD). For in-line production monitoring, haze (in ppm) from laser-scanning surface inspection (Surfscan) serves as a faster proxy for surface roughness, with haze below 0.03 ppm typically corresponding to Rq below 0.10 nm.\"}},{\"@type\":\"Question\",\"name\":\"Does higher polishing pressure always improve surface roughness?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"No \u2014 the relationship between pressure and roughness is not monotonic. At high pressure, mechanical abrasion dominates and produces micro-roughness from individual particle-surface contact events. At low pressure (below 1 psi), the chemical component of CMP dominates and produces smoother surfaces through uniform dissolution. However, at very low pressure the chemical dissolution can become slow enough that the polish time required to remove residual damage from prior steps becomes impractically long. The optimum is typically 0.5\u20131.0 psi for finish-polish applications targeting Ra &lt;0.1 nm.\"}},{\"@type\":\"Question\",\"name\":\"Why does over-polishing increase surface roughness in the finish CMP step?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"In the finish CMP step, once mechanical damage from the prior DSP step has been fully removed, continued polishing enters a regime dominated by alkaline chemical etching of bare crystalline silicon. Unlike the smooth SiO\u2082\u00b7nH\u2082O dissolution mechanism that produces flat surfaces during the effective polishing phase, pure alkaline etching attacks different crystallographic planes and surface features at different rates \u2014 producing step-edge roughness, pit formation, and orientation-dependent texture that increases Ra. The roughness minimum is at the end of the 'effective polishing' phase, just before this pure-etching regime begins. Endpoint control is critical.\"}},{\"@type\":\"Question\",\"name\":\"What is the relationship between haze and surface roughness?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"Haze (measured in ppm on laser-scanning surface inspectors) is the ratio of diffusely scattered light to incident light and is proportional to the power spectral density (PSD) of surface roughness at spatial wavelengths between approximately 0.1 and 10 \u03bcm. It is not simply proportional to Ra or Rq, which are integrated over all spatial frequencies measured by AFM. In practice, for standard silicon finish-polish processes, haze below 0.03 ppm consistently corresponds to Rq below 0.10 nm. However, a process that produces roughness at spatial wavelengths outside the haze measurement window can have low haze but elevated AFM roughness \u2014 which is why both measurements are typically included in prime-grade silicon specifications.\"}}]}<\/script>\n<script>\nfunction jeezToggleFaq(el){\n  var a=el.nextElementSibling,o=a.classList.contains('jp-open');\n  document.querySelectorAll('.jp-faq-a').forEach(function(x){x.classList.remove('jp-open')});\n  document.querySelectorAll('.jp-faq-q').forEach(function(x){x.classList.remove('jp-open')});\n  if(!o){a.classList.add('jp-open');el.classList.add('jp-open');}\n}\n<\/script>","protected":false},"excerpt":{"rendered":"<p>\u2190 Back to: The Complete Guide to Silicon Wafer Polishing JEEZ Semiconductor Materials &nbsp;\u00b7&nbsp; Technical Guide &nbsp;\u00b7&nbsp; Updated June 2026 A process engineering guide to reaching Ra below 0.1 nm  &#8230;<\/p>","protected":false},"author":1,"featured_media":2299,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[9,59],"tags":[],"class_list":["post-2297","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-blog","category-industry"],"acf":[],"_links":{"self":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts\/2297","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/comments?post=2297"}],"version-history":[{"count":2,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts\/2297\/revisions"}],"predecessor-version":[{"id":2300,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts\/2297\/revisions\/2300"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/media\/2299"}],"wp:attachment":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/media?parent=2297"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/categories?post=2297"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/tags?post=2297"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}