{"id":2390,"date":"2026-06-24T10:15:23","date_gmt":"2026-06-24T02:15:23","guid":{"rendered":"https:\/\/jeez-semicon.com\/?p=2390"},"modified":"2026-06-24T10:15:23","modified_gmt":"2026-06-24T02:15:23","slug":"planarization-applications-in-ic-fabrication-sti-ild-cu-damascene-w-plug","status":"publish","type":"post","link":"https:\/\/jeez-semicon.com\/ja\/blog\/planarization-applications-in-ic-fabrication-sti-ild-cu-damascene-w-plug\/","title":{"rendered":"Planarization Applications in IC Fabrication: STI, ILD, Cu Damascene &amp; W Plug"},"content":{"rendered":"<!-- JEEZ | Cluster 06 | Planarization Applications in IC Fabrication: STI, ILD, Cu Damascene & W Plug -->\n<link rel=\"preconnect\" href=\"https:\/\/fonts.googleapis.com\">\n<link rel=\"preconnect\" href=\"https:\/\/fonts.gstatic.com\" crossorigin>\n<link href=\"https:\/\/fonts.googleapis.com\/css2?family=Syne:wght@600;700;800&#038;family=Inter:ital,wght@0,400;0,500;0,600;1,400&#038;display=swap\" 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.jz-cta-box::before{content:'';position:absolute;left:-70px;bottom:-70px;width:230px;height:230px;border-radius:50%;background:radial-gradient(circle,rgba(13,148,136,.16) 0%,transparent 70%)}\n.jeez-pl .jz-cta-box h3{font-family:'Syne',sans-serif;color:#fff;font-size:1.4rem;font-weight:800;margin:0 0 10px;position:relative}\n.jeez-pl .jz-cta-box p{color:rgba(255,255,255,.74);max-width:520px;margin:0 auto 26px;font-size:14.5px;position:relative}\n.jeez-pl .jz-btn{display:inline-block;background:var(--jz-teal);color:#fff;font-size:14.5px;font-weight:700;padding:13px 36px;border-radius:8px;text-decoration:none;transition:background .15s,transform .1s}\n.jeez-pl .jz-btn:hover{background:var(--jz-teal-dark);color:#fff;text-decoration:none;transform:translateY(-2px)}\n.jeez-pl .jz-faq-list{margin-top:18px}\n.jeez-pl .jz-faq-item{border:1px solid var(--jz-border);border-radius:var(--jz-radius);margin-bottom:12px;overflow:hidden}\n.jeez-pl .jz-faq-q{background:var(--jz-bg);padding:15px 20px;font-weight:600;font-size:14.5px;color:var(--jz-navy);border-left:4px solid var(--jz-teal);line-height:1.4}\n.jeez-pl .jz-faq-a{padding:14px 20px 16px;font-size:14px;color:var(--jz-text);line-height:1.74;border-top:1px solid var(--jz-border)}\n@media(max-width:680px){.jeez-pl .jz-hero{padding:28px 22px}.jeez-pl .jz-toc ol{columns:1}.jeez-pl .jz-module{padding:20px 18px}.jeez-pl .jz-cta-box{padding:32px 22px}.jeez-pl h2{font-size:1.3rem}}\n<\/style>\n\n<div class=\"jeez-pl\">\n\n<a class=\"jz-back-link\" href=\"https:\/\/jeez-semicon.com\/ja\/blog\/Planarization-in-Semiconductor-Manufacturing-Complete-Guide\/\" target=\"_blank\" rel=\"noopener noreferrer\">\u2190 Back to Complete Planarization Guide<\/a>\n\n<div class=\"jz-hero\">\n  <span class=\"jz-hero-eyebrow\">IC Process Integration<\/span>\n  <p class=\"jz-hero-lead\">CMP is not a single process \u2014 it is a family of distinct applications deployed at every major integration module in the IC fabrication flow. Each module has its own target film system, selectivity requirements, defect challenges, and consumable specifications. This guide provides a comprehensive module-by-module breakdown of semiconductor planarization applications: Shallow Trench Isolation, Interlayer Dielectric, Copper Damascene, Tungsten Plug, and advanced applications including RMG, TSV reveal, and hybrid bonding.<\/p>\n  <div class=\"jz-hero-meta\">\n    <span>Updated: <strong>June 2026<\/strong><\/span>\n    <span class=\"jz-pipe\">|<\/span>\n    <span>By <strong>JEEZ Technical Team<\/strong><\/span>\n  <\/div>\n<\/div>\n\n<nav class=\"jz-toc\" aria-label=\"\u76ee\u6b21\">\n  <span class=\"jz-toc-label\">\u76ee\u6b21<\/span>\n  <ol>\n    <li><a href=\"#overview\">CMP in the IC Process Flow<\/a><\/li>\n    <li><a href=\"#sti\">STI CMP: Shallow Trench Isolation<\/a><\/li>\n    <li><a href=\"#ild\">ILD CMP: Interlayer Dielectric<\/a><\/li>\n    <li><a href=\"#tungsten\">Tungsten Plug CMP<\/a><\/li>\n    <li><a href=\"#copper\">Copper Damascene CMP<\/a><\/li>\n    <li><a href=\"#rmg\">Replacement Metal Gate (RMG) CMP<\/a><\/li>\n    <li><a href=\"#tsv\">Through-Silicon Via (TSV) Reveal CMP<\/a><\/li>\n    <li><a href=\"#hybrid-bonding\">Hybrid Bonding Planarization<\/a><\/li>\n    <li><a href=\"#module-summary\">Module Summary Table<\/a><\/li>\n    <li><a href=\"#faq\">\u3088\u304f\u3042\u308b\u8cea\u554f<\/a><\/li>\n  <\/ol>\n<\/nav>\n\n\n<section id=\"overview\">\n  <h2><span class=\"jz-sn\">01<\/span>CMP in the IC Process Flow<\/h2>\n  <p>A modern logic chip at the 2 nm node (June 2026) requires more than 25 individual CMP steps distributed across the front-end-of-line (FEOL) device formation and the back-end-of-line (BEOL) interconnect stack. Each CMP step targets a specific film system, achieves a specific planarization objective, and must meet a specific set of uniformity and defect specifications. Understanding each application \u2014 its purpose, process flow context, consumable requirements, and critical defect modes \u2014 is essential for anyone involved in advanced semiconductor process integration.<\/p>\n\n  <div class=\"jz-callout blue\">\n    <span class=\"jz-callout-tag\">Process Flow Context<\/span>\n    <p>CMP applications in order of process flow: STI CMP (FEOL, after trench oxide fill) \u2192 Gate CMP \/ RMG CMP (FEOL, replacement metal gate) \u2192 Self-Aligned Contact CMP \u2192 W plug CMP (contact level) \u2192 ILD CMP (repeated at every metal level, M1 through M15+) \u2192 Cu Damascene CMP (M1 through M15+, two steps per level) \u2192 TSV reveal CMP (if 3D stacking) \u2192 Hybrid bonding CMP (advanced packaging).<\/p>\n  <\/div>\n<\/section>\n\n\n<section id=\"sti\">\n  <h2><span class=\"jz-sn\">02<\/span>STI CMP: Shallow Trench Isolation<\/h2>\n\n  <div class=\"jz-module\">\n    <span class=\"jz-module-tag\">FEOL \u2014 Device Isolation<\/span>\n    <h3>What Is STI and Why Does It Need CMP?<\/h3>\n    <p>Shallow Trench Isolation (STI) is the device isolation technique used in all CMOS logic, DRAM, and NAND flash processes at 0.25 \u00b5m and below, replacing the older LOCOS (Local Oxidation of Silicon) method. In STI, narrow trenches (100\u2013400 nm deep, 50\u2013200 nm wide) are dry-etched into the silicon substrate, filled with high-density plasma CVD (HDP-CVD) oxide, and then the oxide overburden above the wafer surface is planarized by CMP to leave the isolation oxide recessed at or slightly below the silicon nitride surface level. The nitride hard mask is then removed, and the silicon fin or active area is exposed for subsequent gate and source\/drain processing.<\/p>\n    <p>CMP is essential in the STI module because the HDP-CVD oxide deposition leaves a non-planar overburden (typically 300\u2013600 nm above the silicon nitride mask) whose surface topography exactly mirrors the underlying trench pattern density. If this overburden is not globally planarized, the subsequent lithographic steps for gate patterning will fail across the non-uniform surface.<\/p>\n  <\/div>\n\n  <h3>STI CMP Process Details<\/h3>\n\n  <h4>Film Stack and Target<\/h4>\n  <p>The incoming film stack for STI CMP is: Silicon (substrate) \/ Si\u2083N\u2084 (100\u2013200 nm, hard mask) \/ Pad oxide SiO\u2082 (5\u201310 nm) \/ HDP-CVD SiO\u2082 (overburden, 300\u2013600 nm above the Si\u2083N\u2084 surface). The CMP target is to remove the HDP-CVD oxide overburden and stop precisely on the Si\u2083N\u2084 hard mask, with WIWNU in the remaining nitride thickness of \u00b15\u201310 nm across the 300 mm wafer.<\/p>\n\n  <h4>Slurry Requirements: High Selectivity Ceria<\/h4>\n  <p>Standard STI CMP uses a fumed ceria (CeO\u2082) slurry at pH 4\u20137 with optional polymeric selectivity additives (polyacrylic acid). Target SiO\u2082:Si\u2083N\u2084 selectivity is 50:1 to &gt;100:1. This high selectivity ensures that the polishing stops effectively on the nitride stop layer without consuming it \u2014 preserving the full nitride thickness for subsequent processing. Colloidal silica slurries (selectivity 3:1 to 10:1) are insufficient for STI CMP at sub-65 nm nodes where the nitride thickness budget is tight.<\/p>\n\n  <h4>Critical Defect Modes<\/h4>\n  <ul>\n    <li><strong>Dishing:<\/strong> Over-polishing of wide oxide isolation regions (field oxide in sparse areas) below the nitride surface level. Controlled by optimizing over-polish time and selectivity.<\/li>\n    <li><strong>Erosion:<\/strong> Pattern-density-dependent thinning of nitride in dense STI arrays, causing the local oxide height to vary across the chip as a function of active area density. Managed by layout-level dummy fill rules and slurry selectivity optimization.<\/li>\n    <li><strong>Nitride loss:<\/strong> If selectivity drops below specification (e.g., due to slurry pH drift), excessive nitride removal can expose the pad oxide and even the silicon below, causing junction leakage or gate oxide quality degradation.<\/li>\n  <\/ul>\n\n  <h4>Impact on Device Performance<\/h4>\n  <p>The remaining oxide height in STI trenches after CMP \u2014 the STI recess \u2014 directly affects transistor behavior. In FinFET devices, STI CMP determines the effective fin height above the isolation oxide, which controls transistor on-current (I<sub>on<\/sub>) and threshold voltage. A WIWNU of 2 nm in fin height translates directly into 2 nm of drive current variation across the die \u2014 a critical parametric yield concern at advanced nodes.<\/p>\n<\/section>\n\n\n<section id=\"ild\">\n  <h2><span class=\"jz-sn\">03<\/span>ILD CMP: Interlayer Dielectric Planarization<\/h2>\n\n  <div class=\"jz-module\">\n    <span class=\"jz-module-tag\">BEOL \u2014 Dielectric Planarization<\/span>\n    <h3>Role of ILD CMP in Multi-Level Metallization<\/h3>\n    <p>Interlayer Dielectric (ILD) CMP is the highest-volume CMP application in any advanced logic fab \u2014 it is performed once between every pair of adjacent metal interconnect layers, and with 15+ metal levels in a 2 nm node chip, that means 15 or more ILD CMP steps per device. Each ILD CMP step removes the dielectric overburden deposited over the previous metal layer, planarizing the surface to a flat dielectric reference plane onto which the next via and metal pattern will be lithographically defined.<\/p>\n  <\/div>\n\n  <h3>ILD Materials and Their CMP Challenges<\/h3>\n  <p>The dielectric material used for ILD has evolved substantially as the semiconductor industry has driven toward lower dielectric constants (k) to reduce interconnect RC delay:<\/p>\n\n  <div class=\"jz-table-wrap\">\n    <table>\n      <thead>\n        <tr><th>ILD Material<\/th><th>Dielectric Constant (k)<\/th><th>CMP Challenge<\/th><th>Node Range<\/th><\/tr>\n      <\/thead>\n      <tbody>\n        <tr><td>Thermal SiO\u2082 \/ TEOS<\/td><td>3.9\u20134.2<\/td><td>Standard \u2014 well-characterized, mechanically robust<\/td><td>\u22650.18 \u00b5m<\/td><\/tr>\n        <tr><td>Fluorinated Silicate Glass (FSG)<\/td><td>3.4\u20133.7<\/td><td>Minor: fluorine outgassing at high temperature, mild etch rate sensitivity<\/td><td>0.18\u20130.13 \u00b5m<\/td><\/tr>\n        <tr><td>Carbon-doped oxide (SiCOH)<\/td><td>2.7\u20133.0<\/td><td>Moderate: reduced hardness vs. SiO\u2082; requires softer polish conditions<\/td><td>90\u201345 nm<\/td><\/tr>\n        <tr><td>Porous SiCOH (ultra-low-k)<\/td><td>2.0\u20132.5<\/td><td>High: mechanically fragile (porous matrix), delamination risk, moisture absorption<\/td><td>32 nm\u2013present<\/td><\/tr>\n      <\/tbody>\n    <\/table>\n  <\/div>\n\n  <p>For ultra-low-k (ULK) porous dielectric ILD CMP, process conditions must be significantly modified compared to standard oxide CMP: reduced down-force (1\u20132 psi vs. 3\u20136 psi for dense oxide), compliant two-layer pad stack with soft top layer, surfactant-rich slurry chemistry to minimize mechanical stress at the dielectric surface, and strict avoidance of thermal or mechanical cycling that could collapse the porous structure. Delamination of ULK films at the pad interface is the primary yield-loss concern in ULK ILD CMP.<\/p>\n\n  <h3>ILD CMP Uniformity Specifications<\/h3>\n  <p>Post-CMP ILD thickness WIWNU is typically specified at \u00b15\u201310 nm (absolute) or &lt;2% (relative to mean thickness) for standard oxide ILD, and \u00b13\u20135 nm for advanced ULK ILD where via depth variation directly impacts via resistance and RC performance. These specifications are enforced by in-line post-CMP reflectometry measurement and fed back into run-to-run control systems that adjust the next lot&#8217;s polishing time or pressure profile to compensate for drift.<\/p>\n<\/section>\n\n\n<section id=\"tungsten\">\n  <h2><span class=\"jz-sn\">04<\/span>Tungsten Plug CMP<\/h2>\n\n  <div class=\"jz-module\">\n    <span class=\"jz-module-tag\">Contact Level \u2014 Plug Formation<\/span>\n    <h3>Tungsten Contact Plug CMP Overview<\/h3>\n    <p>Tungsten (W) contact plug CMP is the CMP step that defines the contact level \u2014 the vertical connections from the transistor source, drain, and gate terminals up through the pre-metal dielectric (PMD) to the first metal layer (M1). The process fills high-aspect-ratio contact holes (50\u2013100 nm diameter, 200\u2013400 nm deep, AR 4:1 to 8:1) with CVD-deposited tungsten, which conforms to the hole geometry and deposits a thick overburden across the entire wafer surface. CMP removes the W overburden and exposes the TiN\/TiW adhesion\/barrier layer, then continues to clear the barrier and stop on the PMD SiO\u2082 ILD.<\/p>\n  <\/div>\n\n  <h3>W CMP Process Flow<\/h3>\n  <ol>\n    <li><strong>PMD deposition and planarization:<\/strong> CVD oxide PMD is deposited over the transistors and silicide contacts, then planarized by CMP. The planarized PMD surface is the starting surface for contact hole lithography and etch.<\/li>\n    <li><strong>Contact hole etch:<\/strong> Anisotropic RIE etches contact holes through the PMD to the silicide contact. Hole depth uniformity is critical \u2014 a non-planar PMD causes depth variation that degrades tungsten fill quality.<\/li>\n    <li><strong>TiN\/Ti barrier deposition:<\/strong> 5\u201320 nm TiN or Ti\/TiN liner deposited by PVD or ALD covers the contact hole sidewalls and bottom, providing adhesion and a diffusion barrier for the W fill.<\/li>\n    <li><strong>CVD-W fill:<\/strong> Tungsten CVD fills the contact holes and deposits 200\u2013400 nm overburden across the full wafer surface.<\/li>\n    <li><strong>W CMP:<\/strong> Fumed alumina slurry (pH 2\u20134) with H\u2082O\u2082 removes the W overburden (step 1), transitions to barrier clearing (step 2, endpoint-controlled), and stops on the SiO\u2082 PMD surface.<\/li>\n  <\/ol>\n\n  <h3>Critical Defect Modes in W CMP<\/h3>\n  <ul>\n    <li><strong>Plug dishing:<\/strong> Over-polishing of W plugs below the PMD surface level, increasing contact resistance. Controlled by minimizing over-polish time and selecting slurry chemistry with moderate W:SiO\u2082 selectivity.<\/li>\n    <li><strong>Tungsten recess (seam voids):<\/strong> CVD-W deposition in high-aspect-ratio contacts sometimes leaves a seam void at the contact center. If CMP dishing exposes this void, the contact resistance increases sharply. Minimized by optimizing W nucleation chemistry and CVD conditions before CMP.<\/li>\n    <li><strong>Barrier metal residue:<\/strong> Incompletely cleared TiN\/TiW on the PMD surface creates conductive shorts between adjacent contacts. Addressed by extending the clearing step duration or increasing the barrier removal rate through slurry pH optimization.<\/li>\n  <\/ul>\n<\/section>\n\n\n<section id=\"copper\">\n  <h2><span class=\"jz-sn\">05<\/span>Copper Damascene CMP<\/h2>\n\n  <div class=\"jz-module\">\n    <span class=\"jz-module-tag\">BEOL \u2014 Metal Interconnect (M1\u2013M15+)<\/span>\n    <h3>Cu Damascene CMP Overview<\/h3>\n    <p>Copper CMP is the process that defines every metal interconnect layer \u2014 M1 through the top metal \u2014 in dual-damascene copper interconnect technology. It is performed more times than any other CMP application in a leading-edge logic fab, making it the highest-impact CMP process for yield, throughput, and consumable cost. The process must remove copper overburden (electrochemically deposited, typically 500\u20131500 nm above the trench top) and TaN\/Ta barrier metal, stopping precisely on the low-k dielectric ILD, with WIWNU &lt;1.5% and minimum dishing and erosion in the finished metal pattern.<\/p>\n  <\/div>\n\n  <h3>The Dual-Damascene Structure<\/h3>\n  <p>Dual-damascene processing integrates the via (vertical) and trench (horizontal) metal levels into a single patterning and fill sequence. The ILD is patterned with both via holes and metal trenches in one combined lithography-and-etch sequence, then copper fills both simultaneously by electrochemical deposition (ECD). CMP removes the copper above the trench top and the barrier metal, leaving copper-filled trenches (the metal lines) and vias in a planar low-k dielectric surface. This dual-damascene approach, introduced with copper CMP at the 130 nm node, reduces process complexity compared to single-damascene (separate via and trench fill steps) while producing superior interconnect resistance and yield.<\/p>\n\n  <h3>Two-Step Cu CMP in Detail<\/h3>\n\n  <h4>Step 1: Bulk Copper Removal<\/h4>\n  <p>High-pressure, high-MRR polishing (typically 2\u20134 psi, 300\u2013600 nm\/min Cu MRR) removes the bulk copper overburden above the barrier layer. Colloidal silica slurry at pH 4\u20136 with H\u2082O\u2082 oxidizer (added at point-of-use). The endpoint for Step 1 is detected when the barrier metal is first exposed across the majority of the wafer \u2014 typically identified by a friction (motor current) change or a change in the optical EPD signal. Step 1 is stopped slightly before complete barrier exposure to preserve a thin copper over-layer (~50\u2013100 nm) above the barrier, preventing copper from being polished over areas where the barrier is already exposed while the barrier in other areas is not yet cleared.<\/p>\n\n  <h4>Step 2: Barrier Clearing and Final Planarization<\/h4>\n  <p>Gentler polishing conditions (1\u20132 psi, reduced slurry flow) with a barrier-selective slurry formulation removes the remaining copper overburden and the TaN\/Ta barrier layer, stopping on the low-k dielectric ILD. Higher BTA concentration (0.05\u20130.1 wt%) suppresses copper dissolution and dishing during this step. The Step 2 endpoint is the full exposure of the dielectric surface across the entire wafer \u2014 confirmed by optical EPD signal stabilization. Post-Step 2, the wafer surface should show copper lines at (or within 3\u20135 nm of) the dielectric level, with Ra &lt;0.5 nm.<\/p>\n\n  <h3>Dishing and Erosion: The Dominant Defect Modes<\/h3>\n\n  <div class=\"jz-callout gold\">\n    <span class=\"jz-callout-tag\">Critical Defects<\/span>\n    <p><strong>\u30c7\u30a3\u30c3\u30b7\u30f3\u30b0<\/strong> is the concave polishing of wide copper features below the surrounding dielectric level. <strong>\u6d78\u98df<\/strong> is the thinning of the dielectric between copper lines in dense metal arrays. Both increase with over-polish time and are driven by the compliance of the polishing pad conforming to the metal pattern. At sub-20 nm metal pitches, even 1\u20132 nm of dishing or erosion creates measurable increases in line resistance and significant changes in inter-metal capacitance that affect circuit timing.<\/p>\n  <\/div>\n\n  <a class=\"jz-more\" href=\"https:\/\/jeez-semicon.com\/ja\/blog\/Semiconductor-Planarization-for-Advanced-Nodes-FinFET-GAA-3D-IC-Challenges\/\" target=\"_blank\" rel=\"noopener noreferrer\">\n    <span>Advanced challenges: Semiconductor Planarization for Advanced Nodes \u2014 FinFET, GAA &amp; 3D IC<\/span>\n    <span class=\"jz-more-arrow\">\u2192<\/span>\n  <\/a>\n<\/section>\n\n\n<section id=\"rmg\">\n  <h2><span class=\"jz-sn\">06<\/span>Replacement Metal Gate (RMG) CMP<\/h2>\n  <p>Replacement Metal Gate (RMG) \u2014 also called gate-last or high-k-last process \u2014 is the gate formation technique used in all leading-edge logic processes from 22 nm FinFET through current 2 nm GAA nanosheet. The RMG flow requires two CMP steps:<\/p>\n  <ol>\n    <li><strong>Dummy gate planarization CMP:<\/strong> After source\/drain formation and silicide annealing, a thick ILD oxide is deposited over the dummy polysilicon gate. CMP planarizes this ILD to expose the top of the dummy gate \u2014 the reference surface from which the gate is removed and replaced. WIWNU in the remaining ILD thickness directly determines dummy gate height uniformity, which determines the work function consistency of the replacement gate across the die.<\/li>\n    <li><strong>Metal gate CMP:<\/strong> After the dummy gate is removed (wet etch) and the high-k\/metal gate stack (HfO\u2082\/TiN\/TaN\/W or Co fill) is deposited and etched back, a final CMP step planarizes the gate metal level, leaving the high-k\/metal gate stack flush with the surrounding ILD surface. Gate height WIWNU after this CMP directly impacts threshold voltage (V<sub>T<\/sub>) distribution across the wafer \u2014 a key performance specification for high-speed logic.<\/li>\n  <\/ol>\n<\/section>\n\n\n<section id=\"tsv\">\n  <h2><span class=\"jz-sn\">07<\/span>Through-Silicon Via (TSV) Reveal CMP<\/h2>\n  <p>Through-Silicon Vias (TSVs) connect die vertically in 3D stacked memory (HBM, 3D DRAM) and logic-on-logic integration schemes. TSVs are typically formed by &#8220;via-first&#8221; or &#8220;via-middle&#8221; approaches \u2014 etching and copper-filling via structures before or during the device process \u2014 and are then revealed on the wafer back-side by grinding and CMP to expose the copper via tips after wafer thinning.<\/p>\n  <p>TSV reveal CMP removes the back-side silicon from the thinned wafer (~50\u2013100 \u00b5m silicon remaining after grinding) down to the copper TSV tips, then polishes the silicon surface to expose the vias uniformly. The critical specification is the planarity of the silicon back-side relative to the copper TSV tops: excessive silicon over the TSVs (incomplete reveal) blocks electrical contact; excessive removal (over-polish) causes copper dishing in the via and mechanical stress concentration at the via perimeter that risks via cracking during subsequent back-side processing and packaging.<\/p>\n<\/section>\n\n\n<section id=\"hybrid-bonding\">\n  <h2><span class=\"jz-sn\">08<\/span>Hybrid Bonding Planarization<\/h2>\n  <p>Hybrid bonding is the most demanding CMP application in terms of surface finish requirements. In hybrid bonding for 3D IC integration (die-to-wafer or wafer-to-wafer), two bonding surfaces \u2014 each containing copper pads embedded in SiO\u2082 or SiCN dielectric \u2014 are brought into direct contact and bonded simultaneously at the Cu\u2013Cu and dielectric\u2013dielectric interfaces without any adhesive, solder, or underfill.<\/p>\n  <p>For this direct bonding to work at the atomic scale, both surfaces must be prepared by CMP to meet simultaneously: Ra below 0.3 nm (to enable spontaneous SiO\u2082-to-SiO\u2082 oxide fusion at room temperature); copper pad step height (recessed or protruding relative to the dielectric) of no more than \u00b12\u20133 nm; and particle density below 0.01 defects\/cm\u00b2 (any particle at the bond interface creates a void that prevents local bonding and reduces bonding yield). These specifications are at the absolute limit of what CMP can achieve, requiring fixed abrasive or ultra-soft pad systems, ultra-dilute polishing conditions, and extensive post-CMP surface characterization.<\/p>\n<\/section>\n\n\n<section id=\"module-summary\">\n  <h2><span class=\"jz-sn\">09<\/span>Module Summary Table<\/h2>\n  <div class=\"jz-table-wrap\">\n    <table>\n      <thead>\n        <tr><th>CMP Module<\/th><th>Process Location<\/th><th>\u30bf\u30fc\u30b2\u30c3\u30c8\u30d5\u30a3\u30eb\u30e0<\/th><th>Recommended Slurry<\/th><th>Key Spec<\/th><\/tr>\n      <\/thead>\n      <tbody>\n        <tr><td><strong>STI CMP<\/strong><\/td><td>FEOL \u2014 Isolation<\/td><td>HDP-CVD SiO\u2082 \/ stop: Si\u2083N\u2084<\/td><td>Fumed CeO\u2082, pH 4\u20137<\/td><td>Oxide:nitride selectivity &gt;50:1; WIWNU &lt;2%<\/td><\/tr>\n        <tr><td><strong>PMD \/ ILD CMP<\/strong><\/td><td>FEOL\/BEOL \u2014 Dielectric<\/td><td>TEOS, FSG, SiCOH<\/td><td>Colloidal SiO\u2082, pH 10\u201311<\/td><td>WIWNU &lt;2%; Ra &lt;1 nm<\/td><\/tr>\n        <tr><td><strong>W Plug CMP<\/strong><\/td><td>Contact level<\/td><td>CVD-W \/ stop: SiO\u2082 PMD<\/td><td>Fumed Al\u2082O\u2083, pH 2\u20134<\/td><td>Plug dishing &lt;10 nm; barrier clearance<\/td><\/tr>\n        <tr><td><strong>Cu Damascene CMP (Step 1)<\/strong><\/td><td>BEOL \u2014 M1 to M15+<\/td><td>ECD Cu overburden<\/td><td>Colloidal SiO\u2082 + H\u2082O\u2082, pH 4\u20136<\/td><td>Cu MRR 300\u2013600 nm\/min; Cu:barrier &gt;5:1<\/td><\/tr>\n        <tr><td><strong>Cu Damascene CMP (Step 2)<\/strong><\/td><td>BEOL \u2014 barrier clearing<\/td><td>TaN\/Ta barrier + remaining Cu<\/td><td>Colloidal SiO\u2082 + BTA, pH 5\u20137<\/td><td>Dishing &lt;5 nm; erosion &lt;10 nm; Ra &lt;0.5 nm<\/td><\/tr>\n        <tr><td><strong>RMG CMP<\/strong><\/td><td>FEOL \u2014 Gate<\/td><td>ILD SiO\u2082 \/ gate metal<\/td><td>Colloidal SiO\u2082 or specialty<\/td><td>Gate height WIWNU &lt;1 nm; V<sub>T<\/sub> uniformity<\/td><\/tr>\n        <tr><td><strong>TSV Reveal CMP<\/strong><\/td><td>Back-side thinning<\/td><td>Si substrate \/ Cu TSV tips<\/td><td>Colloidal SiO\u2082 + KOH<\/td><td>Via reveal uniformity; Cu dishing &lt;50 nm<\/td><\/tr>\n        <tr><td><strong>Hybrid Bonding CMP<\/strong><\/td><td>Advanced packaging<\/td><td>Cu pads in SiO\u2082\/SiCN<\/td><td>Fixed abrasive or ultra-dilute<\/td><td>Ra &lt;0.3 nm; Cu step &lt;2 nm; defects &lt;0.01\/cm\u00b2<\/td><\/tr>\n      <\/tbody>\n    <\/table>\n  <\/div>\n<\/section>\n\n\n<div class=\"jz-cta-box\">\n  <h3>JEEZ CMP Consumables for Every IC Fabrication Module<\/h3>\n  <p>JEEZ manufactures CMP slurries, polishing pads, and absorption films engineered for STI, ILD, tungsten, and copper planarization modules. Direct manufacturer, global supply, full technical support. Contact us to discuss your application.<\/p>\n  <a class=\"jz-btn\" href=\"https:\/\/jeez-semicon.com\/ja\/contact\/\" target=\"_blank\" rel=\"noopener noreferrer\">Contact JEEZ \u2192<\/a>\n<\/div>\n\n\n<section id=\"faq\">\n  <h2><span class=\"jz-sn\">\u3088\u304f\u3042\u308b\u3054\u8cea\u554f<\/span>\u3088\u304f\u3042\u308b\u8cea\u554f<\/h2>\n  <div class=\"jz-faq-list\">\n    <div class=\"jz-faq-item\">\n      <div class=\"jz-faq-q\">What is STI CMP and why is high-selectivity slurry required?<\/div>\n      <div class=\"jz-faq-a\">STI CMP removes the HDP-CVD oxide overburden deposited into and over shallow trench isolation trenches, stopping precisely on the Si\u2083N\u2084 hard mask below. High-selectivity slurry (fumed ceria with selectivity &gt;50:1 SiO\u2082:Si\u2083N\u2084) is required because the Si\u2083N\u2084 stop layer is thin (100\u2013200 nm) and must survive the polishing process intact to define the final STI oxide height. Low-selectivity slurries would consume too much nitride during oxide overburden clearing, causing unacceptable FinFET fin height variation and transistor performance spread.<\/div>\n    <\/div>\n    <div class=\"jz-faq-item\">\n      <div class=\"jz-faq-q\">What is dishing in copper CMP and how does it affect interconnect performance?<\/div>\n      <div class=\"jz-faq-a\">Dishing is the concave erosion of copper features below the surrounding dielectric level during damascene CMP. It occurs because the soft copper is polished faster than the surrounding harder dielectric \u2014 especially in wide copper features where the pad conforms to and removes copper from the feature center. Dishing increases the effective copper line resistance (thinner copper at the center of wide lines), changes the line-to-line capacitance profile, and in the worst case causes the thin copper at the dish center to be fully consumed, creating open circuits. It is controlled by BTA concentration, polishing conditions (pressure, step 2 duration), and slurry chemistry selection.<\/div>\n    <\/div>\n    <div class=\"jz-faq-item\">\n      <div class=\"jz-faq-q\">Why does ILD CMP become more difficult with lower-k dielectrics?<\/div>\n      <div class=\"jz-faq-a\">Lower-k dielectrics (porous SiCOH, k &lt;2.5) are mechanically weaker than dense SiO\u2082 due to their porous structure \u2014 elastic modulus drops from ~70 GPa for SiO\u2082 to &lt;10 GPa for ultra-low-k films. Under CMP pad contact pressure, these films can delaminate from the underlying etch stop layer or fracture internally if the applied stress exceeds their cohesive strength. Process adaptations include: reduced down-force (1\u20132 psi), compliant pad stacks with soft top layers, surfactant-rich slurry to reduce pad-wafer friction, and post-CMP cleaning chemistry that does not chemically attack the hydrophobic low-k surface.<\/div>\n    <\/div>\n    <div class=\"jz-faq-item\">\n      <div class=\"jz-faq-q\">What makes hybrid bonding CMP the most demanding CMP application?<\/div>\n      <div class=\"jz-faq-a\">Hybrid bonding CMP must simultaneously achieve Ra below 0.3 nm, copper step height within \u00b12\u20133 nm of the dielectric surface, and defect density below 0.01 \/cm\u00b2. These specifications are orders of magnitude tighter than standard ILD or copper CMP (which target Ra 0.5\u20131 nm and dishing\/erosion 5\u201320 nm). The extreme surface finish requirements arise from the bonding mechanism: spontaneous SiO\u2082-to-SiO\u2082 oxide fusion at room temperature requires atomic-level surface contact \u2014 any roughness, step, or particle prevents local bonding and creates voids at the bond interface that degrade electrical yield.<\/div>\n    <\/div>\n  <\/div>\n<\/section>\n\n<\/div>\n\n<script type=\"application\/ld+json\">\n{\n  \"@context\": \"https:\/\/schema.org\",\n  \"@type\": \"FAQPage\",\n  \"mainEntity\": [\n    {\"@type\":\"Question\",\"name\":\"What is STI CMP and why is high-selectivity slurry required?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"STI CMP removes HDP-CVD oxide overburden stopping on Si3N4. High-selectivity ceria slurry (>50:1 SiO2:Si3N4) is required because the Si3N4 stop layer is thin (100\u2013200 nm) and must survive polishing intact. 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These specs are 10\u2013100\u00d7 tighter than standard CMP because spontaneous SiO2-to-SiO2 oxide fusion bonding requires atomic-level surface contact \u2014 any roughness or particle creates voids at the bond interface.\"}}\n  ]\n}\n<\/script>","protected":false},"excerpt":{"rendered":"<p>\u2190 Back to Complete Planarization Guide IC Process Integration CMP is not a single process \u2014 it is a family of distinct applications deployed at every major integration module in  &#8230;<\/p>","protected":false},"author":1,"featured_media":2392,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[9,59],"tags":[],"class_list":["post-2390","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-blog","category-industry"],"acf":[],"_links":{"self":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts\/2390","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/comments?post=2390"}],"version-history":[{"count":2,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts\/2390\/revisions"}],"predecessor-version":[{"id":2393,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts\/2390\/revisions\/2393"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/media\/2392"}],"wp:attachment":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/media?parent=2390"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/categories?post=2390"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/tags?post=2390"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}