{"id":2480,"date":"2026-07-16T13:18:10","date_gmt":"2026-07-16T05:18:10","guid":{"rendered":"https:\/\/jeez-semicon.com\/?p=2480"},"modified":"2026-07-16T13:31:26","modified_gmt":"2026-07-16T05:31:26","slug":"oxide-cmp-slurry-defects-root-causes-detection-yield-impact","status":"publish","type":"post","link":"https:\/\/jeez-semicon.com\/ja\/blog\/oxide-cmp-slurry-defects-root-causes-detection-yield-impact\/","title":{"rendered":"Oxide CMP Slurry Defects: Root Causes, Detection Methods &amp; Yield Impact"},"content":{"rendered":"<p><style>\r\n\/* JEEZ Oxide CMP Cluster Article | Jizhi Electronic Technology Co., Ltd. | jeez-semicon.com *\/\r\n#jeez-ocmp *, #jeez-ocmp *::before, #jeez-ocmp *::after { box-sizing: border-box; }\r\n#jeez-ocmp { font-family: 'Inter', system-ui, -apple-system, sans-serif; font-size: 1rem; line-height: 1.78; color: #1E293B; max-width: 100%; }\r\n#jeez-ocmp h1 { font-family: 'Syne', sans-serif; font-size: clamp(1.75rem, 5vw, 2.875rem); font-weight: 800; line-height: 1.12; color: #0B2444; letter-spacing: -0.025em; margin: 0 0 1.125rem; padding: 0; }\r\n#jeez-ocmp h2 { font-family: 'Syne', sans-serif; font-size: clamp(1.2rem, 3vw, 1.625rem); font-weight: 700; color: #0B2444; margin: 3rem 0 1rem; padding: 0 0 0 1.125rem; position: relative; scroll-margin-top: 90px; }\r\n#jeez-ocmp h2::before { content: ''; position: absolute; left: 0; top: 0.15em; bottom: 0.1em; width: 4px; background: linear-gradient(180deg, #1A6EFF, #0A4DCC); border-radius: 2px; }\r\n#jeez-ocmp h3 { font-family: 'Syne', sans-serif; font-size: clamp(1rem, 2.5vw, 1.2rem); font-weight: 700; color: #0B2444; margin: 1.875rem 0 0.75rem; padding: 0; }\r\n#jeez-ocmp h4 { font-family: 'Syne', sans-serif; font-size: 0.9375rem; font-weight: 700; color: #0F3870; margin: 1.375rem 0 0.5rem; padding: 0; }\r\n#jeez-ocmp p { margin: 0 0 1.2rem; color: #334155; }\r\n#jeez-ocmp ul, #jeez-ocmp ol { margin: 0.5rem 0 1.2rem; padding-left: 1.5rem; }\r\n#jeez-ocmp li { margin-bottom: 0.45rem; color: #334155; }\r\n#jeez-ocmp strong { font-weight: 600; color: #0B2444; }\r\n#jeez-ocmp em { font-style: italic; }\r\n#jeez-ocmp a { color: #1A6EFF; text-decoration: none; transition: color 0.15s; }\r\n#jeez-ocmp a:hover { color: #0A4DCC; text-decoration: underline; }\r\n#jeez-ocmp sub, #jeez-ocmp sup { font-size: 72%; line-height: 0; position: relative; vertical-align: baseline; }\r\n#jeez-ocmp sub { bottom: -0.25em; }\r\n#jeez-ocmp sup { top: -0.5em; }\r\n.ocmp-meta { display: flex; flex-wrap: wrap; align-items: center; gap: 0.5rem 1.5rem; padding: 0.875rem 0 1.5rem; border-bottom: 1px solid #E2EAF4; margin-bottom: 2rem; font-size: 0.8125rem; color: #64748B; }\r\n.ocmp-lead { font-size: 1.0625rem; line-height: 1.8; color: #2D4060; margin-bottom: 1.375rem; }\r\n.ocmp-toc { background: #F5F8FF; border: 1px solid #CDD8F8; border-radius: 12px; padding: 1.75rem 2rem; margin: 0 0 2.75rem; }\r\n.ocmp-toc-title { font-family: 'Syne', sans-serif; font-weight: 700; font-size: 0.75rem; text-transform: uppercase; letter-spacing: 0.1em; color: #1A6EFF; margin: 0 0 1rem; }\r\n.ocmp-toc ol { list-style: none; padding: 0; margin: 0; display: grid; grid-template-columns: repeat(auto-fill, minmax(240px, 1fr)); gap: 0.4rem 2rem; counter-reset: toc-counter; }\r\n.ocmp-toc ol li { counter-increment: toc-counter; display: flex; align-items: baseline; gap: 0.625rem; font-size: 0.875rem; line-height: 1.4; }\r\n.ocmp-toc ol li::before { content: counter(toc-counter); font-family: 'Syne', sans-serif; font-weight: 700; font-size: 0.675rem; color: #fff; background: #1A6EFF; min-width: 18px; height: 18px; border-radius: 50%; display: inline-flex; align-items: center; justify-content: center; flex-shrink: 0; }\r\n.ocmp-toc a { color: #2D4A7A; text-decoration: none; transition: color 0.15s; }\r\n.ocmp-toc a:hover { color: #1A6EFF; }\r\n.ocmp-box { border-radius: 10px; padding: 1.125rem 1.375rem; margin: 1.75rem 0; font-size: 0.9375rem; }\r\n.ocmp-box p { margin: 0; color: inherit; }\r\n.ocmp-box ul { margin: 0.375rem 0 0; }\r\n.ocmp-box-label { font-family: 'Syne', sans-serif; font-size: 0.7rem; font-weight: 700; text-transform: uppercase; letter-spacing: 0.08em; margin: 0 0 0.375rem; display: block; }\r\n.ocmp-box.info { background: #EEF4FF; border-left: 3px solid #1A6EFF; color: #1E3A6A; }\r\n.ocmp-box.info .ocmp-box-label { color: #1A6EFF; }\r\n.ocmp-box.key { background: #ECFDF5; border-left: 3px solid #059669; color: #1A3A2E; }\r\n.ocmp-box.key .ocmp-box-label { color: #059669; }\r\n.ocmp-box.caution { background: #FFFBEB; border-left: 3px solid #D97706; color: #44290A; }\r\n.ocmp-box.caution .ocmp-box-label { color: #B45309; }\r\n.ocmp-table-wrap { overflow-x: auto; margin: 1.75rem 0; border-radius: 12px; border: 1px solid #DDE5F0; box-shadow: 0 1px 3px rgba(0,0,0,0.06); }\r\n.ocmp-table-wrap table { width: 100%; border-collapse: collapse; font-size: 0.875rem; min-width: 480px; }\r\n.ocmp-table-wrap thead th { background: #0B2444; color: #D0DEFA; font-family: 'Syne', sans-serif; font-weight: 600; font-size: 0.74rem; text-transform: uppercase; letter-spacing: 0.055em; padding: 0.875rem 1rem; text-align: left; white-space: nowrap; }\r\n.ocmp-table-wrap thead th:first-child { border-radius: 11px 0 0 0; }\r\n.ocmp-table-wrap thead th:last-child { border-radius: 0 11px 0 0; }\r\n.ocmp-table-wrap tbody td { padding: 0.75rem 1rem; border-bottom: 1px solid #EEF2FA; color: #334155; vertical-align: top; line-height: 1.55; }\r\n.ocmp-table-wrap tbody tr:last-child td { border-bottom: none; }\r\n.ocmp-table-wrap tbody tr:nth-child(even) td { background: #F7F9FD; }\r\n.ocmp-table-wrap tbody tr:hover td { background: #EEF4FF; transition: background 0.12s; }\r\n.ocmp-td-label { font-weight: 600; color: #0B2444; white-space: nowrap; }\r\n.ocmp-compare { display: grid; grid-template-columns: 1fr 1fr; gap: 1.25rem; margin: 1.75rem 0; }\r\n.ocmp-compare-col { border: 1px solid #E2E8F0; border-radius: 10px; padding: 1.375rem 1.5rem; background: #fff; }\r\n.ocmp-compare-col-title { font-family: 'Syne', sans-serif; font-size: 0.9375rem; font-weight: 700; padding-bottom: 0.625rem; margin: 0 0 0.875rem; border-bottom-width: 2px; border-bottom-style: solid; }\r\n.ocmp-compare-col.blue .ocmp-compare-col-title { color: #1A6EFF; border-bottom-color: #1A6EFF; }\r\n.ocmp-compare-col.teal .ocmp-compare-col-title { color: #059669; border-bottom-color: #059669; }\r\n.ocmp-compare-col.amber .ocmp-compare-col-title { color: #D97706; border-bottom-color: #D97706; }\r\n.ocmp-compare-col ul { padding-left: 1.125rem; margin: 0; }\r\n.ocmp-compare-col li { font-size: 0.875rem; margin-bottom: 0.45rem; color: #334155; }\r\n.ocmp-back { background: #F5F8FF; border: 1px solid #C8D8F8; border-radius: 10px; padding: 1.125rem 1.5rem; margin: 2.5rem 0; font-size: 0.9rem; color: #2D4A7A; }\r\n.ocmp-back a { color: #1A6EFF; font-weight: 600; }\r\n.ocmp-faq { margin: 1.5rem 0 2rem; }\r\n.ocmp-faq-item { border: 1px solid #E2EAF4; border-radius: 10px; margin-bottom: 0.75rem; overflow: hidden; }\r\n.ocmp-faq-q { font-family: 'Syne', sans-serif; font-weight: 700; font-size: 0.9375rem; color: #0B2444; padding: 1.125rem 1.25rem; background: #F5F8FF; display: block; margin: 0; border-bottom: 1px solid #E2EAF4; line-height: 1.45; }\r\n.ocmp-faq-a { padding: 1rem 1.25rem; font-size: 0.9rem; color: #334155; margin: 0; line-height: 1.72; }\r\n.ocmp-hr { border: none; border-top: 1px solid #E2EAF4; margin: 2.5rem 0; }\r\n@media (max-width: 640px) {\r\n  .ocmp-compare { grid-template-columns: 1fr; }\r\n  .ocmp-toc ol { grid-template-columns: 1fr; }\r\n  #jeez-ocmp h2 { margin-top: 2.25rem; }\r\n}\r\n<\/style><\/p>\r\n<article id=\"jeez-ocmp\">\r\n<div class=\"ocmp-meta\">\ud83d\udcc5 July 2026\u00b7\u23f1 18 min read\u00b7\u270d\ufe0f JEEZ Technical Team<\/div>\r\n<p class=\"ocmp-lead\">Defects introduced during oxide CMP are among the most yield-consequential defects in the semiconductor manufacturing flow. Unlike contamination defects that can sometimes be cleaned, CMP-induced physical defects \u2014 scratches, particle residues, dishing \u2014 alter the permanent topology of the wafer surface and cannot be corrected by downstream cleaning steps. This guide provides a complete taxonomy of oxide CMP slurry defect types, their root causes, detection strategies, and yield impact quantification. For an overview of oxide CMP slurry fundamentals, see our <a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/oxide-cmp-slurry\/\" target=\"_blank\" rel=\"noopener noreferrer\">Oxide CMP Slurry: Complete Technical Guide<\/a>.<\/p>\r\n<nav class=\"ocmp-toc\" aria-label=\"\u76ee\u6b21\">\r\n<p class=\"ocmp-toc-title\">\u76ee\u6b21<\/p>\r\n<ol>\r\n<li><a href=\"#def-impact\">Why CMP Defects Matter<\/a><\/li>\r\n<li><a href=\"#def-scratch\">Micro-Scratches<\/a><\/li>\r\n<li><a href=\"#def-residue\">Ceria Particle Residue<\/a><\/li>\r\n<li><a href=\"#def-dishing\">Dishing &amp; Erosion<\/a><\/li>\r\n<li><a href=\"#def-contamination\">Contamination Defects<\/a><\/li>\r\n<li><a href=\"#def-detection\">Inspection &amp; Detection Methods<\/a><\/li>\r\n<li><a href=\"#def-yield\">Yield Impact &amp; Cost of Poor Quality<\/a><\/li>\r\n<li><a href=\"#def-faq\">\u3088\u304f\u3042\u308b\u8cea\u554f<\/a><\/li>\r\n<\/ol>\r\n<\/nav>\r\n<h2 id=\"def-impact\">Why CMP Defects Matter<\/h2>\r\n<p>CMP-induced defects can impact final device yield through three distinct failure modes:<\/p>\r\n<p><strong>Immediate kills:<\/strong> Defects that cause direct electrical failure at the die level \u2014 metal shorts from scratch-displaced material, open circuits from particle contamination bridging isolated features. These are detected by end-of-line electrical test and translate directly to die loss.<\/p>\r\n<p><strong>Latent reliability failures:<\/strong> Defects that do not cause immediate electrical failure but create weakened structures that fail under bias-temperature stress or electromigration during device operation. These pass end-of-line test but contribute to early-life field failure \u2014 the most costly yield-loss mechanism for mission-critical applications.<\/p>\r\n<p><strong>Process propagation:<\/strong> Defects that do not directly affect the CMP step&#8217;s own quality but alter the surface presented to subsequent process steps \u2014 a scratch in oxide creates a step at the next metal deposition, an edge bead from dishing creates lithographic focus variation. These indirect effects on downstream yield are often harder to attribute to their CMP root cause.<\/p>\r\n<p>For reference on the process parameters that most directly drive defect generation, see our article on <a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/Oxide-CMP-Process-Parameters-MRR-Within-Wafer-Uniformity-Endpoint-Detection\/\" target=\"_blank\" rel=\"noopener noreferrer\">Oxide CMP Process Parameters: MRR, Uniformity &amp; Endpoint Detection<\/a>.<\/p>\r\n<h2 id=\"def-scratch\">Micro-Scratches<\/h2>\r\n<p>Micro-scratches are the most commonly encountered and most analytically characterized defect type in oxide CMP. They appear as linear or curved grooves on the polished oxide surface, ranging from sub-50 nm deep (sub-critical) to several hundred nanometers deep (catastrophic).<\/p>\r\n<h3>Root Causes<\/h3>\r\n<p><strong>Abrasive particle aggregates (&#8220;killer particles&#8221;):<\/strong> Abrasive particles that aggregate into clusters above approximately 0.5\u20131 \u00b5m in effective diameter can score the oxide surface under polishing load. Aggregation is the primary source of micro-scratches in both colloidal silica and ceria slurries. Triggers for aggregation include: pH drift away from the colloidal stability optimum; temperature excursion (typically above 35\u00b0C); contamination of the slurry bath with metal ions (particularly Ca<sup>2+<\/sup>, Mg<sup>2+<\/sup>); and inadequate point-of-use filtration allowing aggregates that formed in the supply line to reach the pad.<\/p>\r\n<p><strong>Pad debris:<\/strong> Fragments of polishing pad material (polyurethane or IC1000 pad) released during aggressive conditioning or pad break-in can act as abrasives themselves, generating scratches that are broader and shallower than abrasive-particle scratches and tend to appear in clusters correlated with pad conditioning events.<\/p>\r\n<p><strong>Dried slurry on wafer:<\/strong> If slurry dries on the wafer during handling between polishing and cleaning, dried slurry agglomerates can scratch the wafer during subsequent processing. This is prevented by wafer-on-pad rinsing before unloading and maintaining wet conditions throughout transfer to the cleaning station.<\/p>\r\n<h3>Mitigation Strategies<\/h3>\r\n<ul>\r\n<li>Point-of-use filtration at 0.2\u20130.5 \u00b5m absolute (verify filter integrity at every maintenance interval)<\/li>\r\n<li>Slurry bath temperature monitoring with alarm thresholds (typically &lt;30\u00b0C for ILD; &lt;25\u00b0C for STI)<\/li>\r\n<li>Real-time pH monitoring with automatic supply shutoff on pH deviation exceeding \u00b10.5 units from target<\/li>\r\n<li>Slurry supply line cleanliness audits \u2014 inspect for dried slurry deposits at nozzle junctions quarterly<\/li>\r\n<li>Pad conditioning disk inspection at each pad change \u2014 worn conditioner disks produce larger pad debris particles<\/li>\r\n<\/ul>\r\n<h2 id=\"def-residue\">Ceria Particle Residue<\/h2>\r\n<p>Ceria particle residue is a defect category unique to STI CMP and other ceria-based polishing applications. Ceria nanoparticles that form Ce\u2013O\u2013Si bonds with the polished SiO<sub>2<\/sub> surface during polishing resist removal by standard DI water rinse and SC-1 alkaline cleaning \u2014 the same alkaline conditions that are effective for silica particle removal actually promote Ce\u2013O\u2013Si bond stability.<\/p>\r\n<h3>Detection<\/h3>\r\n<p>Ceria residue detection is performed by automated defect inspection using a bright-field or dark-field laser scanning system (KLA Tencor SP-Series, Applied Materials Entera, SCREEN SURFscan). Ceria particles appear as bright point defects against the polished oxide surface. X-ray photoelectron spectroscopy (XPS) or energy-dispersive X-ray analysis (EDX\/EDS) in a scanning electron microscope confirms cerium elemental identity. Post-cleaning residue counts of &gt;0.05 particles\/cm\u00b2 (&gt;70 nm PSL equivalent) above background indicate insufficient ceria removal and require cleaning process adjustment.<\/p>\r\n<h3>Consequences<\/h3>\r\n<p>Residual ceria particles in FEOL applications (between the STI CMP step and subsequent gate oxide or gate dielectric deposition) create localized charge centers that perturb transistor threshold voltage and increase gate oxide defect density. In severe cases, ceria agglomerates larger than the gate dielectric thickness (&lt;2 nm at advanced nodes) can physically puncture the gate oxide and create device shorts. For ceria residue removal protocols, refer to our dedicated article: <a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/Post-CMP-Cleaning-Oxide-Slurry-Chemistry-Equipment-Integration-Guide\/\" target=\"_blank\" rel=\"noopener noreferrer\">Post-CMP Cleaning for Oxide Slurry Processes<\/a>.<\/p>\r\n<h2 id=\"def-dishing\">Dishing &amp; Erosion<\/h2>\r\n<p>Dishing and erosion are not particle defects but geometric deformations of the polished surface. They are characteristic of STI CMP and, to a lesser extent, ILD CMP over wide metal features.<\/p>\r\n<h3>\u30c7\u30a3\u30c3\u30b7\u30f3\u30b0<\/h3>\r\n<p>Dishing is the concave surface profile that develops in the center of wide oxide-filled features (typically &gt;1 \u00b5m width) during STI CMP. The polishing pad conforms to the trench geometry and continues polishing the oxide fill at the feature center even after the surrounding oxide has been removed, creating a dish-shaped depression. The depth of dishing increases with feature width, polishing time past oxide clear, and pad compliance (softer pads dish more). Dishing depths of 5\u201330 nm are typical at FinFET nodes for isolation features in the 1\u20135 \u00b5m width range.<\/p>\r\n<p>Dishing affects transistor performance by creating a non-flat silicon surface at the base of each isolation trench, which propagates into shallow diffusion layer profiles and affects junction depth uniformity. For FinFET devices where fin height must be controlled to \u00b10.5 nm, dishing-induced height variation across different circuit contexts is a significant integration challenge.<\/p>\r\n<h3>\u6d78\u98df<\/h3>\r\n<p>Erosion is the non-uniform thinning of the Si<sub>3<\/sub>N<sub>4<\/sub> hard mask observed across dense active-area arrays in STI CMP. Dense arrays present a higher density of oxide-to-nitride transitions per unit area, creating higher local ceria abrasive contact frequency on the nitride surface and resulting in greater nitride loss than occurs in sparse regions \u2014 despite the high bulk selectivity of the ceria slurry. Erosion of 2\u201310 nm in dense arrays versus sparse regions is typical at 5\u20137 nm FinFET nodes; this variation translates directly to fin height non-uniformity across different circuit contexts on the die.<\/p>\r\n<h3>Control Strategies<\/h3>\r\n<p>Dishing and erosion are interdependent and partially opposed in their control: strategies that reduce dishing (harder pads, lower pressure) tend to increase erosion by increasing abrasive contact with nitride surfaces. The standard production approach is a two-step STI CMP process with a high-selectivity second step optimized for erosion control, combined with layout-level dummy pattern insertion to equalize pattern density and reduce the driving force for erosion.<\/p>\r\n<h2 id=\"def-contamination\">Contamination Defects<\/h2>\r\n<p>Beyond particle and geometric defects, oxide CMP can introduce chemical contamination that affects device performance without generating visually detectable surface defects:<\/p>\r\n<p><strong>Metal ion contamination:<\/strong> Potassium ions (K<sup>+<\/sup>) from KOH-based ILD slurry can diffuse into SiO<sub>2<\/sub> and reach the Si\/SiO<sub>2<\/sub> interface, creating fixed charges that shift transistor threshold voltages. KOH-based slurry should not be used for ILD steps adjacent to active device regions; NH<sub>4<\/sub>OH-formulated slurries eliminate this risk.<\/p>\r\n<p><strong>Cerium ion incorporation:<\/strong> If Ce ions dissolve from ceria particles into the polishing solution and are not removed by post-CMP cleaning, Ce can incorporate into the SiO<sub>2<\/sub> surface layer, creating trap states in the oxide that elevate gate dielectric leakage current. This contamination mode is manageable with optimized post-CMP cleaning but requires verification at each ceria slurry qualification.<\/p>\r\n<p><strong>Organic contamination:<\/strong> Surfactants, polymer additives (PAA), and dispersants in slurry formulations can adsorb onto the polished oxide surface and resist standard aqueous cleaning. Residual organic contamination at &gt;10<sup>13<\/sup> carbon atoms\/cm<sup>2<\/sup> can affect subsequent gate dielectric quality metrics. UV-ozone or dilute H<sub>2<\/sub>O<sub>2<\/sub> treatment in the post-CMP clean sequence addresses this when standard cleaning is insufficient.<\/p>\r\n<h2 id=\"def-detection\">Inspection &amp; Detection Methods<\/h2>\r\n<p>Effective oxide CMP defect control requires a tiered inspection strategy that balances detection sensitivity against throughput and cost:<\/p>\r\n<div class=\"ocmp-table-wrap\">\r\n<table>\r\n<thead>\r\n<tr>\r\n<th>Inspection Type<\/th>\r\n<th>Equipment<\/th>\r\n<th>Detection Capability<\/th>\r\n<th>When Applied<\/th>\r\n<\/tr>\r\n<\/thead>\r\n<tbody>\r\n<tr>\r\n<td class=\"ocmp-td-label\">Bright-Field Laser Scanning<\/td>\r\n<td>KLA SP-7\/8, SCREEN SURFscan<\/td>\r\n<td>Particles &gt;20 nm PSL; scratches &gt;50 nm wide<\/td>\r\n<td>Every wafer (AEI, post-clean)<\/td>\r\n<\/tr>\r\n<tr>\r\n<td class=\"ocmp-td-label\">Dark-Field Laser Scanning<\/td>\r\n<td>Applied Materials Entera, KLA Surfscan<\/td>\r\n<td>Micro-scratches &gt;30 nm; haze from sub-20 nm particles<\/td>\r\n<td>Lot sampling (AEI)<\/td>\r\n<\/tr>\r\n<tr>\r\n<td class=\"ocmp-td-label\">SEM\/EDX Review<\/td>\r\n<td>Hitachi CD-SEM, ZEISS CrossBeam<\/td>\r\n<td>Particle chemistry, scratch morphology, depth estimation<\/td>\r\n<td>Triggered by laser scan excursion<\/td>\r\n<\/tr>\r\n<tr>\r\n<td class=\"ocmp-td-label\">AFM (Atomic Force Microscopy)<\/td>\r\n<td>Bruker Dimension, Keysight 9500<\/td>\r\n<td>Surface roughness Ra to &lt;0.05 nm; dishing\/erosion depth<\/td>\r\n<td>Qualification; periodic sampling<\/td>\r\n<\/tr>\r\n<tr>\r\n<td class=\"ocmp-td-label\">Optical Profilometry<\/td>\r\n<td>KLA P-20H, Bruker ContourX<\/td>\r\n<td>Dishing &gt;2 nm; step height; wafer bow<\/td>\r\n<td>Process development; periodic monitoring<\/td>\r\n<\/tr>\r\n<tr>\r\n<td class=\"ocmp-td-label\">XPS<\/td>\r\n<td>Thermo Fisher, Kratos<\/td>\r\n<td>Surface chemistry; Ce, K contamination; organic residue<\/td>\r\n<td>Qualification; contamination investigation<\/td>\r\n<\/tr>\r\n<\/tbody>\r\n<\/table>\r\n<\/div>\r\n<h2 id=\"def-yield\">Yield Impact &amp; Cost of Poor Quality<\/h2>\r\n<p>Quantifying the yield impact of oxide CMP defects requires connecting defect density and defect size distribution to the probability that any given defect intersects a yield-critical layout feature. The standard framework is the Poisson yield model:<\/p>\r\n<p><strong>Y = exp(\u2013D\u2080 \u00d7 A<sub>critical<\/sub>)<\/strong><\/p>\r\n<p>where D\u2080 is the critical defect density (defects\/cm\u00b2 that can cause a failure) and A<sub>critical<\/sub> is the critical area per die that is sensitive to the defect type in question. For a 300 mm advanced-node logic die with A<sub>critical<\/sub> = 500 mm\u00b2 and a scratch defect specification of D\u2080 &lt;0.02\/cm\u00b2, the predicted yield loss from scratches alone is approximately 1\u20132% \u2014 a significant contribution to total fab yield loss that justifies aggressive defect control investment.<\/p>\r\n<p>The cost of oxide CMP defect excursions extends beyond direct yield loss to include: quarantine and retest of affected lots; root cause investigation time; potential exposure of downstream wafers to defective slurry before the excursion is detected; and customer notification requirements for shipped product found to have been processed with out-of-control consumables. For large logic die ($500\u20132,000 each at 3 nm node), a single 25-wafer lot with 5% incremental yield loss from a scratch excursion represents $30,000\u2013$120,000 in lost die value plus investigation costs.<\/p>\r\n<div class=\"ocmp-back\">\u2190 Part of the JEEZ Oxide CMP Slurry series. Return to the <a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/oxide-cmp-slurry\/\" target=\"_blank\" rel=\"noopener noreferrer\">Oxide CMP Slurry: Complete Technical &amp; Procurement Guide<\/a><\/div>\r\n<hr class=\"ocmp-hr\" \/>\r\n<h2 id=\"def-faq\">Frequently Asked Questions: Oxide CMP Defects<\/h2>\r\n<div class=\"ocmp-faq\">\r\n<div class=\"ocmp-faq-item\">\r\n<p class=\"ocmp-faq-q\">What is the most common oxide CMP defect in production?<\/p>\r\n<p class=\"ocmp-faq-a\">Micro-scratches are the most commonly encountered and monitored oxide CMP defect in production. They result from abrasive particle aggregates (&#8220;killer particles&#8221;) above ~0.5 \u00b5m contacting the wafer surface under polishing load. They are more prevalent with ceria STI slurry (harder particles, higher aggregation tendency) than with colloidal silica ILD slurry. Mitigation requires point-of-use filtration, pH and temperature control, and slurry supply line cleanliness programs.<\/p>\r\n<\/div>\r\n<div class=\"ocmp-faq-item\">\r\n<p class=\"ocmp-faq-q\">How is ceria particle residue detected after STI CMP?<\/p>\r\n<p class=\"ocmp-faq-a\">Ceria residue is detected by automated laser scanning inspection (bright-field or dark-field) using a wafer surface scanner such as KLA SP-7\/8 or SCREEN SURFscan, with particle sensitivity to 20\u201370 nm PSL equivalent. Chemical identity is confirmed by SEM\/EDX (cerium peaks) or XPS (Ce 3d binding energy peaks). Post-cleaning residue counts above 0.05 particles\/cm\u00b2 (&gt;70 nm) above background indicate inadequate cleaning and require protocol adjustment.<\/p>\r\n<\/div>\r\n<div class=\"ocmp-faq-item\">\r\n<p class=\"ocmp-faq-q\">What is the difference between STI dishing and erosion?<\/p>\r\n<p class=\"ocmp-faq-a\">Dishing is the concave depression that develops within individual wide isolation trenches (&gt;1 \u00b5m), caused by pad conformance continuing to polish oxide below the surrounding nitride plane. Erosion is the non-uniform thinning of the Si<sub>3<\/sub>N<sub>4<\/sub> hard mask across dense active-area arrays, caused by pattern-density-dependent polishing rate variation. Dishing occurs within features; erosion occurs across arrays of features. Both occur simultaneously during STI CMP and must be managed together through two-step process strategies and layout dummy insertion.<\/p>\r\n<\/div>\r\n<div class=\"ocmp-faq-item\">\r\n<p class=\"ocmp-faq-q\">Can oxide CMP defects cause device reliability failures?<\/p>\r\n<p class=\"ocmp-faq-a\">Yes. Latent CMP defects \u2014 particularly shallow micro-scratches that do not immediately cause electrical failure but weaken the oxide at the scratch location \u2014 can become reliability failures under electrical stress during device operation. Cerium ion incorporation in the oxide from incomplete ceria cleaning creates trap states that elevate gate dielectric leakage and reduce time-to-dielectric-breakdown (TDDB). These latent failures are particularly concerning for automotive and other long-lifetime reliability applications, where TDDB requirements are measured in decades of operation.<\/p>\r\n<\/div>\r\n<div class=\"ocmp-faq-item\">\r\n<p class=\"ocmp-faq-q\">How does slurry lot-to-lot variability affect defect performance?<\/p>\r\n<p class=\"ocmp-faq-a\">Lot-to-lot slurry variability \u2014 particularly in particle size distribution (D99 specification), pH, and polymer additive concentration \u2014 directly affects defect performance. A slurry lot with D99 above specification is likely to contain more large-particle aggregates and generate higher scratch counts. A ceria STI slurry lot with PAA concentration below specification will have inadequate particle stabilization and higher aggregation tendency. This is why incoming inspection (or supplier CoA acceptance with reference wafer verification) against D50, D99, pH, and MRR is standard practice for advanced-node oxide CMP.<\/p>\r\n<\/div>\r\n<\/div>\r\n<\/article>\r\n<p><script type=\"application\/ld+json\">\r\n{\"@context\":\"https:\/\/schema.org\",\"@type\":\"FAQPage\",\"mainEntity\":[\r\n{\"@type\":\"Question\",\"name\":\"What is the most common oxide CMP defect in production?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"Micro-scratches are the most common oxide CMP defect, from abrasive particle aggregates above ~0.5 micrometers. More prevalent with ceria than colloidal silica. Mitigation requires point-of-use filtration, pH\/temperature control, and slurry line cleanliness.\"}},\r\n{\"@type\":\"Question\",\"name\":\"How is ceria particle residue detected after STI CMP?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"Ceria residue is detected by automated laser scanning (KLA SP-7\/8, SCREEN SURFscan) with 20-70 nm PSL sensitivity, confirmed by SEM\/EDX or XPS. Counts above 0.05 particles\/cm2 above background indicate inadequate cleaning.\"}},\r\n{\"@type\":\"Question\",\"name\":\"What is the difference between STI dishing and erosion?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"Dishing is a concave depression within individual wide isolation trenches from pad conformance. Erosion is non-uniform Si3N4 thinning across dense active-area arrays from pattern-density polishing variation. Both occur simultaneously and require two-step process strategies and layout dummy insertion.\"}},\r\n{\"@type\":\"Question\",\"name\":\"Can oxide CMP defects cause device reliability failures?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"Yes. Shallow micro-scratches can become reliability failures under electrical stress. Cerium ion incorporation creates gate dielectric trap states elevating leakage and reducing TDDB. Latent failures are especially critical for automotive and long-lifetime reliability applications.\"}},\r\n{\"@type\":\"Question\",\"name\":\"How does slurry lot-to-lot variability affect defect performance?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"Lot-to-lot variability in D99, pH, and polymer concentration directly affects defects. High D99 raises scratch counts; low PAA raises ceria aggregation. Incoming inspection against D50, D99, pH, and MRR is standard for advanced-node oxide CMP.\"}}\r\n]}<\/script><\/p>","protected":false},"excerpt":{"rendered":"<p>\ud83d\udcc5 July 2026\u00b7\u23f1 18 min read\u00b7\u270d\ufe0f JEEZ Technical Team Defects introduced during oxide CMP are among the most yield-consequential defects in the semiconductor manufacturing flow. Unlike contamination defects that can  &#8230;<\/p>","protected":false},"author":1,"featured_media":2482,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[9,59],"tags":[],"class_list":["post-2480","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-blog","category-industry"],"acf":[],"_links":{"self":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts\/2480","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/comments?post=2480"}],"version-history":[{"count":3,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts\/2480\/revisions"}],"predecessor-version":[{"id":2496,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts\/2480\/revisions\/2496"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/media\/2482"}],"wp:attachment":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/media?parent=2480"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/categories?post=2480"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/tags?post=2480"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}