{"id":2544,"date":"2026-07-30T15:46:54","date_gmt":"2026-07-30T07:46:54","guid":{"rendered":"https:\/\/jeez-semicon.com\/?p=2544"},"modified":"2026-07-30T15:46:54","modified_gmt":"2026-07-30T07:46:54","slug":"dishing-and-erosion-in-copper-cmp-causes-pattern-density-effects-mitigation","status":"publish","type":"post","link":"https:\/\/jeez-semicon.com\/ja\/blog\/dishing-and-erosion-in-copper-cmp-causes-pattern-density-effects-mitigation\/","title":{"rendered":"Dishing and Erosion in Copper CMP: Causes, Pattern Density Effects &amp; Mitigation"},"content":{"rendered":"<style>\n@import url('https:\/\/fonts.googleapis.com\/css2?family=Space+Grotesk:wght@400;500;600;700;800&family=Inter:ital,wght@0,300;0,400;0,500;0,600;1,400&display=swap');\n.jz-cl*{box-sizing:border-box}.jz-cl{font-family:'Inter',-apple-system,BlinkMacSystemFont,'Segoe UI',sans-serif;font-size:17px;line-height:1.75;color:#1e293b;max-width:860px;margin:0 auto}\n.jz-cl h1{font-family:'Space Grotesk',sans-serif;font-size:clamp(1.85rem,4.5vw,2.55rem);font-weight:800;color:#0c2340;line-height:1.2;margin:0 0 1.5rem;letter-spacing:-.5px}\n.jz-cl h2{font-family:'Space Grotesk',sans-serif;font-size:clamp(1.18rem,3vw,1.58rem);font-weight:700;color:#0c2340;margin:2.8rem 0 .9rem;padding-left:15px;border-left:4px solid #B87333;line-height:1.3;scroll-margin-top:80px}\n.jz-cl h3{font-family:'Space Grotesk',sans-serif;font-size:1.1rem;font-weight:700;color:#1a3a5c;margin:2rem 0 .55rem}\n.jz-cl h4{font-family:'Space Grotesk',sans-serif;font-size:.96rem;font-weight:700;color:#334155;margin:1.3rem 0 .4rem}\n.jz-cl p{margin:0 0 1.2rem}.jz-cl ul,.jz-cl ol{margin:0 0 1.2rem;padding-left:1.5rem}.jz-cl li{margin-bottom:.45rem;line-height:1.68}\n.jz-cl strong{color:#0c2340;font-weight:600}.jz-cl sub,.jz-cl sup{font-size:.72em}\n.jz-cl a{color:#1d4ed8;text-decoration:underline;text-decoration-color:rgba(29,78,216,.28);text-underline-offset:3px;transition:color .15s}.jz-cl a:hover{color:#B87333;text-decoration-color:#B87333}\n.jz-hero{background:linear-gradient(135deg,#0c2340,#1a4480);border-top:5px solid #B87333;border-radius:14px;padding:28px 34px;color:#fff;margin:0 0 2.4rem;position:relative;overflow:hidden}\n.jz-hero::before{content:'';position:absolute;top:-50px;right:-50px;width:180px;height:180px;border-radius:50%;background:rgba(184,115,51,.08)}\n.jz-hero p{font-size:1.02rem;opacity:.9;margin:0;line-height:1.62;position:relative}.jz-hero strong{color:#f4c07e}\n.jz-toc{background:#f8fafc;border:1px solid #dde4ee;border-left:4px solid #B87333;border-radius:10px;padding:20px 24px 16px;margin:0 0 2.4rem}\n.jz-toc-hd{font-family:'Space Grotesk',sans-serif;font-size:.73rem;font-weight:800;letter-spacing:.12em;text-transform:uppercase;color:#94a3b8;margin:0 0 11px}\n.jz-toc ol{margin:0;padding:0;list-style:none}.jz-toc li{margin-bottom:5px;font-size:.9rem;display:flex;align-items:baseline;gap:6px}\n.jz-toc-n{font-family:'Space Grotesk',sans-serif;font-size:.7rem;font-weight:800;color:#B87333;flex-shrink:0}\n.jz-toc a{color:#334155;text-decoration:none;font-weight:500}.jz-toc a:hover{color:#B87333}\n.jz-pillar-banner{display:flex;align-items:flex-start;gap:11px;background:linear-gradient(90deg,#eff6ff,#fef9f0);border:1px solid #bfdbfe;border-radius:9px;padding:13px 17px;margin:0 0 2rem}\n.jz-pillar-banner p{margin:0;font-size:.9rem;color:#1e40af;line-height:1.5}.jz-pillar-banner a{color:#1e40af;font-weight:600}.jz-pillar-banner a:hover{color:#B87333}\n.jz-callout{border-radius:9px;padding:15px 19px;margin:1.5rem 0;border-left:4px solid}.jz-callout p{margin:0;font-size:.92rem;line-height:1.6}\n.jz-ci{background:#eff6ff;border-color:#3b82f6}.jz-ci strong{color:#1e40af}\n.jz-ct{background:#f0fdf4;border-color:#22c55e}.jz-ct strong{color:#15803d}\n.jz-cw{background:#fff7ed;border-color:#f97316}.jz-cw strong{color:#9a3412}\n.jz-cc{background:#fef9f0;border-color:#B87333}.jz-cc strong{color:#92400e}\n.jz-tw{overflow-x:auto;margin:1.5rem 0;border-radius:10px;border:1px solid #e2e8f0}\n.jz-tab{width:100%;border-collapse:collapse;font-size:.88rem}.jz-tab thead{background:#0c2340}\n.jz-tab thead th{padding:11px 15px;text-align:left;color:#fff;font-family:'Space Grotesk',sans-serif;font-weight:600;font-size:.75rem;text-transform:uppercase;letter-spacing:.06em}\n.jz-tab tbody tr{border-bottom:1px solid #f1f5f9}.jz-tab tbody tr:last-child{border-bottom:none}.jz-tab tbody tr:nth-child(even){background:#f8fafc}.jz-tab tbody tr:hover{background:#f0f7ff}\n.jz-tab td{padding:10px 15px;vertical-align:top;color:#334155;line-height:1.5}.jz-tab td:first-child{font-weight:600;color:#0c2340}\n.jz-related{background:#f8fafc;border:1px solid #e2e8f0;border-radius:10px;padding:17px 21px;margin:2rem 0}\n.jz-related h3{font-size:.75rem;font-weight:800;letter-spacing:.1em;text-transform:uppercase;color:#94a3b8;margin:0 0 10px}\n.jz-related ul{margin:0;padding:0;list-style:none}.jz-related li{margin-bottom:7px;font-size:.91rem}.jz-related li::before{content:'\u2192 ';color:#B87333;font-weight:700}\n.jz-cta{background:linear-gradient(135deg,#0c2340,#1a4480);border-top:5px solid #B87333;border-radius:14px;padding:36px 42px;text-align:center;color:#fff;margin:3.5rem 0 2rem;position:relative;overflow:hidden}\n.jz-cta::before{content:'';position:absolute;top:-70px;right:-70px;width:250px;height:250px;border-radius:50%;background:rgba(184,115,51,.06)}\n.jz-cta h2{font-family:'Space Grotesk',sans-serif;font-size:clamp(1.28rem,3vw,1.62rem);font-weight:800;color:#fff;margin:0 0 10px;border:none;padding:0;position:relative}\n.jz-cta p{opacity:.85;font-size:.96rem;margin:0 0 24px;position:relative}\n.jz-cta-btn{display:inline-block;background:#B87333;color:#fff;text-decoration:none;font-family:'Space Grotesk',sans-serif;font-weight:700;font-size:.97rem;padding:13px 32px;border-radius:8px;transition:background .2s,transform .15s;position:relative}\n.jz-cta-btn:hover{background:#9a6228;color:#fff;text-decoration:none;transform:translateY(-2px)}\n.jz-faq{border-top:1px solid #e2e8f0;margin:.8rem 0}.jz-faq-item{border-bottom:1px solid #f1f5f9;padding:1.15rem 0}\n.jz-faq-q{font-family:'Space Grotesk',sans-serif;font-weight:700;color:#0c2340;font-size:.96rem;margin:0 0 5px}\n.jz-faq-a{font-size:.91rem;color:#475569;margin:0;line-height:1.65}\n.jz-hr{border:none;border-top:1px solid #e2e8f0;margin:2.5rem 0}\n@media(max-width:640px){.jz-cl h1{font-size:1.7rem}.jz-cl h2{font-size:1.15rem}.jz-hero{padding:20px 18px}.jz-cta{padding:26px 20px}}\n<\/style>\n\n<div class=\"jz-cl\">\n\n<div class=\"jz-pillar-banner\">\n  <span>\ud83d\udcda<\/span>\n  <p>Part of the <strong>\u9285CMP\u30b9\u30e9\u30ea\u30fc<\/strong> knowledge series. For the complete process overview, see the <a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/Copper-CMP-Slurry-Complete-Guide-Chemistry-Process-Optimization-Advanced-Node-Applications\/\" target=\"_blank\" rel=\"noopener noreferrer\">Copper CMP Slurry: Complete Guide<\/a>.<\/p>\n<\/div>\n\n\n<div class=\"jz-hero\">\n  <p>Dishing and erosion are the two defining topographic defects of copper CMP \u2014 and controlling them simultaneously is one of the most difficult challenges in BEOL process integration. <strong>\u30c7\u30a3\u30c3\u30b7\u30f3\u30b0<\/strong> recesses the copper line below the surrounding dielectric, raising interconnect resistance and threatening electromigration lifetime. <strong>\u6d78\u98df<\/strong> thins the dielectric in dense metal arrays, threatening isolation integrity and creating planarity nonuniformities that compound across multiple metal levels. This article covers the root causes, measurement approaches, and the full toolkit of slurry, process, and design mitigations available to control both defects in 2026 production environments.<\/p>\n<\/div>\n\n<div class=\"jz-toc\">\n  <p class=\"jz-toc-hd\">\u76ee\u6b21<\/p>\n  <ol>\n    <li><span class=\"jz-toc-n\">01.<\/span><a href=\"#impact\">Why Dishing and Erosion Are Critical Yield Drivers<\/a><\/li>\n    <li><span class=\"jz-toc-n\">02.<\/span><a href=\"#dishing\">Copper Dishing: Mechanism, Measurement &amp; Feature-Width Dependence<\/a><\/li>\n    <li><span class=\"jz-toc-n\">03.<\/span><a href=\"#erosion\">Dielectric Erosion: Pattern Density Effects &amp; Measurement<\/a><\/li>\n    <li><span class=\"jz-toc-n\">04.<\/span><a href=\"#tradeoff\">The Dishing\u2013Erosion Tradeoff<\/a><\/li>\n    <li><span class=\"jz-toc-n\">05.<\/span><a href=\"#slurry-mit\">Slurry-Side Mitigation Strategies<\/a><\/li>\n    <li><span class=\"jz-toc-n\">06.<\/span><a href=\"#process-mit\">Process-Side Mitigation Strategies<\/a><\/li>\n    <li><span class=\"jz-toc-n\">07.<\/span><a href=\"#design-mit\">Design-Side Mitigation: CMP-Aware Design<\/a><\/li>\n    <li><span class=\"jz-toc-n\">08.<\/span><a href=\"#faq\">\u3088\u304f\u3042\u308b\u8cea\u554f<\/a><\/li>\n  <\/ol>\n<\/div>\n\n<h2 id=\"impact\">1. Why Dishing and Erosion Are Critical Yield Drivers<\/h2>\n<p>Copper interconnect resistance is proportional to the reciprocal of the cross-sectional area of the metal line. Even modest dishing or erosion can drive significant resistance increase:<\/p>\n<ul>\n  <li>A copper line 100 nm wide \u00d7 100 nm tall that dishes by 10 nm loses 10% of its cross-sectional area and experiences approximately 10% higher resistance \u2014 potentially shifting a critical timing path outside specification.<\/li>\n  <li>At 7 nm node interconnect dimensions (copper line width \u2248 15\u201320 nm, height \u2248 25\u201330 nm), even 2\u20133 nm of dishing represents 10\u201315% cross-sectional loss \u2014 pushing well beyond parametric budget.<\/li>\n<\/ul>\n<p>Beyond resistance increase, dishing and erosion generate planarity nonuniformity that compounds upward through the metal stack. The next dielectric deposition fills into the topographic variation created by dishing and erosion at layer N, creating local thickness variations that affect via depth at layer N+1, which in turn creates etch nonuniformity at layer N+2. By the time the process reaches upper metal layers, topographic errors from lower levels have been amplified through multiple deposition and etch steps.<\/p>\n\n<div class=\"jz-callout jz-cw\">\n  <p><strong>Reliability impact:<\/strong> Beyond resistance, dishing creates local current density hotspots at the thinned sections of copper lines. Electromigration (EM) lifetime scales inversely with the square of current density: a 15% dishing-driven current density increase reduces EM lifetime by approximately 25% \u2014 a significant reliability margin loss for products targeting 10+ year operational lifetimes.<\/p>\n<\/div>\n\n<h2 id=\"dishing\">2. Copper Dishing: Mechanism, Measurement &amp; Feature-Width Dependence<\/h2>\n\n<h3>Dishing Mechanism<\/h3>\n<p>Copper dishing arises from two concurrent mechanisms acting on the copper in completed trench features during CMP:<\/p>\n<p><strong>Mechanical mechanism:<\/strong> The polishing pad is an elastic solid that deflects under the applied downforce. When the pad crosses a wide copper trench, it partially deflects into the trench opening under the locally unsupported span, bringing abrasive particles into contact with the copper below the level of the surrounding dielectric. The deflection magnitude \u2014 and therefore the dishing contribution \u2014 scales with feature width, pad compliance (softer pads dish more), and applied pressure.<\/p>\n<p><strong>Chemical mechanism:<\/strong> Even without pad contact, the slurry&#8217;s oxidizer and complexing agent continuously dissolve copper through the static etch rate (SER) mechanism. In the recessed trench feature, where no pad contact occurs, this isotropic chemical dissolution removes copper uniformly from all surfaces \u2014 floor and sidewalls \u2014 at the SER. Over the duration of the polishing process, this chemical contribution can add 1\u20135 nm to the total dishing depending on SER and process time.<\/p>\n\n<h3>Feature-Width Dependence<\/h3>\n<p>The mechanical contribution to dishing scales strongly with feature width because pad deflection into the trench scales with the unsupported span width. This creates the characteristic feature-width dependence of copper dishing:<\/p>\n<div class=\"jz-tw\">\n  <table class=\"jz-tab\">\n    <thead><tr><th>Feature Width<\/th><th>Typical Dishing (Hard Pad)<\/th><th>Typical Dishing (Soft Pad)<\/th><th>\u652f\u914d\u7684\u30e1\u30ab\u30cb\u30ba\u30e0<\/th><\/tr><\/thead>\n    <tbody>\n      <tr><td>10\u201350 nm logic lines<\/td><td>1\u20133 nm<\/td><td>2\u20135 nm<\/td><td>Primarily chemical (SER-driven)<\/td><\/tr>\n      <tr><td>100\u2013500 nm semi-isolated lines<\/td><td>5\u201315 nm<\/td><td>10\u201325 nm<\/td><td>Mixed chemical + mechanical<\/td><\/tr>\n      <tr><td>1\u201310 \u00b5m metal fills<\/td><td>20\u201350 nm<\/td><td>40\u201380 nm<\/td><td>Primarily mechanical (pad deflection)<\/td><\/tr>\n      <tr><td>50\u2013100 \u00b5m bond pads<\/td><td>50-100 nm<\/td><td>80\u2013150 nm<\/td><td>Mechanical dominated<\/td><\/tr>\n    <\/tbody>\n  <\/table>\n<\/div>\n\n<h3>Dishing Measurement<\/h3>\n<p>Dishing is measured by profilometry (contact or optical) on dedicated test structures \u2014 typically isolated lines of varying width in a low-density field. The measurement is the height difference between the copper line top and the adjacent ILD surface after CMP, with a positive value indicating copper is recessed below the ILD. High-resolution optical profilometry tools (e.g., Zygo, Bruker) can resolve dishing values down to 0.5 nm, and scatterometry-based techniques are increasingly used for sub-nm measurement on advanced-node test structures.<\/p>\n\n<h2 id=\"erosion\">3. Dielectric Erosion: Pattern Density Effects &amp; Measurement<\/h2>\n\n<h3>Erosion Mechanism<\/h3>\n<p>Erosion is the thinning of the ILD material in dense metal array regions relative to isolated or low-density areas after CMP. It occurs because the polishing pad cannot distinguish between the copper lines and the narrow inter-line ILD spaces in a dense array: it contacts and removes both simultaneously during Step 2 barrier clearing. The selectivity of the Step 2 slurry (Cu:ILD selectivity) determines how much ILD is removed per unit of barrier clearing time \u2014 but even high-selectivity slurries remove some ILD in the Step 2 process, and that removal is concentrated in dense array regions where the pad contacts ILD most frequently.<\/p>\n\n<h3>Pattern Density Dependence<\/h3>\n<p>Erosion magnitude is strongly correlated with copper fill density (the fraction of a region&#8217;s area occupied by copper). Regions with 70\u201380% copper fill density show the most severe erosion because: (1) high density means the pad encounters ILD surfaces frequently per unit scan distance; (2) high density means the effective removal rate in the region is elevated due to the &#8220;loading effect,&#8221; driving more material removal per unit time than the nominal rate in open areas; and (3) dense regions tend to have the thinnest ILD inter-line spaces, which are abraded more easily by the slurry particles than wide ILD fields.<\/p>\n<p>Erosion measurement requires measurements in both dense array regions and isolated ILD fields after CMP. The erosion value is the ILD thickness difference between these two regions: Erosion = ILD<sub>isolated<\/sub> \u2013 ILD<sub>dense<\/sub>. Production targets for erosion are typically 10\u201320 nm at 45 nm and older nodes, tightening to 3\u20135 nm at 7 nm and below.<\/p>\n\n<h2 id=\"tradeoff\">4. The Dishing\u2013Erosion Tradeoff<\/h2>\n<p>Dishing and erosion are not independent defects \u2014 they are linked through several common causal factors that create fundamental tradeoffs in the optimization of copper CMP slurry and process conditions.<\/p>\n<p>The central tradeoff is between <strong>Cu:ILD selectivity<\/strong> in Step 2 and the ability to clear the barrier metal:<\/p>\n<ul>\n  <li><strong>High Cu:ILD selectivity<\/strong> (e.g., &gt;100:1): Effectively stops ILD erosion once copper and barrier are cleared, but may leave residual barrier metal in low-density regions where insufficient mechanical force is applied to remove the hard Ta or TaN. Residual barrier creates local resistivity increase and potential reliability failures.<\/li>\n  <li><strong>Low Cu:ILD selectivity<\/strong> (e.g., 10:1): Ensures complete barrier metal clearing across all pattern density regions but removes significant ILD material in dense arrays, increasing erosion substantially.<\/li>\n<\/ul>\n<p>A second tradeoff exists between BTA loading (which reduces dishing) and removal rate (which BTA also suppresses). Higher BTA loading reduces both dishing and removal rate simultaneously \u2014 so reducing dishing through BTA optimization always costs throughput. The process window for acceptable dishing with acceptable throughput is narrower at advanced nodes than at conventional nodes due to tighter dishing tolerances.<\/p>\n\n<h2 id=\"slurry-mit\">5. Slurry-Side Mitigation Strategies<\/h2>\n\n<h3>BTA Concentration Optimization<\/h3>\n<p>Increasing BTA concentration suppresses the chemical (SER-driven) contribution to dishing by strengthening the Cu-BTA passivation film on recessed copper surfaces. For every 2\u00d7 increase in BTA concentration within the effective range (0.001\u20130.1 wt%), SER typically decreases by 30\u201350%. The tradeoff is a proportional decrease in dynamic removal rate, requiring a compensating increase in H\u2082O\u2082 or mechanical parameters to maintain throughput. The optimal BTA concentration is process-specific and must be experimentally determined for each formulation and node target.<\/p>\n\n<h3>Step 2 Slurry Selectivity Engineering<\/h3>\n<p>Controlling erosion requires engineering the Cu:ILD selectivity of the Step 2 slurry. The primary formulation levers are:<\/p>\n<ul>\n  <li><strong>Abrasive type and hardness:<\/strong> Colloidal silica (lower hardness) preferentially removes the softer copper oxide and barrier metal while being gentler on the harder ILD. Switching from alumina to colloidal silica in Step 2 typically increases Cu:ILD selectivity by 2\u20135\u00d7.<\/li>\n  <li><strong>pH adjustment:<\/strong> Near-neutral to mildly alkaline pH (7\u20138) in Step 2 reduces the ILD removal rate (oxide is more stable at higher pH) while maintaining adequate copper and barrier removal rates.<\/li>\n  <li><strong>Selective surface inhibitors:<\/strong> Some advanced Step 2 formulations include ILD-selective surfactants that adsorb preferentially onto oxide surfaces, providing a degree of ILD passivation analogous to BTA&#8217;s role on copper \u2014 further increasing effective Cu:ILD selectivity.<\/li>\n<\/ul>\n\n<h3>Abrasive Particle Size and Distribution<\/h3>\n<p>Smaller abrasive particles (D50 below 80 nm) generally produce less mechanical dishing than larger particles (D50 above 150 nm) because smaller particles make contact with smaller areas of the copper trench floor during each asperity-contact event. The tradeoff is lower removal rate per unit particle contact, which must be compensated by higher particle loading or enhanced chemical activity. JEEZ&#8217;s CuS barrier slurry series uses sub-80 nm colloidal silica for this reason, achieving single-digit nanometer dishing on 100 nm features at standard Step 2 conditions.<\/p>\n\n<h2 id=\"process-mit\">6. Process-Side Mitigation Strategies<\/h2>\n\n<h3>Endpoint Detection and Over-Polish Control<\/h3>\n<p>Over-polish time \u2014 the time polished beyond the theoretical endpoint \u2014 is the single most controllable contributor to both dishing and erosion. Every 10 seconds of over-polish at a Step 2 removal rate of 100 nm\/min adds ~17 nm of additional exposure to the copper and ILD surfaces. Tight endpoint control using in-situ detection (motor current, optical reflectance, or eddy-current) combined with APC-driven run-to-run endpoint correction is the most effective process-side mitigation for both dishing and erosion.<\/p>\n<p>Practical targets for over-polish time in advanced-node Step 2 copper CMP are &lt;15 seconds \u2014 requiring endpoint detection accuracy better than \u00b15 seconds, which in turn requires clean endpoint signal discrimination (high signal-to-noise ratio) from the in-situ sensor system.<\/p>\n\n<h3>Polishing Pressure Optimization<\/h3>\n<p>Lower Step 2 polishing pressure reduces mechanical dishing by decreasing pad deflection into trench features. However, lower pressure also reduces the mechanical driving force for barrier metal removal, potentially leading to residual barrier on low-density regions. The optimal Step 2 pressure minimizes mechanical dishing while maintaining complete barrier clearing across all pattern density regions \u2014 typically 1.5\u20132.5 psi for conventional nodes, 0.7\u20131.2 psi for ELK-containing advanced nodes.<\/p>\n\n<h3>Pad Hardness Selection<\/h3>\n<p>Harder polishing pads deflect less into copper trenches, producing less mechanical dishing. The tradeoff with harder pads is higher defect density (more aggressive asperity contact) and less conformable surface contact on wafers with initial topographic variation. In practice, a two-layer pad stack \u2014 a hard backing layer (e.g., IC1000) under a softer polishing surface layer (e.g., SUBA) \u2014 offers a compromise that delivers hard-pad dishing performance with soft-pad defect levels.<\/p>\n\n<h2 id=\"design-mit\">7. Design-Side Mitigation: CMP-Aware Design<\/h2>\n<p>The most powerful long-term mitigation for dishing and erosion is design-level copper density control \u2014 ensuring that the circuit layout presents a sufficiently uniform copper density to the CMP process that pattern-density-dependent dishing and erosion effects are minimized before polishing begins.<\/p>\n\n<h3>Copper Fill Metal Insertion<\/h3>\n<p>Fill metal (also called &#8220;dummy metal&#8221; or &#8220;floating fill&#8221;) consists of electrically disconnected copper structures inserted into low-density regions of the layout to bring local copper density within a specified range (typically 30\u201370%) across all regions of the chip. Fill metal insertion is governed by design rules that specify minimum and maximum local density targets, fill shape constraints (to minimize capacitance coupling), and exclusion zones around critical timing paths.<\/p>\n<p>Modern EDA tools (from Synopsys, Cadence, and others) include CMP-aware fill insertion algorithms that optimize fill density distributions to minimize predicted dishing and erosion based on calibrated CMP simulation models. JEEZ&#8217;s application engineering team can assist customers in calibrating CMP simulation models to specific slurry formulations and process conditions for accurate fill insertion optimization.<\/p>\n\n<h3>CMP Simulation in Sign-Off<\/h3>\n<p>CMP simulation tools (e.g., Mentor CMP Predictor, Cadence Voltus CMP) use physics-based or data-driven models to predict dishing and erosion at every location on the chip layout based on local copper density and feature geometry. These predictions are used to: identify hotspots that exceed dishing\/erosion tolerance before tape-out, guide fill insertion optimization, and define which circuit paths need resistance margin adjustment in timing sign-off to account for CMP-induced resistance increase.<\/p>\n<p>As of July 2026, CMP simulation accuracy at 7 nm and below has improved to \u00b12 nm dishing prediction error on calibrated test structures, making simulation-driven design sign-off a viable replacement for iterative physical silicon test iterations in most cases.<\/p>\n\n<hr class=\"jz-hr\">\n\n<h2 id=\"faq\">8. Frequently Asked Questions<\/h2>\n<div class=\"jz-faq\">\n  <div class=\"jz-faq-item\">\n    <p class=\"jz-faq-q\">How is copper dishing measured in production?<\/p>\n    <p class=\"jz-faq-a\">Dishing is most commonly measured using optical profilometry on dedicated test structures \u2014 typically isolated copper lines of varying width in a low-density matrix. Contact stylus profilometry is also used for sub-nm resolution measurements. In production, scatterometry (optical CD measurement) is increasingly used for non-contact dishing estimation on patterned wafers. Ellipsometry measures ILD thickness but not copper step height directly; cross-sectional TEM is used for reference calibration of optical measurement tools.<\/p>\n  <\/div>\n  <div class=\"jz-faq-item\">\n    <p class=\"jz-faq-q\">What is the difference between dishing and erosion \u2014 can&#8217;t I just measure &#8220;topography&#8221;?<\/p>\n    <p class=\"jz-faq-a\">Dishing and erosion are distinct defects with different root causes and different effects. Dishing measures the copper surface recession relative to the adjacent ILD \u2014 it affects copper line cross-section and resistance. Erosion measures the ILD thickness reduction in dense metal arrays relative to isolated ILD regions \u2014 it affects dielectric isolation, capacitance, and planarity for subsequent layers. &#8220;Topography&#8221; encompasses both but doesn&#8217;t differentiate their independent contributions. Separating the two requires measurements on dedicated structures with known geometry: isolated lines (for dishing) and dense arrays in a measured field (for erosion).<\/p>\n  <\/div>\n  <div class=\"jz-faq-item\">\n    <p class=\"jz-faq-q\">If I increase BTA to reduce dishing, do I need to also increase H\u2082O\u2082?<\/p>\n    <p class=\"jz-faq-a\">Yes, generally. Higher BTA loading strengthens the Cu-BTA passivation film, which suppresses both static etch rate (good for dishing) and dynamic removal rate (bad for throughput). To maintain the target dynamic removal rate with higher BTA, you typically need to increase oxidizer concentration to provide more thermodynamic driving force for the BTA film disruption at pad-asperity contact points. However, higher H\u2082O\u2082 increases oxidizing power and can partially offset the SER reduction from BTA \u2014 so the final formulation must be re-optimized as a pair, not individually tuned.<\/p>\n  <\/div>\n  <div class=\"jz-faq-item\">\n    <p class=\"jz-faq-q\">How much over-polish time is typically acceptable in Step 2?<\/p>\n    <p class=\"jz-faq-a\">This depends strongly on the technology node and feature geometry. At 45 nm and above, 30\u201360 seconds of over-polish after barrier metal endpoint detection is common practice, producing acceptable dishing and erosion for that node&#8217;s tolerance budget. At 7 nm and below, the tolerance budget is so tight that over-polish time must be reduced to &lt;15 seconds, requiring in-situ endpoint detection with very high signal-to-noise ratio and run-to-run APC control that adjusts polishing time based on the previous wafer&#8217;s measured endpoint time.<\/p>\n  <\/div>\n<\/div>\n\n<div class=\"jz-related\">\n  <h3>Related Articles in This Series<\/h3>\n  <ul>\n    <li><a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/Copper-CMP-Removal-Rate-Preston-Equation-Key-Variables-Practical-Optimization\/\" target=\"_blank\" rel=\"noopener noreferrer\">Copper CMP Removal Rate: Preston Equation, Key Variables &amp; Practical Optimization<\/a><\/li>\n    <li><a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/Two-Step-Copper-CMP-Bulk-Cu-vs-Barrier-Slurry-Chemistry-Selectivity-Endpoint-Detection\/\" target=\"_blank\" rel=\"noopener noreferrer\">Two-Step Copper CMP: Bulk Cu vs. Barrier Slurry \u2014 Chemistry, Selectivity &amp; Endpoint Detection<\/a><\/li>\n    <li><a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/How-to-Select-a-Copper-CMP-Slurry-Specifications-Checklist-Supplier-Evaluation-Guide\/\" target=\"_blank\" rel=\"noopener noreferrer\">How to Select a Copper CMP Slurry: Specifications Checklist &amp; Supplier Evaluation Guide<\/a><\/li>\n    <li><a href=\"https:\/\/jeez-semicon.com\/ja\/blog\/Copper-CMP-Slurry-Complete-Guide-Chemistry-Process-Optimization-Advanced-Node-Applications\/\" target=\"_blank\" rel=\"noopener noreferrer\">Copper CMP Slurry: Complete Guide (Pillar)<\/a><\/li>\n  <\/ul>\n<\/div>\n\n<div class=\"jz-cta\">\n  <h2>Dishing or Erosion Out of Spec in Your Copper CMP Process?<\/h2>\n  <p>Jizhi Electronic Technology Co., Ltd. (JEEZ) provides targeted process support \u2014 from slurry BTA\/selectivity optimization to endpoint and APC consulting \u2014 for copper CMP integration teams dealing with dishing and erosion challenges at any technology node.<\/p>\n  <a href=\"https:\/\/jeez-semicon.com\/ja\/contact\/\" target=\"_blank\" rel=\"noopener noreferrer\" class=\"jz-cta-btn\">Contact JEEZ Application Engineering \u2192<\/a>\n<\/div>\n\n<\/div>\n\n<script type=\"application\/ld+json\">\n{\"@context\":\"https:\/\/schema.org\",\"@type\":\"FAQPage\",\"mainEntity\":[{\"@type\":\"Question\",\"name\":\"How is copper dishing measured in production?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"Dishing is measured using optical or contact stylus profilometry on isolated copper line test structures. Scatterometry is used for non-contact production monitoring. Cross-sectional TEM is used for calibration reference. Dishing = height difference between copper line top and adjacent ILD surface after CMP.\"}},{\"@type\":\"Question\",\"name\":\"What is the difference between copper dishing and dielectric erosion?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"Dishing measures copper surface recession relative to adjacent ILD \u2014 affecting copper cross-section and resistance. Erosion measures ILD thinning in dense metal arrays relative to isolated ILD regions \u2014 affecting dielectric isolation and planarity for subsequent layers. They require different test structures and have different root causes.\"}},{\"@type\":\"Question\",\"name\":\"If I increase BTA to reduce dishing, must I also increase H\u2082O\u2082?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"Yes, generally. Higher BTA suppresses both SER (good) and dynamic removal rate (throughput loss). To maintain removal rate, H\u2082O\u2082 must be increased to provide more driving force for BTA film disruption. BTA and H\u2082O\u2082 concentrations must be co-optimized as a pair, not independently adjusted.\"}},{\"@type\":\"Question\",\"name\":\"How much over-polish time is acceptable in copper CMP Step 2?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"At 45 nm and above, 30-60 seconds of over-polish after barrier endpoint is typical. At 7 nm and below, tolerance tightens to under 15 seconds, requiring high-SNR in-situ endpoint detection and run-to-run APC control of polishing time.\"}}]}\n<\/script>","protected":false},"excerpt":{"rendered":"<p>\ud83d\udcda Part of the Copper CMP Slurry knowledge series. For the complete process overview, see the Copper CMP Slurry: Complete Guide. Dishing and erosion are the two defining topographic defects  &#8230;<\/p>","protected":false},"author":1,"featured_media":2546,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[9,59],"tags":[],"class_list":["post-2544","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-blog","category-industry"],"acf":[],"_links":{"self":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts\/2544","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/comments?post=2544"}],"version-history":[{"count":2,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts\/2544\/revisions"}],"predecessor-version":[{"id":2547,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/posts\/2544\/revisions\/2547"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/media\/2546"}],"wp:attachment":[{"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/media?parent=2544"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/categories?post=2544"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/jeez-semicon.com\/ja\/wp-json\/wp\/v2\/tags?post=2544"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}