CMP Materials FAQ: 20 Common Questions Answered

CMP slurry is an aqueous colloidal suspension engineered from several functional ingredient classes, each serving a specific role in the material removal process:

• Abrasive particles — the mechanical cutting agents. The three main types are ceria (CeO₂) for oxide and STI applications, colloidal silica (SiO₂) for copper, barrier, cobalt, and dielectric polishing, and alumina (Al₂O₃) for tungsten and hard substrate applications. Typical size range: 20–150 nm. Typical concentration: 0.5–8 wt%.
• Chemical agents — react with the wafer surface to form a softer, more removable layer. These include oxidizers (H₂O₂ for Cu and W CMP), pH adjusters (KOH, HNO₃, citric acid), and complexants (glycine, citric acid) that dissolve and carry away removed material.
• Corrosion inhibitors — protect metal surfaces from over-etch between abrasive contact events. BTA (benzotriazole) is the most widely used inhibitor for copper CMP; azole derivatives are used for cobalt and other transition metals.
• Surfactants and dispersants — maintain colloidal stability of the abrasive particles and promote uniform slurry distribution at the pad–wafer interface.
• DI water — the carrier medium; must be of semiconductor-grade purity (<18 MΩ·cm resistivity) to avoid ionic contamination of the slurry.

The exact formulation varies substantially by application — a copper CMP slurry and an STI oxide slurry may share only the water as a common ingredient, with completely different abrasive types, pH ranges, and functional chemistry.

For a comprehensive breakdown, see our full guide on CMP Slurry Types, Applications & Selection.

CMP (Chemical Mechanical Planarization) and dry etching (plasma etch, RIE, ALE) are both material removal processes used in semiconductor manufacturing, but they serve fundamentally different purposes and work through different physical mechanisms:

In the semiconductor process flow, CMP and dry etching are complementary: dry etching creates the topographic features (trenches, vias, gate patterns), and CMP subsequently planarizes the deposited fill material back to a flat surface for the next lithographic layer. Neither process can replace the other — they address fundamentally different challenges in device fabrication.

CMP stands for Chemical Mechanical Planarization (also written as Chemical Mechanical Polishing, though planarization is the technically preferred term in semiconductor manufacturing contexts). The name describes the dual nature of the process: chemical refers to the reactive chemistry of the slurry that softens or modifies the wafer surface, and mechanical refers to the physical abrasive action of particles and the polishing pad against the wafer. The combination of both mechanisms — working simultaneously — is what gives CMP its unique ability to achieve global flatness while maintaining high selectivity between different film materials. The process was first introduced into commercial semiconductor manufacturing by IBM in the late 1980s for oxide planarization, and it has since become one of the most ubiquitous process steps in wafer fabrication, used across FEOL, MOL, and BEOL process sequences at every major logic and memory node.

Selecting a CMP slurry starts with clearly defining your process specification envelope — the set of performance requirements your process must meet. The key parameters to specify before beginning slurry evaluation are:

• Target film and stop layer: What is being removed, and what must be preserved? (e.g., “remove Cu overburden, stop on TaN barrier”)
• Required MRR: What removal rate is needed to meet your cycle time budget?
• Required selectivity: What is the minimum acceptable ratio of target film removal rate to stop-layer removal rate?
• WIWNU budget: What within-wafer uniformity (typically expressed as % 1σ) must the process achieve?
• Defect budget: What is the maximum acceptable scratch count and particle density post-CMP?
• Metal contamination limit: What is the maximum acceptable surface metal concentration (particularly relevant for FEOL applications)?

With these requirements defined, you can screen candidate slurries by abrasive type (ceria for STI/oxide, colloidal silica for Cu/barrier/Co, alumina for W), then evaluate finalists on blanket wafers followed by patterned wafer testing. Our detailed seven-step qualification framework is covered in the CMP Slurry Types, Applications & Selection Guide.

CMP scratches are caused by mechanical contact events where a hard particle or debris creates a groove in the wafer surface. The most common root causes in production are:

• Oversized or agglomerated abrasive particles in the slurry (the most frequent cause)
• Diamond particles shed from a worn conditioner disc
• Pad debris or hard particles embedded in the pad surface
• Dried slurry fragments from the delivery system or dispensing nozzle
• Slurry starvation causing dry-friction contact events

The single most cost-effective countermeasure is point-of-use (POU) filtration at 0.1–0.2 µm, which prevents oversized particles from reaching the pad–wafer interface regardless of their origin. Additional measures include: regular conditioner disc inspection and proactive replacement, slurry line flush schedules, DLS particle size testing on incoming lots, and monitoring platen friction current for anomalous spikes that indicate dry-contact events.

For a complete root cause and corrective action reference, see our guide on CMP Process Defects: Causes, Types & Solutions.

Ceria (cerium oxide, CeO₂) is a rare earth metal oxide abrasive used as the active particle in slurries for Shallow Trench Isolation (STI) and oxide planarization CMP. It is preferred over silica and alumina for these applications because of the chemical tooth effect — a surface-chemical reaction mechanism in which cerium atoms at the CeO₂ surface form covalent Ce–O–Si bonds with the SiO₂ wafer surface, providing a chemical removal contribution on top of mechanical abrasion.

This mechanism gives ceria two key advantages for STI: first, it achieves dramatically higher SiO₂ removal rates per unit abrasive loading compared to silica; second, it naturally selects for SiO₂ over Si₃N₄ — because the Ce–O–Si reaction is specific to silicon dioxide chemistry and does not occur to the same extent with Si₃N₄. This selectivity (up to 100:1 or more under optimized conditions) allows the STI CMP process to remove the oxide fill while preserving the Si₃N₄ hard mask, which defines the remaining oxide thickness and thus the STI trench depth uniformity.

For a full comparison of ceria vs. silica vs. alumina, see our article on CMP Abrasives: Ceria vs. Silica vs. Alumina.

CMP slurry shelf life varies significantly by formulation type:

• Ceria and silica oxide slurries: Typically 12–18 months from manufacture at 15–25°C
• Copper slurry with premixed H₂O₂: Only 3–6 months due to oxidizer decomposition — many fabs use H₂O₂-free base slurry with POU oxidizer addition to extend base slurry life to 12–18 months
• Tungsten slurries: 6–12 months depending on oxidizer type
• Cobalt slurries: 6–12 months at ≤20°C

Shelf life management requires labeling all containers with receipt date and calculated expiry, enforcing FIFO stock rotation, and performing re-qualification testing (PSD, pH, reference wafer MRR) on any lot that has reached its expiry date before use. Slurry stored above its specified maximum temperature has reduced effective shelf life proportionally. See our comprehensive storage and handling guide at CMP Slurry Storage, Handling & Safety.

Yes, slurry reclaim is practiced at some fabs as a cost-reduction measure. Slurry reclaim systems use ultrafiltration membranes or centrifugal separation to remove used abrasive particles, reaction by-products (dissolved metal ions, organic fragments), and pad debris from the spent slurry stream. The cleaned filtrate can be used as dilution water or, in some systems, the recovered abrasive particles are returned to the slurry preparation system after treatment.

However, reclaim is not universally recommended. Recirculated slurry always contains some level of accumulated metal ion contamination, modified particle surface chemistry, and degraded chemical additive concentration — all of which can increase defect density and reduce process stability compared to once-through delivery. Most leading-edge logic fabs use once-through slurry delivery for their most critical process steps. Slurry reclaim is more commonly practiced at mature-node fabs, memory fabs for less-critical CMP applications, and in cost-sensitive manufacturing environments where the reclaim infrastructure investment is justified by volume savings.

CMP pad conditioning is the process of periodically or continuously refreshing the pad surface using a diamond-embedded disc to restore the micro-textured asperity landscape that is essential for effective polishing. Without conditioning, the pad surface is progressively smoothed and loaded with polishing debris — a process called pad glazing — which reduces the real contact area between pad and wafer and causes MRR to decline by 40–60% within 20–30 wafer passes.

The diamond conditioner disc is pressed against the rotating pad with a controlled downforce (typically 5–60 N) while sweeping across the pad radius. The diamond grits micro-cut the polyurethane pad surface, removing the glazed outer layer and re-exposing fresh pad material with active asperities and open pores that can hold and transport slurry to the polishing interface.

Two conditioning modes are used: in-situ conditioning (conditioner runs simultaneously with wafer polishing, maintaining stable MRR at the cost of faster pad wear) and ex-situ conditioning (pad is conditioned between wafer runs, reducing pad wear but allowing some within-run MRR drift). Most oxide and W CMP applications use in-situ conditioning; soft pads in copper buff applications typically use ex-situ conditioning.

The full technical treatment is in our guide on CMP Pad Conditioners & the Conditioning Process.

The fundamental difference is in mechanical stiffness and how that stiffness affects the pad–wafer contact mechanics:

• Hard pads (IC1000-type, Shore D 50–65): Made from closed-cell polyurethane foam with high stiffness. Because they resist local deformation, they maintain contact preferentially with the highest topographic points on the wafer surface, creating higher local pressure at elevated regions and lower pressure at recessed regions. This makes them excellent at planarizing step height — removing high points faster than low points. The tradeoff is moderate defect performance and higher scratch risk vs. soft pads.
• Soft pads (Politex-type, Shore A 15–30): Made from non-woven polyester felt or open-cell foam. Their low modulus allows them to conform closely to the local wafer topography, distributing contact pressure more uniformly across features at different heights. This eliminates the preferential high-point removal that drives planarization, making soft pads poor planarizers — but it also dramatically reduces scratch defects and surface roughness, making them excellent for final buff polishing steps where defect minimization is the priority.

Most production CMP tools use a stacked composite pad (hard top pad + compressible sub-pad) that combines the planarization efficiency of a hard pad with improved edge uniformity from the compliant sub-pad. For the complete comparison, see our guide on CMP Polishing Pads: Technologies & Comparison.

Copper dishing is the concave depression that forms in copper features (particularly wide damascene lines and pads) after CMP, where the copper surface is recessed below the surrounding dielectric surface. It results from the pad conforming into wide copper features during over-polish and mechanically removing the BTA passivation film from the copper center, allowing the chemical oxidizer to continue attacking the unprotected copper surface.

Prevention strategies, in order of effectiveness:

• Tight endpoint control: Implement in-situ optical reflectance or eddy-current endpoint detection and stop polishing immediately upon endpoint signal. The single largest source of excessive dishing is uncontrolled over-polish time.
• BTA concentration optimization: Ensure the inhibitor concentration in the Step 2 slurry is sufficient to maintain passivation film integrity throughout the barrier clearing step. Test BTA concentration on incoming lots.
• Reduce oxidizer concentration: Lower H₂O₂ concentration reduces the chemical etch rate on unprotected copper, slowing dishing progression during any over-polish time that does occur.
• Use harder pad for Step 2: A harder pad maintains a more planar contact surface and conforms less deeply into wide features, reducing the mechanical removal of passivation film from the feature center.

See our complete defect guide at CMP Process Defects: Causes, Types & Solutions.

The number of CMP steps per wafer scales dramatically with process node complexity:

The rapid increase in CMP step count at advanced nodes is driven by the increasing 3D complexity of device architecture, the growing number of metal layers in BEOL interconnect, and the introduction of entirely new CMP steps for novel materials and structures (nanosheet reveal, cobalt and ruthenium contact CMP, hybrid bonding surface preparation) that simply did not exist at mature nodes.

Within-wafer non-uniformity (WIWNU) is the variation in material removal rate or remaining film thickness across a single 300 mm wafer after CMP. It is typically expressed as the standard deviation (1σ) of a set of thickness measurements taken at multiple sites across the wafer, divided by the mean thickness — and expressed as a percentage. For example, a WIWNU of 2% 1σ means the standard deviation of post-CMP thickness across the wafer is 2% of the mean thickness.

WIWNU arises from several sources: non-uniform pressure distribution between the carrier head and the pad (addressed by multi-zone carrier pressure control), radial variations in pad conditioning intensity, slurry flow distribution effects, and the wafer’s own bow and warp affecting local contact pressure. Best-in-class WIWNU for advanced production processes is ±1–2% 1σ. Values above 3–4% begin to consume significant process budget and can contribute to yield loss through over-polish of thin-film regions while leaving residuals at thick-film regions.

CMP endpoint detection is the real-time monitoring method used to determine when the polishing step has reached the target removal depth, triggering the tool to stop or transition to the next step. Without endpoint detection, process control relies on timed polishing — which accumulates MRR drift error over a run and leads to over-polish on some wafers and under-polish on others. The main endpoint detection methods used in production are:

• In-situ reflectometry (ISRM): A laser or broadband optical beam passes through a window in the platen and reflects off the wafer surface. Changes in reflectance indicate film thickness transitions as different materials are exposed. Most effective for processes with clear optical contrast change at endpoint (copper clearing, poly reveal).
• Eddy-current (EC) sensing: An electromagnetic sensor in the platen measures the electrical conductance of the metal film on the wafer. As metal is removed, conductance decreases — providing a direct real-time measurement of metal thickness. Used for copper, tungsten, and other metal CMP applications.
• Friction current (motor current) monitoring: The friction between pad and wafer changes when the surface material changes (e.g., when copper overburden is removed and the barrier metal is exposed). The resulting change in platen motor current provides a secondary endpoint indicator, though it is less precise than optical or eddy-current methods for advanced applications.
• Real-time film thickness measurement: Advanced tools combine multiple endpoint signals with process models to provide wafer-level thickness uniformity feedback, enabling profile correction during polishing by adjusting zone pressures on the carrier head.

CMP plays a central role in 3D-IC integration at multiple process levels. The most demanding application is the preparation of bonding surfaces for hybrid bonding — a direct wafer-to-wafer or die-to-wafer bonding technique where SiO₂ (or SiCN) dielectric surfaces and Cu metal pads bond directly without any adhesive. This bond forms through surface chemistry activated by thermal annealing, and its quality depends entirely on the surface quality of both bonding partners.

The CMP requirements for hybrid bonding surface preparation are the most stringent in semiconductor manufacturing:

• Surface roughness Ra < 0.3 nm (vs. <1–2 nm for conventional BEOL CMP)
• Cu dishing < 5 nm (vs. <20–30 nm for conventional Cu CMP)
• Surface particle count < 10 per wafer above 50 nm
• Metal contamination < 1×10¹⁰ atoms/cm²

Achieving these specifications requires ultra-pure sub-30 nm colloidal silica slurry at very low concentration (<2 wt%), ultra-soft polishing pads at downforce below 1 psi, and extended multi-step post-CMP cleaning. CMP is also used for TSV (Through-Silicon Via) reveal, RDL planarization, and wafer thinning in 3D-IC packages. See our guide on CMP Materials for Advanced Nodes.

CMP can affect device reliability in several ways — both through immediate defects that cause functional failures at test, and through subtle damage mechanisms that cause degradation under field operating conditions:

• Metal contamination: Cu, Fe, or Co ions from CMP slurry that are not removed by post-CMP clean can diffuse into the active device region during subsequent thermal processing, creating mid-gap trap states, increasing junction leakage, and reducing minority carrier lifetime. Even sub-ppb surface contamination levels can cause measurable transistor performance degradation.
• Subsurface scratch damage: Micro-scratches below the optical detection threshold can create stress concentration sites in metal lines that become preferential electromigration failure sites under current-carrying conditions at device operating temperatures.
• Dishing and erosion: Copper dishing increases the effective resistance of wide interconnect lines. At advanced nodes where resistance-capacitance (RC) delay is a primary performance limiter, even 10–15 nm of excess dishing can produce measurable performance impact.
• Dielectric damage: Subsurface mechanical damage to ultra-low-k dielectric films from high-downforce CMP can increase dielectric constant and reduce breakdown voltage, degrading the insulating capability of the interconnect stack and reducing time-dependent dielectric breakdown (TDDB) reliability margins.

Copper and tungsten CMP are both metal removal processes but differ fundamentally in chemistry, process structure, and defect risk profile:

Qualifying a new CMP slurry supplier at a production fab is a structured process that typically takes 6–24 months depending on application complexity. The key stages are:

• Technical pre-screening: Review the supplier’s product data sheets and qualification data from comparable process nodes and tool platforms. Request COA data from three consecutive production lots.
• Blanket wafer evaluation: Evaluate MRR, WIWNU, and surface roughness (AFM) on blanket films across a process parameter DOE. Confirm that the slurry meets specification targets.
• Patterned wafer evaluation: Run on standard qualification patterned wafers (SEMATECH masks or equivalent) to measure dishing, erosion, and residuals vs. pattern density. Compare to incumbent slurry data.
• Defect and contamination characterization: Full-wafer inspection (KLA or Hitachi) for particle defects and scratches; VPD-ICPMS for trace metal surface contamination.
• Downstream yield correlation: Track polished wafers through subsequent process steps and electrical test to confirm no downstream yield impact from the new slurry.
• Supply chain audit: Review supplier QMS, manufacturing site, raw material sourcing, and supply continuity commitments.

JEEZ provides a complete qualification support package for all our products — including reference data, COA documentation, and dedicated application engineering support throughout the process. See our supplier comparison article: Top CMP Materials Suppliers: 2026 Comparison.

Silicon carbide (SiC) is one of the hardest substrate materials in semiconductor manufacturing (Mohs hardness 9.5), making it extremely challenging to polish compared to silicon (Mohs 7) or gallium arsenide (Mohs 4.5). CMP of SiC requires abrasives and process conditions specially adapted to this hardness:

• Colloidal silica at alkaline pH (10–12): The most widely used approach for final SiC CMP. At high pH, the silica abrasive combined with chemical oxidation of the SiC surface (forming a softer SiO₂ layer) enables polishing at practical removal rates. Achieves <0.1 nm Ra on the Si face for epitaxial quality substrates.
• Alumina at acidic conditions: Fumed or calcined alumina provides higher mechanical removal rate than silica on the harder SiC surface. Used for pre-polish (rough CMP) to reduce substrate bow and scratch damage from wire sawing before the final silica polish.
• Nano-diamond slurry: For polishing the extremely hard C-face of SiC or for removing subsurface damage from wire-saw cutting; achieves high MRR but requires careful defect control to avoid deep scratches.
• Oxidizing chemistry assistance: KMnO₄, H₂O₂, or electrochemical oxidation can assist SiC CMP by converting the hard SiC surface to a softer oxide layer, increasing effective MRR even with softer abrasives.

JEEZ offers specialized slurry formulations for SiC substrate CMP applications. Contact our technical team for a recommendation tailored to your substrate grade, wafer diameter, and surface quality requirements.

Cobalt has replaced tungsten for contacts and local interconnects at 7 nm and below in leading-edge logic, and it presents a substantially different — and more challenging — CMP environment compared to copper:

• Different corrosion inhibitor requirement: BTA (the standard copper inhibitor) is less effective on cobalt surfaces. Cobalt CMP requires cobalt-specific inhibitors (imidazole derivatives, TTZ, proprietary azoles) that form stable passivation films on Co surfaces at the relevant process pH.
• Galvanic corrosion risk at Co/TiN interface: The electrochemical potential difference between cobalt and TiN barrier metal drives anodic dissolution of cobalt at contact perimeters in the presence of an oxidizing slurry. This galvanic corrosion mechanism — which does not occur in the same way for copper — creates pitting defects at contact edges that degrade contact resistance and reliability. Slurry chemistry must be carefully tuned to suppress this specific interaction.
• Cobalt contamination toxicity: Dissolved Co²⁺/Co³⁺ ions leached into the slurry are classified as potential carcinogens (IARC Group 2A) and are subject to stricter worker exposure and environmental discharge limits than copper ions. Post-CMP clean must effectively remove Co ions from the wafer surface, and Co-containing waste streams require dedicated treatment.
• Lower hardness: Cobalt (Vickers ~1,000 MPa) is softer than tungsten (~3,430 MPa), meaning CMP conditions suitable for W will cause excessive dishing and defects on Co. Lower downforce, finer abrasive, and more aggressive corrosion inhibition are all required.

For the full technical treatment including slurry formulation design principles, see our guide on CMP Materials for Advanced Nodes (Below 14 nm).