Final Silicon Polishing with Colloidal Silica: Achieving Sub-Ångström Surface Roughness
A comprehensive technical guide to final silicon polish (FSP) with colloidal silica CMP slurry—covering surface quality specifications, slurry design principles, process parameter optimization, multi-step polish sequences, and post-CMP clean compatibility for prime and epi-ready wafers.
Among all chemical mechanical planarization steps performed in semiconductor manufacturing, silicon wafer final polishing stands apart in the severity of its surface quality requirements. While oxide CMP and STI planarization tolerate surface roughness on the order of 0.5–1.0 nm RMS, final silicon polish must achieve roughness below 0.1 nm (1 Ångström) RMS—an order of magnitude tighter—while simultaneously delivering light-point defect (LPD) counts below 50 particles at sub-100 nm detection thresholds, nanotopography within 10 nm peak-to-valley across 10×10 mm sites, and surface metal contamination below 5×10¹⁰ atoms/cm² for critical elements.
Colloidal silica is the only commercially available abrasive capable of meeting these specifications in production. But selecting the right colloidal silica grade and optimizing the process parameters requires a detailed understanding of how each slurry variable connects to each surface quality outcome—the subject of this guide.
1. Why Final Silicon Polish Is the Most Demanding CMP Step
Final silicon polish (FSP) is the last mechanical processing step in silicon wafer manufacturing before the wafer is shipped to device fabrication. Every defect introduced at FSP—whether a surface scratch, a sub-surface damage layer, a haze-causing roughness contribution, or a metal contamination residue—propagates directly into the device fab’s incoming wafer quality and cannot be corrected downstream. There is no subsequent processing step to mask or repair FSP-induced defects.
The increasingly stringent FSP requirements are driven by advanced device technology requirements. At 2 nm logic nodes, the gate dielectric thickness is below 1 nm (effective oxide thickness), meaning the electronic quality of the Si-SiO₂ interface is governed by sub-angstrom features of the underlying silicon surface. For epitaxial applications (GaN-on-Si, SiGe layers for strained channels), the surface must be essentially free of crystallographic defects—pits, hillocks, or surface steps—that would propagate as threading dislocations through the epitaxial film.
Additionally, wafer-level nanotopography—slow, long-wavelength surface height variations across millimeter to centimeter spatial scales—directly impacts gate oxide thickness uniformity and local planarity for contact alignment in leading-edge lithography steps. Nanotopography is introduced or inherited from the FSP process and cannot be fully corrected by downstream chemical amplification.
2. Surface Quality Specifications for Prime and Epi-Ready Wafers
The surface quality targets for final silicon polish are defined by multiple industry specifications, most commonly SEMI M1 (silicon prime wafer) and customer-specific specifications for epitaxial and SOI substrates:
- Surface roughness (RMS): <0.10 nm over 1×1 µm² AFM scan; <0.07 nm for leading-edge epitaxial substrates
- LPD count: <50 particles at >0.09 µm detection threshold (KLA SP5 or equivalent); <20 LPD at >0.12 µm for Class 1 applications
- Nanotopography (SFQR): <10 nm peak-to-valley over 10×10 mm site; <25 nm global (GBIR) across the full 300 mm wafer
- Haze: <0.05 ppm (normalized to SiO₂ standard) measured by laser scatterometry
- Surface metal contamination: Fe <5×10¹⁰ atoms/cm²; Cu <1×10¹⁰ atoms/cm²; Ni <5×10¹⁰ atoms/cm²
- Oxygen precipitates: Zero bulk microdefects (BMDs) in the top 10 µm (FEOL epitaxial grade)
Haze vs. roughness: Haze (measured by laser scatterometry at low incidence angles) and surface roughness (measured by AFM at nanometer spatial scales) capture different aspects of the surface quality but are strongly correlated. High roughness at the 1–10 nm spatial frequency range produces elevated haze. Final polish slurry selection must target both metrics simultaneously.
3. Slurry Design for Sub-Ångström Surface Quality
Achieving sub-ångström surface roughness with colloidal silica requires slurry design that optimizes four interdependent variables simultaneously: particle size, pH, solids content, and additive chemistry.
3.1 Particle Size: The Primary Roughness Lever
For final silicon polish, the D50 must be in the range of 20–40 nm. At this size, the individual abrasive–substrate contact area is small enough that each removal event removes only a few atomic layers of silicon, producing an atomically smooth surface. Larger particles (D50 >60 nm) produce deeper individual contact events that translate to higher roughness contributions—each particle leaves a slightly deeper “divot” in the hydrated surface layer, increasing the RMS roughness of the final polished surface.
The D90 must be tightly controlled: D90/D50 ratio ≤2.0 ensures that the 10% of particles above the median are not significantly larger than the median, preventing the “tail” particles from contributing disproportionately to roughness and LPD. The large particle count (LPC) at >0.5 µm must be below 300 particles/mL (ideally <100) to meet LPD specifications below 50 at >0.09 µm detection.
3.2 pH: Balancing MRR, Roughness, and Haze
Final silicon polish slurries typically operate at pH 10.5–12.0. The optimal pH represents a careful trade-off: higher pH accelerates Si surface hydration and increases MRR, but also increases the chemical etching rate of the silicon surface, which can increase surface haze if the chemical removal component outpaces the mechanical smoothing. Most final polish processes use pH 10.5–11.5 for prime wafer applications, with higher pH (11.0–12.0) reserved for epi-substrate preparation where higher Si removal is needed to eliminate sub-surface damage from preceding rough polish steps.
3.3 Additive Chemistry
Final silicon polish slurries frequently include small concentrations of surface-active additives that modify the silicon surface during polishing. Key additive types include:
- Quaternary ammonium compounds (QAC): Such as TMAH or choline, enhance silicon dissolution rate at alkaline pH by complexing Si dissolution products, preventing re-deposition on the surface
- Non-ionic surfactants: Reduce haze by modifying the surface wetting characteristics after polishing, promoting more uniform re-passivation of the silicon surface with oxide
- Chelating agents: Such as EDTA or citric acid, sequester trace metal ions (Fe³⁺, Cu²⁺) in solution to prevent them from depositing on the polished silicon surface as metal contamination
4. Process Parameters and Pad Selection
Final silicon polish process conditions differ significantly from oxide CMP conditions—lower pressures, softer pads, and gentler conditioning are the norm:
| Параметр | Typical Oxide CMP | Final Silicon Polish | Reason for Difference |
|---|---|---|---|
| Down-force (pressure) | 2–4 psi | 0.5–2.0 psi | Lower stress to prevent sub-surface damage |
| Table speed | 60–120 rpm | 30–80 rpm | Lower velocity reduces shear-induced roughness |
| Pad type | IC1000 (hard) | Suba or Politex (soft) | Soft pad conforms to surface, smooths micro-roughness |
| Conditioner | Diamond dresser (aggressive) | Soft conditioner or brush | Minimize pad debris; avoid hard conditioning particles |
| Slurry flow rate | 150–300 mL/min | 100–200 mL/min | Less slurry needed at lower MRR; reduces waste |
| Polish time | 60–180 s | 120–600 s | Lower MRR requires longer time; achieves gradual roughness reduction |
Soft CMP pads (Suba series, Politex) are preferred for final silicon polish because their low elastic modulus allows them to conform to the sub-nanometer topography of the wafer surface, providing more uniform abrasive contact across the full wafer area. Hard pads (IC1000) maintain better planarity for oxide step-height reduction but do not smooth roughness as effectively at the angstrom scale.
5. Multi-Step Polish Sequences
Industrial final silicon polish is typically a multi-step process, not a single CMP step. The number and nature of steps depend on the upstream wafer condition (saw-damage depth, lapping roughness) and the final specification target:
- Step 1 — Stock removal (SR) polish: Uses a larger D50 colloidal silica (60–100 nm) or ceria-based slurry at higher pressure (2–4 psi) to rapidly remove 5–20 µm of silicon and eliminate all saw damage and sub-surface crystal defects. Surface roughness after SR polish: 0.3–1.0 nm RMS.
- Step 2 — Intermediate finish (IF) polish: Uses a medium D50 colloidal silica (40–60 nm) at moderate pressure (1.0–2.5 psi) to reduce roughness from 0.3–1.0 nm to 0.15–0.30 nm RMS while removing 0.5–2 µm of silicon.
- Step 3 — Final polish (FP): Uses fine colloidal silica (D50 = 20–35 nm) at low pressure (0.5–1.5 psi) on a soft pad to bring roughness from 0.15–0.30 nm to the final target (<0.10 nm RMS). Removes 50–200 nm of silicon. This is the step where LPD generation is most critical and slurry cleanliness specifications are most stringent.
The transition between steps typically includes a DI water rinse to prevent contamination of the subsequent step’s slurry with residues from the preceding step—particularly important when transitioning from higher-MRR slurry in Step 1 to the ultra-clean final polish slurry in Step 3.
6. Post-CMP Clean Compatibility
After final silicon polish, the wafer undergoes a post-CMP clean sequence designed to remove slurry particle residues, metallic contamination, and organic additive residues without damaging the freshly polished surface. The effectiveness of the post-CMP clean directly impacts the final LPD count and surface metal contamination—often the binding specifications for prime wafer acceptance.
Standard post-CMP clean sequences for silicon final polish include:
- Brush scrub with dilute NH₄OH/H₂O₂ (SC1-equivalent): Removes colloidal silica particle residues through a combination of mechanical scrubbing and chemical etching of the silicon surface beneath particle contact points. SC1 at 0.5–1% NH₄OH, 0.5–1% H₂O₂, 50°C for 60–120 s is a common process.
- Dilute HF rinse: Strips the native oxide grown during SC1, removing oxide-trapped metal contaminants and leaving a hydrogen-terminated silicon surface with minimal particle adhesion
- Final DI water rinse with Marangoni drying: Marangoni (IPA-assisted) drying minimizes water-mark defects on the polished surface by using IPA vapor to create a surface-tension gradient that pulls the water film off cleanly
The key compatibility requirement between the final polish slurry and the post-CMP clean is particle de-adhesion: colloidal silica particles must not form strong chemical bonds with the silicon surface during polishing that resist removal by brush scrub and SC1 chemistry. Well-formulated final polish slurries include pH adjusters and additive packages that prevent strong silica-silicon condensation bonds from forming at the particle–substrate interface.
7. Common Failure Modes and Root Causes
| Режим отказа | Симптом | Most Likely Root Cause | Корректирующие действия |
|---|---|---|---|
| High LPD count | LPD > spec at >0.09 µm after clean | LPC spike in slurry (agglomeration event); insufficient post-CMP clean; pad debris | Verify slurry pH and LPC; review dilution water quality; optimize clean chemistry |
| High surface roughness (haze) | RMS >0.10 nm; haze >0.05 ppm | D50 too large; pH too high (excessive chemical etching); polish time too short | Reduce D50; lower pH to 10.5; extend final polish step time |
| Nanotopography excursion | SFQR or GBIR out of spec | Pad thickness non-uniformity; carrier membrane pressure map issue; incoming wafer nanotopography | Pad qualification; carrier membrane inspection; review rough polish sequence |
| Scratch defects | Visible scratches on KLA review | Large particle tail in final polish slurry; pad conditioner debris; cross-contamination from SR step | Verify LPC by SPOS; add POF filter; review rinse protocol between steps |
| Metal contamination | Fe or Cu above spec by TXRF | Slurry metallic impurity; process water contamination; equipment surface contamination | Verify slurry CoA for Fe/Cu; audit process water; inspect tool surfaces |
8. JEEZ CS-20 Series for Final Silicon Polish
The JEEZ CS-20 Series is specifically engineered for final silicon polish applications requiring sub-ångström surface roughness and ultra-low LPD counts. Key specifications: D50 = 20–30 nm, D90 <60 nm, LPC <300 counts/mL at >0.5 µm by SPOS, pH 10.0–11.5 (NH₄OH or KOH adjusted, customer-specified), solids content 12.5 wt% RTU or 25 wt% concentrate.
Each lot is released with a full Certificate of Analysis including SPOS-measured LPC data. JEEZ application engineering team provides process integration guidance, dilution protocol recommendations, and technical support for qualification at customer tools.
For the complete colloidal silica technical reference, see: Colloidal Silica Slurry: The Complete Guide to CMP Applications, Properties, and Selection.
9. Frequently Asked Questions
For prime silicon wafer final polish targeting surface roughness <0.10 nm RMS and LPD <50 at >0.09 µm, use D50 = 20–30 nm. For epi-substrate preparation where slightly higher MRR is acceptable and the roughness target is <0.15 nm RMS, D50 = 30–40 nm provides a better throughput-quality balance. Do not use D50 >50 nm for final polish—the roughness and haze penalties are significant and typically exceed specification limits.
Final silicon polish intentionally uses conditions that minimize MRR to maximize surface quality: fine particles (20–30 nm D50), low pressure (0.5–1.5 psi), moderate velocity, and soft pads. The MRR under these conditions is typically 100–400 Å/min—much lower than oxide CMP (500–3,500 Å/min). The low MRR is a feature, not a bug: each removal event removes fewer atoms, producing a smoother final surface. The trade-off is longer polish times (120–600 seconds), which is acceptable for prime silicon wafer manufacturing where throughput is less constrained than in device fabrication CMP steps.
Yes, KOH-adjusted colloidal silica is used in final silicon polish, but the K⁺ contamination implications must be managed. After FSP with KOH-adjusted slurry, the post-CMP clean sequence (SC1 + dilute HF + DI rinse) must achieve K⁺ surface concentration below the incoming wafer specification—typically <1×10¹⁰ atoms/cm². If your post-CMP clean is effective, KOH-adjusted slurry is suitable. If K⁺ specifications are extremely tight (e.g., for gate-oxide-proximate FEOL process compatibility), specify NH₄OH-adjusted or TMAH-adjusted colloidal silica to eliminate K⁺ introduction entirely.
Nanotopography—slow-wavelength surface height variation at 0.2–20 mm spatial scales—is primarily inherited from upstream mechanical processing (wire sawing, lapping) and is reduced but not eliminated by the CMP polish sequence. The FSP process influences nanotopography through pad stiffness (softer pads conform to and reduce shorter-wavelength nanotopography but have less effect on longer-wavelength components), carrier head pressure uniformity, and wafer holder backpressure distribution. Tight nanotopography specifications (<8 nm SFQR over 10×10 mm) require optimization of the full polish sequence, including the intermediate polish steps, not just the final polish step.
Achieve Sub-Ångström Silicon Polish with JEEZ CS-20
Request a sample of JEEZ CS-20 Series final polish slurry for evaluation against your prime wafer LPD and roughness specifications. Our application engineering team can provide a tailored qualification protocol and process integration support.
Request Sample & Technical Support →Published by Jizhi Electronic Technology Co., Ltd. (JEEZ) · August 2026. For process-specific advice, contact our application engineering team.
