Hard vs. Soft CMP Polishing Pads: The Definitive Selection Guide

Published On: 2026年4月7日Просмотров: 214

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Jizhi Electronic Technology — Selection Guide Series

A rigorous, application-mapped guide to choosing between hard and soft CMP polishing pads — covering the fundamental physics of the trade-off, process-step-by-step recommendations, stacked pad strategy, and a practical decision framework for fab engineers.

📅 April 2026⏱ 15 min read🏭 Jizhi Electronic Technology Co., Ltd.
Hard CMP Pad Soft CMP Pad Pad Selection Guide Planarization Efficiency WIWNU Stacked Pad Shore D Hardness Cu BEOL
Process
Verified
Written by Jizhi Electronic Technology Co., Ltd. — CMP pad manufacturer supplying both hard polyurethane pads and soft subpads to wafer fabs, equipment makers, and research institutions. Selection recommendations are based on our in-house process characterization data and current April 2026 industry practice.

Every CMP process engineer eventually faces the same fundamental decision: hard pad or soft pad? The question seems deceptively simple — but it sits at the intersection of contact mechanics, surface chemistry, and wafer-scale uniformity physics. Getting it wrong can mean poor planarization (hard pad selected where soft was needed) or excessive defects and uniformity excursions (soft pad selected where hard was required).

This guide provides the definitive answer — not as a simple rule, but as a structured framework that maps pad hardness to process requirements, film type, node, and defect budget. If you want to first understand how pad hardness affects material removal at a mechanistic level, see: How CMP Polishing Pads Work. For a broader overview of pad material classes beyond just hardness, see: CMP Pad Materials: Polyurethane vs Other Options.

55–65
Shore D hardness range of production hard pads (IC1000-type)
28–45
Shore D hardness range of soft CMP pads / subpads
<1%
WIWNU (1σ) target for Cu BEOL CMP at 7 nm and below
2–3×
Planarization efficiency advantage of hard pad over soft on identical incoming topography

1. The Core Trade-off: Planarization Efficiency vs. Within-Wafer Uniformity

The hard-vs-soft pad decision is governed by a single, inescapable physical trade-off: a harder pad is better at removing topographic features, but a softer pad is better at distributing removal uniformly across the wafer. These two objectives are in direct tension, and no pad can simultaneously maximize both. Understanding why — at the mechanical level — is the foundation of informed pad selection.

Why Hard Pads Plannarize Better

A hard pad (Shore D 55–65) has a high Young’s modulus, typically 200–500 MPa. When pressed against a wafer surface with raised topographic features (hills created by underlying device structures), the rigid pad surface bridges over the valleys and concentrates contact force on the hilltops. This selective loading means that material removal preferentially occurs at the high points, progressively reducing step height and approaching global planarization. The phenomenon is analogous to a stiff ruler pressed across a bumpy surface — only the bumps touch the ruler.

Why Soft Pads Are More Uniform

A soft pad (Shore D 28–45) has a low Young’s modulus, typically 10–60 MPa. Under the same applied down-force, it deforms and conforms to the wafer surface topography rather than bridging over it. Contact force is distributed more evenly across both hills and valleys. The result is more uniform material removal — but at the cost of lower step-height reduction. Additionally, at the wafer scale, a soft pad conforms to the bow and warp of a 300 mm production wafer (commonly 20–80 µm peak-to-valley), reducing the edge-to-center pressure differential that causes non-uniform removal profiles with hard pads.

ℹ️
The Planarization Length Scale The hard-pad planarization advantage operates over a specific lateral length scale — approximately 1–10 mm — corresponding to the distance over which a hard pad can bridge across topographic features without conforming. Features smaller than this length scale are effectively “invisible” to the hard pad’s bridging mechanism and are removed uniformly regardless of their height. Features larger than the bridging length require multiple CMP cycles or alternative planarization approaches. Understanding this length scale for your specific hard pad and process conditions is essential for predicting planarization efficiency.

2. Hard Pads: Properties, Strengths, and Limitations

HARD PAD — Strengths
Shore D 55–65
  • High planarization efficiency — step-height reduction >80% in one pass typical
  • Stable, predictable removal rate over extended conditioning campaigns
  • Better selectivity between high and low features — ideal for damascene steps
  • Stiffer surface resists asperity flattening — maintains MRR over longer pad life
  • Higher Preston coefficient Kp — higher throughput per pressure unit
  • Better compatibility with high-selectivity ceria slurries for STI oxide CMP
HARD PAD — Limitations
Watch out for:
  • Higher scratch density — stiff asperities transmit more force to abrasive particles
  • Poor edge-center uniformity on bowed or warped wafers
  • Risk of low-k dielectric delamination under high shear forces
  • Higher sensitivity to pressure non-uniformity from retaining ring geometry
  • Requires more aggressive conditioning to prevent glazing — higher conditioner wear
  • Not suitable for ultra-thin films where over-polishing risk is high

Typical Hard Pad Specifications (Production Grade)

Параметр Specification Range Test Method
Shore D hardness 55–65 (±2 within lot) ASTM D2240, 5-point wafer map
Compressibility 0.5–2.5% % thickness change at 25 kPa, 60 s
Elastic recovery >70% % recovery 60 s after load removal
Mean pore diameter 20–45 µm Optical cross-section, image analysis
Pore size CV (%) <18% Standard deviation / mean × 100
Pad thickness 2.0–2.5 mm (±0.05 mm) 5-point contact gauge
Groove depth 0.5–0.8 mm Profilometer cross-section
Groove width 0.3–0.6 mm Profilometer cross-section

3. Soft Pads: Properties, Strengths, and Limitations

SOFT PAD — Strengths
Shore D 28–45
  • Superior within-wafer uniformity — conforms to wafer bow and warp
  • Low shear force on fragile films — safe for low-k dielectrics (k < 2.5)
  • Lower scratch and micro-scratch density — critical for Cu and barrier CMP
  • Excellent for final surface finishing steps requiring Ra < 0.5 nm
  • Better results on 300 mm wafers with high bow/warp from stress films
  • Forgiving to minor slurry flow variations and recipe perturbations
SOFT PAD — Limitations
Watch out for:
  • Low planarization efficiency — poor step-height reduction on rough incoming surfaces
  • Faster MRR decay as pad glazes — requires more frequent conditioning
  • Lower Tg — more susceptible to thermal softening at elevated process temperatures
  • Higher compressibility variation wafer-to-wafer in early pad life
  • Not suitable for STI, PMD, or any step requiring >50% step-height reduction
  • Sensitive to conditioning parameters — over-conditioning dramatically increases MRR

4. Head-to-Head Comparison: Every Key Metric

Метрика Hard Pad (Shore D 55–65) Soft Pad (Shore D 28–45) Winner
Planarization efficiency High — bridges topography, removes selectively from high points Low — conforms to topography, removes uniformly Hard
Within-wafer uniformity (WIWNU) Moderate — sensitive to wafer bow and retaining ring geometry High — conforms to wafer-scale shape variations Soft
Scratch defect density Higher — stiff asperities transmit higher local stress Lower — compliant asperities reduce peak contact stress Soft
Low-k film safety Risk of delamination at standard pressures Safe at standard pressures (<3 psi) Soft
Material removal rate Higher MRR at same P × V — better throughput Lower MRR — longer polishing times needed Hard
Pad lifetime (wafers/pad) 500–2,000 wafers — stiffer surface resists wear 300–1,000 wafers — softer surface glazes faster Hard
Slurry utilization Moderate — closed-cell pores provide good retention High — open-cell structure absorbs and releases slurry efficiently Soft
Conditioning sensitivity Lower — MRR change per unit conditioner force is smaller Higher — small conditioning changes cause significant MRR shifts Hard
Thermal stability Higher Tg (90–120°C) — better for high-pressure processes Lower Tg (55–80°C) — softens faster under thermal load Hard
Cost (unit price) Baseline (1.0×) Slightly lower (0.8–1.1×) — depends on formulation Похожие

5. Application-by-Application Selection Map

The following application map provides pad hardness recommendations for the most common CMP steps in advanced semiconductor manufacturing. Each recommendation is grounded in the process physics described above and reflects April 2026 fab best practice. For a broader view of how CMP pads are used across the full IC process flow, see: Semiconductor CMP Polishing Pads.

HARD PAD STI Oxide CMP
Shallow trench isolation requires aggressive step-height removal (1,000–3,000 Å of incoming oxide step). Hard pad with ceria-based slurry achieves >90% step-height reduction in a single polish step. Selectivity to Si₃N₄ stop layer is critical — hard pad helps maintain mechanical selectivity.
HARD PAD Pre-Metal Dielectric (PMD)
BPSG or USG planarization before the first metal level. High incoming topography from gate and contact structures demands hard-pad planarization efficiency. The target film is oxide — hard pads with silica or ceria slurry are the standard approach.
HARD PAD W Plug CMP
Tungsten chemical mechanical polishing removes excess W deposited in contact/via holes, stopping on the TiN/TaN barrier layer. Hard pad required for planarization and to maintain the high down-force needed for W’s moderate hardness. High selectivity to the barrier layer is critical.
SOFT PAD Cu Bulk Removal (BEOL Step 1)
The first CMP step in Cu damascene removes the bulk of the overburden copper deposited by electroplating. Moderate hardness soft pad (Shore D 38–45) balances reasonable removal rate with protection of the underlying low-k dielectric from delamination under shear.
SOFT PAD Cu / Barrier Buff (BEOL Step 2)
Final clearing of barrier metal (Ta, TaN) and surface planarization after Cu bulk removal. Very soft pad (Shore D 28–38) minimizes scratch generation during this defect-critical finishing step. Post-CMP surface roughness Ra < 0.5 nm is the target.
SOFT PAD Low-k ILD Planarization
Porous low-k dielectrics (k < 2.5, porosity 20–50%) are mechanically fragile — Young’s modulus as low as 3–8 GPa. Only soft pads at reduced pressure (<2 psi) can polish these films without crack initiation. Stacked pad configurations with a very soft subpad are standard.
STACKED 300 mm Advanced Node Oxide
At 7 nm and below, incoming wafer bow exceeds 100 µm. A stacked configuration (hard IC1000-type top pad + soft Suba-type subpad) provides hard-pad planarization efficiency while the compliant subpad corrects for wafer bow. Industry-standard configuration at leading fabs.
HARD / SPECIALTY SiC / GaN Substrates
Compound semiconductors require specialty hard pads with enhanced chemical resistance and thermal stability. Standard hard PU pads underperform on SiC (Mohs 9.5). See: SiC-specific pad guide.

6. The Stacked Pad Strategy: Getting the Best of Both

The most practically important development in CMP pad engineering over the past decade is the widespread adoption of stacked pad configurations — combining a hard polishing top pad with a compliant foam subpad — to simultaneously achieve planarization efficiency and within-wafer uniformity. This strategy directly addresses the hard-vs-soft trade-off by decoupling the two functions into separate layers.

How the Stack Works

In a stacked pad configuration, the hard polyurethane top pad (Shore D 55–65) provides the polishing surface. Its high Young’s modulus ensures that contact with the wafer surface is dominated by the asperity-level mechanics that deliver planarization efficiency. Beneath the top pad, a soft foam subpad (typically Shore A 30–55, 0.5–1.5 mm thick) is laminated directly to the platen. The subpad’s role is purely mechanical: its bulk compliance absorbs wafer-scale bow and warp, redistributing the contact force from the carrier head more evenly across the wafer surface. The subpad does not contact the slurry or the wafer directly.

💡
Tuning the Stack: Subpad as a Process Knob The effective compressibility of the combined pad stack is primarily controlled by the subpad thickness and foam density. A thicker or softer subpad increases the stack’s macro-scale compliance, improving edge-center uniformity at the cost of some planarization efficiency. A thinner or harder subpad reduces compliance, shifting the balance back toward planarization performance. Process engineers at advanced fabs routinely fine-tune subpad hardness in 5–10 Shore A increments to optimize WIWNU profiles, treating the subpad as a variable process parameter rather than a fixed consumable.

Stack Configuration Naming Conventions

Stack Type Top Pad Subpad Application Sweet Spot
Hard / Hard Shore D 60–65 Shore D 45–55 (stiffer foam) Maximum planarization, mature node oxide — wafer bow not a concern
Hard / Soft (standard stack) Shore D 55–62 Shore A 35–50 (soft foam) 300 mm advanced node oxide and W CMP — industry standard configuration
Medium / Soft Shore D 45–55 Shore A 25–40 (very soft foam) Cu bulk step — balance of MRR and uniformity, moderate low-k protection
Soft / Very Soft Shore D 28–42 Shore A 20–30 (ultra-soft foam) Ultra-thin low-k finishing, Cu barrier buff — maximum defect protection

7. Decision Framework: Choosing the Right Pad Hardness

The following decision tree provides a systematic path from process step description to pad hardness recommendation. Work through the questions in order — the first applicable branching point gives the recommendation.

Is the target film ultra-hard (SiC, GaN, sapphire, Mohs > 8)?
Specialty hard pad or fixed-abrasive pad required. See SiC guide.
Continue to next question.
Is incoming step height > 500 Å (significant topography to remove)?
Hard pad (Shore D 55–65). Planarization efficiency is the priority.
Continue to next question.
Is the target film a fragile low-k dielectric (k < 2.8) or ultra-thin metal (< 50 nm)?
Soft pad (Shore D 28–42) at reduced pressure (< 2 psi). Shear protection is the priority.
Continue to next question.
Is within-wafer non-uniformity (WIWNU 1σ) required below 1%?
Soft pad or stacked (hard top + soft subpad). Uniformity is the priority.
Continue to next question.
Is wafer bow or warp > 50 µm (common in 300 mm stress-film wafers)?
Stacked pad configuration (hard top + soft subpad) to correct for bow-induced pressure non-uniformity.
Hard pad (Shore D 55–60) is the safe default for standard oxide and metal CMP steps.

8. Qualifying a New Pad Hardness in Production

Switching pad hardness — even within the same product family — is a significant process change that requires structured qualification. A change in Shore D hardness of even 5 points can shift the Preston coefficient by 8–15%, requiring recipe pressure adjustments. Here is the standard qualification protocol:

1

Establish Baseline Metrics on Qualified Pad

Run a minimum of 3 qualification lots (25 wafers each) on the currently qualified pad at the locked production recipe. Record mean removal rate, WIWNU (1σ), post-CMP scratch density (from KLA/Hitachi inspection), and electrical test results (if applicable). These become the acceptance criteria for the new hardness.

2

Run Initial Characterization Splits

Polish a minimum of 50 monitor wafers on the new-hardness pad at the existing production recipe parameters. Do not adjust the recipe yet. Compare MRR (target: within ±15% of baseline), WIWNU (target: within ±0.5% 1σ), and scratch density (target: within ±20%). Expect MRR to shift — the Preston coefficient changes with hardness. Recipe adjustment will be needed.

3

Adjust Recipe to Match Baseline MRR

If switching to a harder pad (MRR increased), reduce down-force pressure proportionally. If switching to a softer pad (MRR decreased), increase pressure. Use the Preston equation (MRR = Kp × P × V) as a first-order guide — the Kp of the new pad relative to the baseline can be estimated from the initial characterization data. Re-run 3 lots at the adjusted recipe to confirm MRR within ±8% of baseline.

4

Validate Conditioning Protocol

Pad conditioning parameters (conditioner down-force, sweep speed, in-situ vs. ex-situ ratio) optimized for the original hardness may need adjustment. Harder pads require more aggressive conditioning to prevent glazing; softer pads are more sensitive to over-conditioning. Optimize the conditioning protocol independently before committing to production qualification lots.

5

Run Full Qualification Lot and Engineering Sign-Off

Run 3 full-size production lots (25 wafers each) at the optimized recipe. All metrics must meet acceptance criteria. Obtain engineering and process owner sign-off. Update the process specification (process spec) with the new pad hardness, recipe parameters, and conditioning protocol before any production release.

For detailed guidance on pad conditioning protocols — which differ between hard and soft pad types — see: CMP Pad Conditioning and Lifespan Management. For the relationship between pad hardness and material removal rate at a quantitative level, see: CMP Material Removal Rate and Pad Parameters.

9. Jizhi’s Hard and Soft Pad Product Range

Jizhi Electronic Technology manufactures both hard and soft CMP polishing pads using proprietary polyurethane formulations developed through in-house R&D. Our product range is engineered to provide qualified alternatives to IC1000-type hard pads and Politex / Suba-type soft pads, with full process characterization data provided for each product.

Product Series Тип колодки Shore D Primary Application Доступность
JZ-H60 Series Твердый полиуретан 58–62 Oxide ILD, STI, PMD, W plug — IC1000 equivalent In stock
JZ-H65 Series Hard polyurethane (high hardness) 63–67 High-topography oxide CMP, aggressive step-height applications In stock
JZ-S38 Series Soft polyurethane subpad 35–42 Cu bulk removal (BEOL Step 1), stacked pad subpad In stock
JZ-S28 Series Very soft polyurethane 26–32 Cu / barrier buff (BEOL Step 2), ultra-thin low-k finishing In stock
JZ-SiC Series Specialty hard (SiC-optimized) 60–68 SiC and GaN substrate CMP, 3rd-generation semiconductors In stock / custom
JZ-Custom OEM Customer-specified Any range Custom hardness, groove, and formulation per customer spec 3–6 week lead time
🏭
Request Process Characterization Data Every Jizhi CMP pad series comes with a process characterization data package including: Shore D hardness map, pore size distribution, baseline MRR at reference recipe conditions, and WIWNU data. Contact our application engineering team to receive data for your specific process step and tool configuration. Request a data package →

10. Frequently Asked Questions

Can I use a hard pad for Cu CMP if I reduce the down-force pressure?
Reducing pressure to compensate for a hard pad in Cu CMP partially addresses the scratch and shear-force problem, but it does not solve the fundamental issue: a hard pad’s stiff asperities generate higher local contact stress per asperity contact than a soft pad at any given nominal pressure. Additionally, very low pressures can push the process into the hydrodynamic lubrication regime (Stribeck curve), causing unstable MRR and poor uniformity. For Cu BEOL, soft pads at standard pressure are strongly preferred over hard pads at reduced pressure — the physics favor the soft pad, not the recipe workaround.
Is a softer pad always safer for defect density?
Generally yes in terms of scratch defects, but not universally. Very soft pads can generate particle contamination from their open-cell foam structure if the foam sheds debris during conditioning or polishing. Additionally, soft pads used with incompatible slurry chemistry (e.g., highly oxidizing slurry on a low-Tg soft PU) can degrade faster, generating polymer debris that causes contamination defects. Defect density depends on the full pad-slurry-conditioning system, not pad hardness alone.
What Shore D value is considered “medium hardness” in CMP pads?
The industry does not have a formal “medium hardness” category, but pads in the Shore D 46–54 range are frequently described as medium hardness. These pads are sometimes used as a compromise when a single pad must serve both oxide-like and Cu-like steps in a simplified process flow. They deliver moderate planarization efficiency and moderate scratch performance — neither as good as a dedicated hard pad nor as safe as a dedicated soft pad. Most leading fabs avoid this compromise and maintain separate hard and soft pad SKUs for each process step.
How does pad hardness interact with slurry particle size for defect control?
Pad hardness and slurry particle size interact multiplicatively for scratch defect generation. A hard pad with large particles (d50 > 150 nm) creates the highest scratch risk. A soft pad with small particles (d50 < 80 nm) creates the lowest. The combination of pad hardness and particle size determines the effective contact stress at the three-body interface — both parameters must be optimized together. For Cu BEOL defect-critical steps, soft pads are paired with ultra-fine silica slurry (d50 30–60 nm). For oxide CMP where throughput matters more than defects, hard pads can use coarser ceria particles (d50 100–200 nm) without unacceptable scratch generation on the less defect-sensitive ILD films.
Does Jizhi offer pad samples for process evaluation before committing to volume purchase?
Yes. Jizhi Electronic Technology provides evaluation samples — typically 3–5 pads — for qualified customers conducting process characterization and pad qualification at their facility. Samples come with full characterization data packages. To request evaluation samples for your specific application (hard, soft, SiC-specific, or custom), please contact our application engineering team with your pad size, target application, and CMP tool type.

Hard Pad, Soft Pad, or Stacked — We Have Your Process Covered

Jizhi Electronic Technology supplies the full hardness spectrum of CMP polishing pads, from high-planarization-efficiency hard pads for oxide and tungsten CMP to ultra-soft subpads for Cu BEOL and low-k protection. Process characterization data and application engineering support included.

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