Highly Selective vs. Low Selective Tungsten CMP Slurry: Which One Does Your Process Need?

1. What Is Selectivity in Tungsten CMP?

In tungsten CMP, selectivity is defined as the ratio of the tungsten material removal rate (W MRR) to the silicon dioxide dielectric material removal rate (Oxide MRR), measured under identical polishing conditions on blanket film test wafers:

This ratio is a formulation property — determined primarily by the slurry’s oxidizer concentration, pH, abrasive type, and the presence or absence of selective inhibitor additives — but it is also a process variable that shifts with downforce, rotation speed, temperature, and pad condition. A selectivity value on a data sheet applies only at the test conditions stated; understanding how selectivity changes with process parameters is as important as knowing the nominal value.

Selectivity values encountered in commercial tungsten CMP slurries span a wide range:

• Hyper-selective: W:Oxide >100:1 — oxide MRR so low it is essentially negligible during Step 1
• Highly selective: W:Oxide 25:1–100:1 — standard Step 1 bulk removal range
• Moderately selective: W:Oxide 5:1–25:1 — endpoint clearing or transitional step applications
• Low selective (non-selective): W:Oxide 0.5:1–3:1 — Step 2 buff and barrier step range

2. Highly Selective Slurry: Mechanism, Properties, and Trade-offs

A highly selective tungsten CMP slurry achieves its elevated W:Oxide ratio through formulation design that accelerates tungsten oxidation and removal while simultaneously protecting the oxide surface from significant abrasive attack. The primary mechanisms are:

Elevated oxidizer and catalyst activity toward tungsten: Higher H₂O₂ concentration (within the optimal window) and well-tuned Fe³⁺ catalyst loading ensure rapid WO₃ formation at the tungsten surface, maintaining a high tungsten MRR.

Selective surface passivation of oxide: Some highly selective formulations incorporate additive molecules (typically organic amines, polyelectrolytes, or surfactants) that adsorb preferentially onto the oxide surface and reduce the contact probability between abrasive particles and the dielectric, lowering the effective oxide MRR without significantly affecting tungsten removal. This is distinct from simply using a softer or smaller abrasive — the selective passivation mechanism specifically targets the oxide-abrasive interaction.

pH optimization for tungsten vs. oxide abrasion balance: At lower pH within the acidic W CMP window, the surface chemistry of both the abrasive and the oxide surface can be tuned to favor mechanical removal of the softer WO₃ while leaving the harder SiO₂ dielectric relatively unaffected.

3. Low Selective (Non-Selective) Slurry: Mechanism, Properties, and Trade-offs

A low selective or non-selective tungsten CMP slurry removes tungsten and oxide at comparable rates, typically within a 3:1 ratio or better (some formulations achieve near-unity 1:1 selectivity). This behavior results from formulations that do not include selective passivation additives for oxide, use abrasive types and sizes that effectively remove both tungsten oxide and silicon dioxide, and operate at pH conditions where both materials are susceptible to mechanical abrasion at similar rates.

4. Decision Framework: Which to Use at Each Step

5. Logic Applications: Contact and Gate CMP

At sub-14 nm logic nodes, the combination of very small feature sizes, extreme dishing tolerances, and tight dielectric loss budgets makes selectivity management one of the most precision-sensitive aspects of tungsten CMP process development.

MOL Contact CMP: Contacts at sub-5 nm nodes are below 15 nm in diameter, but dishing and erosion tolerances are in the sub-50 Å range because any concavity in the contact surface directly increases electrical contact resistance at the transistor terminal. A two-step process with highly selective Step 1 (W:Oxide >50:1) and a very brief, carefully timed non-selective Step 2 (limited erosion budget) is the standard approach. Step 1 overpolish time is minimized to limit dishing: with contact diameters below 15 nm, even isolated features (essentially every contact in a logic context) do not generate significant pad-deflection dishing, but the overpolish rate is still the primary dishing accumulation mechanism.

RMG Gate CMP: Replacement metal gate polishing requires high selectivity in the clearing step to protect the high-k dielectric and surrounding ILD from removal, followed by a buff step tuned for low surface roughness and minimal residue. The gate height uniformity budget (which maps to transistor V_th spread) may require even tighter endpoint control than the contact CMP step.

For logic applications at leading-edge nodes, colloidal silica abrasive — with its narrow PSD and lower scratch risk — is strongly preferred over fumed silica, because the sub-50 Å dishing and <10 defects/cm² post-clean targets leave essentially zero tolerance for abrasive-induced scratch events.

6. 3D NAND Applications: Wordline and Staircase CMP

3D NAND tungsten CMP presents a unique selectivity challenge because the structure being polished is not a simple metal-in-dielectric pattern but a multi-layer stack of alternating oxide and tungsten films, each potentially several nanometers thick, stacked to heights of 5 μm or more. The CMP process must planarize this structure without causing delamination between the oxide/tungsten interfaces under the applied mechanical stress.

Selectivity in the 3D NAND context affects two somewhat different objectives:

Wordline tungsten removal: The top surface of the deposited tungsten must be cleared uniformly from both the dense array region and the stepped staircase contact region, which have very different pattern densities. A moderately selective slurry (10:1–25:1) balances the competing requirements of efficient tungsten clearing in the array with adequate oxide protection at the staircase contacts where the oxide surface is exposed at different wordline levels.

Stack stress management: Very high downforce in combination with high-selectivity slurry formulations that drive high MRR can generate mechanical stress on the 3D NAND stack that risks delamination at the oxide/nitride and oxide/tungsten interfaces. 3D NAND-specific slurry formulations typically target lower downforce operation with enhanced chemical contribution to MRR, achieving the needed tungsten removal rate through chemistry rather than pressure — reducing the risk of mechanical stack damage.

7. DRAM Applications: Buried Wordline and Storage Node Contact

DRAM tungsten CMP applications require a different balance of selectivity requirements than logic or NAND, driven by the specific geometry and tolerance stack of DRAM cell structures.

Buried Wordline (bWL) CMP: After tungsten fills the narrow bWL trenches (recessed below the active silicon surface), the overburden must be cleared and the tungsten must be recessed to a precisely controlled depth. This depth tolerance is extremely tight — ±5 Å in advanced DRAM — because the wordline recess determines the gate-to-active overlap and thus the cell’s threshold voltage and read/write margin. A highly selective Step 1 slurry with strong endpoint detection is required; any low-selectivity buff step must be extremely brief and tightly timed to avoid additional recess beyond specification.

Storage Node Contact (SNC) CMP: The storage node contact connects the bitline to the capacitor electrode through a high aspect ratio via filled with tungsten. SNC CMP is primarily a surface quality and contamination control step — the contact must be flat, clean, and free of metallic contamination that could increase capacitor leakage. A moderate selectivity slurry with excellent defect performance (particularly Fe and other metallic impurity control) is appropriate, as the electrical sensitivity of the capacitor to surface metallic contamination is higher than for logic contacts.

8. Overpolish Strategy and Selectivity Interaction

Overpolish — the additional polish time beyond the nominal endpoint of tungsten clearance — is an unavoidable component of production CMP processes because within-wafer non-uniformity means the fastest-polishing region of the wafer clears before the slowest. The amount of overpolish needed is set by the WIWNU of Step 1; tighter WIWNU requires less overpolish, which in turn reduces both dishing (in Step 1) and the need for a long Step 2 buff.

The relationship between selectivity and overpolish outcomes is straightforward:

• For every 10 seconds of overpolish at 2,000 Å/min W MRR with a 50:1 selective slurry, approximately 330 Å of tungsten recess accumulates in a feature where the pad can contact the tungsten center — a significant fraction of the dishing budget at advanced nodes.
• For every 10 seconds of overpolish in Step 2 at 500 Å/min oxide MRR with a 2:1 selective slurry, approximately 83 Å of oxide erosion accumulates in high-density array regions — a tolerable rate if Step 2 time is carefully controlled.

These calculations make clear why the two-step overpolish allocation — how much time in Step 1 vs. Step 2 — is the primary lever for balancing dishing and erosion simultaneously, and why improving Step 1 WIWNU (to reduce required overpolish) has compound benefits on both defect metrics.

9. Process Window: How Conditions Modify Effective Selectivity

The selectivity value on a slurry data sheet is measured at a specific set of process conditions. In production, process conditions vary within a tool-to-tool and lot-to-lot range, and selectivity varies with them. Understanding these dependencies prevents misinterpretation of qualification data.

The most critical practical implication: increasing downforce — a tempting lever for improving throughput on a low-MRR process — tends to reduce effective selectivity, increasing oxide erosion risk in the dense array regions. If throughput improvement is needed, increasing downforce on a Step 1 process should be accompanied by a re-characterization of dishing and erosion performance, not just W MRR.

10. Common Mistakes in Selectivity Selection

The following errors in selectivity selection or application are observed frequently in process development and production CMP engineering:

Using Step 1 selectivity to evaluate Step 2 performance: Requesting selectivity data on a buff slurry and comparing it to a bulk removal slurry’s selectivity, as if a higher selectivity is always better, misses the purpose of the buff step. Low selectivity in Step 2 is a feature, not a deficiency — it is what enables topography correction and surface planarization.

Running Step 1 overpolish with Step 2 selectivity: Using a non-selective slurry on Platen 1 in a misguided attempt to eliminate the buff step entirely is a common process simplification that typically produces unacceptable levels of array erosion. The two steps have different objectives; the step structure exists for a reason.

Assuming high selectivity eliminates dishing: Very high selectivity (>100:1) does not prevent dishing — it eliminates the planarizing effect that lower selectivity would provide. Dishing in Step 1 is primarily a function of overpolish time and feature geometry, not simply selectivity. High selectivity makes dishing worse by continuing to remove tungsten without removing the surrounding oxide to compensate.

Using a single selectivity number for process design without verifying temperature and downforce dependence: A 50:1 selectivity number measured at 2 psi and 25°C may be 20:1 or 30:1 at the actual production downforce and slurry temperature at your facility. Always request selectivity characterization across your production operating window, not just at a single test condition.