{"id":2289,"date":"2026-06-09T15:53:40","date_gmt":"2026-06-09T07:53:40","guid":{"rendered":"https:\/\/jeez-semicon.com\/?p=2289"},"modified":"2026-06-09T15:53:40","modified_gmt":"2026-06-09T07:53:40","slug":"silicon-wafer-surface-defects-in-cmp-causes-detection-prevention","status":"publish","type":"post","link":"https:\/\/jeez-semicon.com\/ru\/blog\/silicon-wafer-surface-defects-in-cmp-causes-detection-prevention\/","title":{"rendered":"Silicon Wafer Surface Defects in CMP: Causes, Detection &amp; Prevention"},"content":{"rendered":"<style>\n@import url('https:\/\/fonts.googleapis.com\/css2?family=Sora:wght@400;500;600;700;800&family=IBM+Plex+Sans:ital,wght@0,300;0,400;0,500;0,600;1,400&display=swap');\n.jeez-pillar*,.jeez-pillar*::before,.jeez-pillar*::after{box-sizing:border-box;margin:0;padding:0}\n.jeez-pillar{font-family:'IBM Plex Sans',-apple-system,BlinkMacSystemFont,sans-serif;font-size:17px;line-height:1.78;color:#1C2B3A;max-width:900px;margin:0 auto;padding:0 0 3rem}\n.jeez-pillar h2,.jeez-pillar h3,.jeez-pillar h4{font-family:'Sora',-apple-system,sans-serif;line-height:1.25}\n.jeez-pillar h2{font-size:1.85rem;font-weight:700;color:#07193A;margin:3rem 0 1.1rem;padding-bottom:.65rem;border-bottom:3px solid #1553A0}\n.jeez-pillar h3{font-size:1.2rem;font-weight:600;color:#1553A0;margin:2rem 0 .75rem}\n.jeez-pillar p{margin-bottom:1.3rem}.jeez-pillar p:last-child{margin-bottom:0}\n.jeez-pillar ul,.jeez-pillar ol{padding-left:1.5rem;margin-bottom:1.3rem}\n.jeez-pillar li{margin-bottom:.5rem}\n.jeez-pillar strong{font-weight:600;color:#07193A}\n.jeez-pillar a{color:#1553A0;text-decoration:none;border-bottom:1px solid rgba(21,83,160,.35);transition:color .18s,border-color .18s}\n.jeez-pillar a:hover{color:#007B6E;border-bottom-color:#007B6E}\n.jp-back{display:inline-flex;align-items:center;gap:.5rem;font-family:'Sora',sans-serif;font-size:.82rem;font-weight:600;color:#1553A0;background:#EEF4FF;border:1px solid #C5D6F5;border-radius:6px;padding:.4rem .9rem;text-decoration:none;border-bottom:none;margin-bottom:1.5rem;transition:background .18s}\n.jp-back:hover{background:#1553A0;color:#fff}\n.jp-hero{background:linear-gradient(135deg,#071B40 0%,#1553A0 55%,#0086A0 100%);color:#fff;padding:3rem 2.75rem 2.75rem;border-radius:14px;margin-bottom:2.5rem;position:relative;overflow:hidden}\n.jp-hero::before{content:'';position:absolute;top:-50px;right:-50px;width:240px;height:240px;border:48px solid rgba(255,255,255,.06);border-radius:50%;pointer-events:none}\n.jp-hero::after{content:'';position:absolute;bottom:-70px;right:80px;width:320px;height:320px;border:48px solid rgba(255,255,255,.04);border-radius:50%;pointer-events:none}\n.jp-hero-eyebrow{font-family:'Sora',sans-serif;font-size:.72rem;font-weight:600;letter-spacing:.18em;text-transform:uppercase;color:rgba(255,255,255,.6);margin-bottom:.85rem}\n.jp-hero h1{font-family:'Sora',sans-serif;font-size:2.1rem;font-weight:800;line-height:1.15;color:#fff;margin-bottom:1.1rem}\n.jp-hero-lead{font-size:1rem;color:rgba(255,255,255,.85);max-width:660px;line-height:1.72;margin-bottom:1.5rem}\n.jp-hero-meta{display:flex;gap:1.75rem;flex-wrap:wrap;font-size:.8rem;color:rgba(255,255,255,.55);font-family:'Sora',sans-serif}\n.jp-toc{background:#EEF4FF;border:1px solid #C5D6F5;border-left:5px solid #1553A0;border-radius:0 10px 10px 0;padding:1.6rem 2rem 1.6rem 1.75rem;margin:0 0 2.75rem}\n.jp-toc-title{font-family:'Sora',sans-serif;font-size:.78rem;font-weight:700;letter-spacing:.14em;text-transform:uppercase;color:#07193A;margin-bottom:1rem}\n.jp-toc ol{column-count:2;column-gap:2.5rem;margin:0;padding-left:1.25rem}\n.jp-toc li{margin-bottom:.45rem;break-inside:avoid;font-size:.88rem}\n.jp-toc a{color:#1553A0;border-bottom:none;font-weight:400;line-height:1.5}\n.jp-toc a:hover{text-decoration:underline;color:#007B6E}\n@media(max-width:620px){.jp-toc ol{column-count:1}}\n.jp-stats{display:grid;grid-template-columns:repeat(auto-fit,minmax(170px,1fr));gap:1rem;margin:1.75rem 0}\n.jp-stat{background:#07193A;color:#fff;border-radius:10px;padding:1.35rem 1.25rem;text-align:center}\n.jp-stat-value{font-family:'Sora',sans-serif;font-size:1.9rem;font-weight:700;color:#6DB8FF;display:block;line-height:1;margin-bottom:.45rem}\n.jp-stat-label{font-size:.78rem;color:rgba(255,255,255,.65);line-height:1.45}\n.jp-callout{padding:1.2rem 1.5rem;border-radius:0 10px 10px 0;border-left:4px solid #1553A0;background:#EEF4FF;margin:1.75rem 0;font-size:.93rem;line-height:1.7}\n.jp-callout.teal{background:#E0F5F1;border-color:#007B6E}\n.jp-callout.amber{background:#FFF8E6;border-color:#D97706}\n.jp-callout.slate{background:#F1F5F9;border-color:#475569}\n.jp-steps{list-style:none;padding:0;margin:1.5rem 0;counter-reset:jp-step}\n.jp-steps li{counter-increment:jp-step;position:relative;padding:1.1rem 1.25rem 1.1rem 3.75rem;background:#F7FAFD;border:1px solid #E2EAF4;border-radius:10px;margin-bottom:.85rem}\n.jp-steps li::before{content:counter(jp-step);position:absolute;left:1rem;top:50%;transform:translateY(-50%);width:30px;height:30px;background:#1553A0;color:#fff;border-radius:50%;display:flex;align-items:center;justify-content:center;font-size:.8rem;font-weight:700;font-family:'Sora',sans-serif}\n.jp-steps li strong{display:block;font-family:'Sora',sans-serif;font-size:.95rem;color:#07193A;margin-bottom:.35rem}\n.jp-compare{display:grid;grid-template-columns:1fr 1fr;gap:1.1rem;margin:1.5rem 0}\n@media(max-width:600px){.jp-compare{grid-template-columns:1fr}}\n.jp-compare-box{background:#F7FAFD;border:1px solid #E2EAF4;border-top:4px solid #1553A0;border-radius:0 0 10px 10px;padding:1.25rem}\n.jp-compare-box:nth-child(2){border-top-color:#007B6E}\n.jp-compare-box h4{font-family:'Sora',sans-serif;font-size:.95rem;font-weight:700;color:#07193A;margin-bottom:.85rem}\n.jp-compare-box ul{padding-left:1.15rem;margin:0}\n.jp-compare-box li{font-size:.875rem;color:#334155;margin-bottom:.45rem}\n.jp-table-wrap{overflow-x:auto;margin:1.75rem 0;border-radius:10px;border:1px solid #E2EAF4;box-shadow:0 1px 4px rgba(21,83,160,.06)}\n.jp-table{width:100%;border-collapse:collapse;font-size:.865rem;background:#fff}\n.jp-table thead th{background:#07193A;color:#fff;padding:11px 15px;text-align:left;font-family:'Sora',sans-serif;font-weight:600;font-size:.77rem;letter-spacing:.05em;text-transform:uppercase;white-space:nowrap}\n.jp-table td{padding:10px 15px;border-bottom:1px solid #EEF2F8;vertical-align:top;line-height:1.55}\n.jp-table tr:last-child td{border-bottom:none}\n.jp-table tbody tr:nth-child(even) td{background:#F7FAFD}\n.jp-readmore{display:inline-flex;align-items:center;gap:7px;font-family:'Sora',sans-serif;font-size:.86rem;font-weight:600;color:#1553A0;border:none!important;text-decoration:none;padding:.55rem 1.1rem;background:#EEF4FF;border-radius:6px;margin-top:.75rem;transition:background .18s,color .18s}\n.jp-readmore:hover{background:#1553A0;color:#fff!important}\n.jp-readmore::after{content:'\u2192'}\n.jp-hr{border:none;border-top:1px solid #E2EAF4;margin:2.75rem 0}\n.jp-related{background:#F7FAFD;border:1px solid #E2EAF4;border-radius:12px;padding:1.75rem 2rem;margin:2.5rem 0}\n.jp-related-title{font-family:'Sora',sans-serif;font-size:.78rem;font-weight:700;letter-spacing:.14em;text-transform:uppercase;color:#07193A;margin-bottom:1.1rem}\n.jp-related-links{display:flex;flex-direction:column;gap:.6rem}\n.jp-rl{display:flex;align-items:flex-start;gap:.75rem;padding:.7rem .9rem;background:#fff;border:1px solid #E2EAF4;border-radius:8px;text-decoration:none;border-bottom:none;color:#1C2B3A;transition:border-color .18s,box-shadow .18s}\n.jp-rl:hover{border-color:#1553A0;box-shadow:0 2px 8px rgba(21,83,160,.1)}\n.jp-rl-icon{font-size:1.1rem;flex-shrink:0;margin-top:1px}\n.jp-rl strong{display:block;font-family:'Sora',sans-serif;font-size:.88rem;font-weight:600;color:#07193A;margin-bottom:2px}\n.jp-rl span{font-size:.8rem;color:#5A6A7A}\n.jp-faq{margin:1.5rem 0}\n.jp-faq-item{border:1px solid #E2EAF4;border-radius:10px;margin-bottom:.75rem;overflow:hidden}\n.jp-faq-q{padding:1.05rem 1.35rem;font-family:'Sora',sans-serif;font-size:.93rem;font-weight:600;color:#07193A;background:#F7FAFD;cursor:pointer;display:flex;justify-content:space-between;align-items:center;user-select:none;gap:1rem;transition:background .15s}\n.jp-faq-q:hover{background:#EEF4FF}\n.jp-faq-icon{flex-shrink:0;width:24px;height:24px;background:#1553A0;color:#fff;border-radius:50%;display:flex;align-items:center;justify-content:center;font-size:1.1rem;line-height:1;transition:transform .2s,background .2s}\n.jp-faq-q.jp-open .jp-faq-icon{transform:rotate(45deg);background:#007B6E}\n.jp-faq-a{display:none;padding:1.1rem 1.35rem;font-size:.91rem;line-height:1.75;color:#2D3F50;background:#fff;border-top:1px solid #E2EAF4}\n.jp-faq-a.jp-open{display:block}\n.jp-cta{background:linear-gradient(135deg,#071B40,#1553A0 70%,#006DAB);color:#fff;padding:2.75rem 2.5rem;border-radius:14px;text-align:center;margin:3rem 0 0}\n.jp-cta h2{font-family:'Sora',sans-serif;font-size:1.5rem;font-weight:700;color:#fff;border:none;margin:0 0 .85rem;padding:0}\n.jp-cta p{color:rgba(255,255,255,.82);font-size:1rem;max-width:580px;margin:0 auto 1.75rem}\n.jp-cta-btn{display:inline-block;background:#fff;color:#1553A0!important;padding:.85rem 2.25rem;border-radius:7px;font-family:'Sora',sans-serif;font-weight:700;font-size:.95rem;text-decoration:none;border:none!important;transition:background .2s,transform .2s}\n.jp-cta-btn:hover{background:#D4E7FF;transform:translateY(-2px);color:#07193A!important}\n@media(max-width:640px){.jp-hero{padding:2rem 1.5rem}.jp-hero h1{font-size:1.6rem}.jeez-pillar h2{font-size:1.4rem}.jp-cta{padding:2rem 1.5rem}}\n.jeez-pillar [id]{scroll-margin-top:90px}\n<\/style>\n<div class=\"jeez-pillar\">\n<a href=\"https:\/\/jeez-semicon.com\/ru\/blog\/The-Complete-Guide-to-Silicon-Wafer-Polishing\/\" target=\"_blank\" class=\"jp-back\">\u2190 Back to: The Complete Guide to Silicon Wafer Polishing<\/a>\n<div class=\"jp-hero\">\n<div class=\"jp-hero-eyebrow\">JEEZ Semiconductor Materials &nbsp;\u00b7&nbsp; Technical Guide &nbsp;\u00b7&nbsp; Updated June 2026<\/div>\n<p class=\"jp-hero-lead\">A comprehensive reference for engineers managing defect yield in silicon wafer CMP \u2014 classifying scratches, COPs, LPDs, haze, and edge roll-off; tracing each to its root cause; and presenting evidence-based prevention strategies.<\/p>\n<div class=\"jp-hero-meta\">~2,500 words &nbsp;\u00b7&nbsp; 10-minute read &nbsp;\u00b7&nbsp; Published by JEEZ<\/div>\n<\/div>\n<div class=\"jp-toc\"><div class=\"jp-toc-title\">\u041e\u0433\u043b\u0430\u0432\u043b\u0435\u043d\u0438\u0435<\/div><ol><li><a href=\"#intro\">Why Defect Control Is the #1 CMP Challenge<\/a><\/li><li><a href=\"#scratch\">Scratch Defects<\/a><\/li><li><a href=\"#cops\">Crystal-Originated Pits (COPs)<\/a><\/li><li><a href=\"#lpd\">Light Point Defects (LPDs)<\/a><\/li><li><a href=\"#haze\">Surface Haze<\/a><\/li><li><a href=\"#edge\">Edge Roll-off<\/a><\/li><li><a href=\"#detection\">Defect Detection and Metrology<\/a><\/li><li><a href=\"#faq\">\u0427\u0430\u0441\u0442\u043e \u0437\u0430\u0434\u0430\u0432\u0430\u0435\u043c\u044b\u0435 \u0432\u043e\u043f\u0440\u043e\u0441\u044b<\/a><\/li><\/ol><\/div>\n\n<section id=\"intro\">\n<h2>Why Defect Control Is the #1 CMP Yield Challenge<\/h2>\n<p>A single scratch on a polished silicon wafer detected during laser-scanning surface inspection triggers immediate wafer rejection, writing off all upstream manufacturing cost \u2014 ingot growth, slicing, lapping, etching, and polishing \u2014 that may represent $200\u2013500 per wafer. Defect control in silicon wafer CMP is therefore not a quality-assurance afterthought; it is the primary economic driver of the polishing operation.<\/p>\n<p>This guide from Jizhi Electronic Technology Co., Ltd. (JEEZ) classifies the five major types of CMP defects encountered in silicon wafer polishing, traces each to its root cause, explains how they are detected, and presents the process engineering strategies that minimize them. For a broader context, see our <a href=\"https:\/\/jeez-semicon.com\/ru\/blog\/The-Complete-Guide-to-Silicon-Wafer-Polishing\/\" target=\"_blank\">Complete Guide to Silicon Wafer Polishing<\/a>.<\/p>\n<div class=\"jp-stats\">\n<div class=\"jp-stat\"><span class=\"jp-stat-value\">&lt;30<\/span><span class=\"jp-stat-label\">LPD count target per 300mm prime wafer at 35 nm detection threshold<\/span><\/div>\n<div class=\"jp-stat\"><span class=\"jp-stat-value\">500 nm<\/span><span class=\"jp-stat-label\">Critical &#8220;killer particle&#8221; size threshold: particles above this cause most scratches<\/span><\/div>\n<div class=\"jp-stat\"><span class=\"jp-stat-value\">&lt;0.03 ppm<\/span><span class=\"jp-stat-label\">Haze specification on 300mm prime-grade silicon wafers post-final polish<\/span><\/div>\n<\/div>\n<\/section>\n<hr class=\"jp-hr\">\n\n<section id=\"scratch\">\n<h2>Defect Type 1 \u2014 Scratch Defects<\/h2>\n<p>Scratches are the highest-severity defect class in silicon wafer CMP. They appear as linear or arc-shaped grooves on the wafer front surface, with widths ranging from ~0.05 \u03bcm (borderline detectable) to several micrometers and lengths from tens of micrometers to full-wafer arcs traversing most of the 300mm diameter. Scratches are detected during laser-scanning surface inspection (e.g., KLA Surfscan SP series) as elongated high-signal events with a specific shape signature that distinguishes them from round particles or pits.<\/p>\n<h3>Root Causes of Scratches<\/h3>\n<ul>\n<li><strong>Killer particles in slurry:<\/strong> Abrasive agglomerates &gt;500 nm that lodge between the pad and the wafer surface and are dragged across the wafer by the rotating pad. These are the most common and most preventable scratch source. Agglomerates form when slurry pH drifts outside the stability window, when slurry sits stagnant in delivery lines (sedimentation followed by flow disruption), or when slurry exceeds its shelf life.<\/li>\n<li><strong>Pad debris:<\/strong> Fragments of pad material shed during polishing or conditioning can act as abrasive bodies. This is more common after aggressive conditioning or when a new pad is improperly broken in.<\/li>\n<li><strong>Environmental contamination:<\/strong> Particles from the cleanroom environment, from polishing tool internals (bearing wear, retaining ring fragments), or from inadequate tooling maintenance enter the slurry dispense path and appear at the wafer surface.<\/li>\n<li><strong>Slurry cross-contamination:<\/strong> Residual rough-polish slurry (larger particles) carry-over into the finish-polish step, where their particle size is grossly mismatched to the soft pad and low-pressure conditions.<\/li>\n<\/ul>\n<h3>Prevention<\/h3>\n<ul>\n<li>Install 0.2\u20130.5 \u03bcm point-of-use filters on all slurry delivery lines<\/li>\n<li>Monitor slurry D99 and Dmax with single-particle optical sensing (SPOS\/LFI) \u2014 not just DLS D50<\/li>\n<li>Implement slurry delivery line flush protocols after tool idle periods (&gt;30 min)<\/li>\n<li>Perform a DI water or dilute acid quench rinse between rough and finish polish steps<\/li>\n<li>Execute a proper pad break-in protocol after each pad change<\/li>\n<\/ul>\n<\/section>\n<hr class=\"jp-hr\">\n\n<section id=\"cops\">\n<h2>Defect Type 2 \u2014 Crystal-Originated Pits (COPs)<\/h2>\n<p>COPs (Crystal-Originated Pits) are octahedral vacancy-cluster voids present in the bulk Czochralski-grown silicon crystal before any polishing occurs. They form during crystal growth when the ingot cools through a critical temperature range: silicon vacancies condense into octahedral void clusters of 50\u2013200 nm diameter. In standard (non-COP-free) CZ silicon, COPs occur at densities of 10\u00b2\u201310\u2074 cm\u207b\u00b3.<\/p>\n<p>During alkaline CMP, the polishing process intersects the sub-surface void clusters and the interior of each void \u2014 which lacks a silicon crystal lattice on its exposed faces \u2014 etches faster than the surrounding perfect crystal. The result is a characteristic octahedral pit on the polished surface with a size of 0.1\u20130.3 \u03bcm, classified as a COP-related LPD on surface inspection.<\/p>\n<h3>Mitigating COP Manifestation in Polishing<\/h3>\n<ul>\n<li>Use COP-free (or COP-reduced) silicon crystal from ingot growers who use controlled V\/G growth conditions, nitrogen doping, or hydrogen annealing to suppress vacancy cluster formation<\/li>\n<li>Avoid over-aggressive alkaline chemistry in the finish polish (pH &gt;11.2 at elevated temperature) which accelerates void interior etching and enlarges pits<\/li>\n<li>Hydrogen annealing of polished wafers (1150\u20131200\u00b0C in H\u2082 atmosphere) fills and annihilates near-surface COPs \u2014 a process option for zero-COP epi-ready wafer production<\/li>\n<\/ul>\n<\/section>\n<hr class=\"jp-hr\">\n\n<section id=\"lpd\">\n<h2>Defect Type 3 \u2014 Light Point Defects (LPDs) and Particles<\/h2>\n<p>Light point defects are the primary pass\/fail metric for polished silicon wafer quality. On a KLA Surfscan SP3 or SP5 system, the wafer is illuminated with a focused laser beam in dark-field mode; any surface feature that scatters light above the detection threshold (typically 35 nm or 60 nm calibrated sphere diameter equivalent) registers as an LPD event. LPDs include particles, pits, mounds, and surface anomalies of all physical origins.<\/p>\n<p>In the context of CMP process control, the key LPD sources are:<\/p>\n<ul>\n<li><strong>Residual slurry abrasive:<\/strong> Colloidal silica particles that adhere to the polished surface and are not removed by post-CMP cleaning. Electrostatic adhesion between the slightly positive silicon surface and negatively charged silica particles can be surprisingly strong, especially if the pH drops during the rinse sequence.<\/li>\n<li><strong>Re-deposited silicon species:<\/strong> Dissolved SiO\u2082\u00b7nH\u2082O from the polishing reaction can re-precipitate as amorphous silica micro-deposits during rinsing, particularly if the rinse water temperature or pH is not well-controlled.<\/li>\n<li><strong>Pad debris and atmospheric particles:<\/strong> Small fragments from pad conditioning or ambient contamination that land on the wafer surface during or after polishing.<\/li>\n<\/ul>\n<p>Achieving LPD counts below 30 at 35 nm on 300mm wafers requires both excellent slurry quality and a highly effective post-CMP cleaning sequence. For cleaning protocols, see: <a href=\"https:\/\/jeez-semicon.com\/ru\/blog\/Post-CMP-Cleaning-for-Silicon-Wafers-Methods-and-Best-Practices\/\" target=\"_blank\">Post-CMP Cleaning for Silicon Wafers: Methods and Best Practices<\/a>.<\/p>\n<\/section>\n<hr class=\"jp-hr\">\n\n<section id=\"haze\">\n<h2>Defect Type 4 \u2014 Surface Haze<\/h2>\n<p>Haze is not a discrete defect but a spatially distributed surface characteristic: the intensity of diffuse scattered light from micro-roughness across the wafer surface, measured in parts per million (ppm) of incident light intensity. Haze arises from surface features at spatial wavelengths between ~1 and ~10 \u03bcm \u2014 too small to resolve as individual LPDs but collectively measurable as a background signal on the surface inspector.<\/p>\n<p>Haze has two distinct origins in CMP:<\/p>\n<ul>\n<li><strong>Roughness haze:<\/strong> Micro-roughness at the 1\u201310 \u03bcm spatial frequency range, typically produced by over-polishing (where isotropic chemical etching roughens the crystal surface along crystallographic directions), by mechanical abrasion from an overly stiff pad or overly large slurry particles, or by pad-to-wafer contact non-uniformity that creates azimuthal roughness patterns.<\/li>\n<li><strong>Contamination haze:<\/strong> Thin chemical contamination films \u2014 residual slurry organic additives, silicic acid re-deposits, or oxidation films \u2014 that create a spatially uniform increase in scattered light intensity rather than discrete LPD events.<\/li>\n<\/ul>\n<p>Haze is controlled by optimizing the SSP finish polish parameters (slurry pH, particle size, pad hardness, pressure, and polish time) and by ensuring effective post-CMP cleaning removes all chemical residues before inspection. For detailed guidance on achieving sub-0.03 ppm haze levels, see: <a href=\"https:\/\/jeez-semicon.com\/ru\/blog\/How-to-Achieve-Sub-nm-Surface-Roughness-in-Silicon-Wafer-CMP\/\" target=\"_blank\">How to Achieve Sub-nm Surface Roughness in Silicon Wafer CMP<\/a>.<\/p>\n<\/section>\n<hr class=\"jp-hr\">\n\n<section id=\"edge\">\n<h2>Defect Type 5 \u2014 Edge Roll-off and Edge Exclusion<\/h2>\n<p>The wafer edge zone \u2014 typically defined as the outermost 2\u20135 mm of the wafer radius \u2014 is the most geometrically challenging region in CMP. The polishing pad extends beyond the wafer edge during processing; as it does so, the contact pressure distribution at the wafer periphery diverges from the contact mechanics in the central area. Depending on retaining ring load, pad stiffness, and slurry film thickness, the result is either edge-fast (roll-down) or edge-slow (roll-up) removal \u2014 both are referred to as &#8220;edge roll-off&#8221; and both produce SFQR failures at the outermost exposure sites.<\/p>\n<p>Edge roll-off translates directly to yield loss: die sites in the edge exclusion zone cannot meet overlay specifications and are scrapped. Minimizing the edge exclusion zone from the standard 2 mm toward 1 mm is a significant yield-improvement opportunity at 300mm.<\/p>\n<p>Control strategies include: retaining ring material and load optimization, edge profile (chamfer geometry) standardization, and carrier head edge zone pressure control in multi-zone membrane systems. For detailed 300mm edge management strategies, see: <a href=\"https:\/\/jeez-semicon.com\/ru\/blog\/300mm-Silicon-Wafer-Polishing-Challenges-and-Uniformity-Control\/\" target=\"_blank\">300mm Silicon Wafer Polishing: Challenges and Uniformity Control<\/a>.<\/p>\n<\/section>\n<hr class=\"jp-hr\">\n\n<section id=\"detection\">\n<h2>Defect Detection and Metrology<\/h2>\n<p>Three principal metrology techniques characterize defect levels on polished silicon wafers:<\/p>\n<ul>\n<li><strong>Laser-scanning surface inspection (Surfscan SP3\/SP5, Candela CS920):<\/strong> Scans the entire wafer at high speed in dark-field illumination. Reports LPD count at specified size thresholds, haze level (ppm), and defect location maps. Essential for go\/no-go quality control on every wafer.<\/li>\n<li><strong>Atomic force microscopy (AFM):<\/strong> Provides true topographic maps at nanometer-scale resolution over 1\u00d71 \u03bcm to 10\u00d710 \u03bcm scan areas. Used to characterize roughness (Ra, Rq), identify scratch morphology, and confirm the nature of LPD events. Too slow for 100% production inspection; used for process development and failure analysis.<\/li>\n<li><strong>Transmission electron microscopy (TEM) \/ cross-sectional SEM:<\/strong> Reveals sub-surface crystal damage, COP morphology, and the depth profile of scratch damage. Destructive technique used in root-cause analysis of defect events, not routine inspection.<\/li>\n<\/ul>\n<\/section>\n\n<div class=\"jp-related\"><div class=\"jp-related-title\">Related Articles in This Series<\/div><div class=\"jp-related-links\">\n<a href=\"https:\/\/jeez-semicon.com\/ru\/blog\/The-Complete-Guide-to-Silicon-Wafer-Polishing\/\" target=\"_blank\" class=\"jp-rl\"><span class=\"jp-rl-icon\">\ud83d\udcd8<\/span><div><strong>The Complete Guide to Silicon Wafer Polishing<\/strong><span>Comprehensive reference for all CMP topics \u2014 defects, slurry, process, and quality.<\/span><\/div><\/a>\n<a href=\"https:\/\/jeez-semicon.com\/ru\/blog\/CMP-Slurry-for-Silicon-Wafer-Types-Selection-Best-Practices\/\" target=\"_blank\" class=\"jp-rl\"><span class=\"jp-rl-icon\">\ud83d\udca7<\/span><div><strong>CMP Slurry for Silicon Wafer: Types, Selection &amp; Best Practices<\/strong><span>How slurry formulation \u2014 particle size distribution, pH stability, filtration \u2014 drives defect performance.<\/span><\/div><\/a>\n<a href=\"https:\/\/jeez-semicon.com\/ru\/blog\/How-to-Achieve-Sub-nm-Surface-Roughness-in-Silicon-Wafer-CMP\/\" target=\"_blank\" class=\"jp-rl\"><span class=\"jp-rl-icon\">\ud83d\udd2d<\/span><div><strong>How to Achieve Sub-nm Surface Roughness in Silicon Wafer CMP<\/strong><span>Process levers for achieving the sub-nm surface roughness that minimizes haze and LPDs.<\/span><\/div><\/a>\n<a href=\"https:\/\/jeez-semicon.com\/ru\/blog\/Post-CMP-Cleaning-for-Silicon-Wafers-Methods-and-Best-Practices\/\" target=\"_blank\" class=\"jp-rl\"><span class=\"jp-rl-icon\">\ud83e\uddea<\/span><div><strong>Post-CMP Cleaning for Silicon Wafers: Methods and Best Practices<\/strong><span>Post-CMP cleaning protocols that remove residual particles and achieve LPD specifications.<\/span><\/div><\/a>\n<\/div><\/div>\n<hr class=\"jp-hr\">\n<section id=\"faq\">\n<h2>\u0427\u0430\u0441\u0442\u043e \u0437\u0430\u0434\u0430\u0432\u0430\u0435\u043c\u044b\u0435 \u0432\u043e\u043f\u0440\u043e\u0441\u044b<\/h2>\n<div class=\"jp-faq\"><div class=\"jp-faq-item\"><div class=\"jp-faq-q\" onclick=\"jeezToggleFaq(this)\">What is the most common cause of scratch defects in silicon wafer CMP?<span class=\"jp-faq-icon\">+<\/span><\/div><div class=\"jp-faq-a\">The most common cause is large &#8216;killer particles&#8217; \u2014 abrasive agglomerates above ~500 nm in the polishing slurry \u2014 that become trapped between the polishing pad and the wafer surface and are dragged across the wafer during rotation. These agglomerates form when slurry pH drifts outside the colloidal stability range, when slurry ages past its shelf life, or when settled particles in delivery lines are flushed forward. Point-of-use filtration at 0.2\u20130.5 \u03bcm is the primary preventive control.<\/div><\/div>\n<div class=\"jp-faq-item\"><div class=\"jp-faq-q\" onclick=\"jeezToggleFaq(this)\">What are COPs and can they be eliminated entirely?<span class=\"jp-faq-icon\">+<\/span><\/div><div class=\"jp-faq-a\">COPs (Crystal-Originated Pits) are octahedral vacancy-cluster voids (50\u2013200 nm diameter) that form in the silicon crystal during Czochralski ingot growth. They are inherent to standard CZ silicon produced outside the &#8216;perfect silicon&#8217; growth window. They can be eliminated by using COP-free silicon (grown with controlled V\/G ratio and nitrogen doping), or by hydrogen annealing polished wafers at 1150\u20131200\u00b0C, which fills near-surface COPs by surface migration. For advanced node epi-substrate applications, COP-free silicon is routinely specified.<\/div><\/div>\n<div class=\"jp-faq-item\"><div class=\"jp-faq-q\" onclick=\"jeezToggleFaq(this)\">How is surface haze measured on polished silicon wafers?<span class=\"jp-faq-icon\">+<\/span><\/div><div class=\"jp-faq-a\">Haze is measured on laser-scanning surface inspection tools (e.g., KLA Surfscan SP3\/SP5) as the ratio of diffusely scattered light intensity to incident light intensity, expressed in parts per million (ppm). The measurement is spatially averaged over the wafer surface or reported as a map. Typical prime-grade 300mm silicon specification is haze below 0.03 ppm. AFM can characterize the spatial frequency components of roughness that contribute to haze, but laser-scanning inspection is the standard production measurement.<\/div><\/div>\n<div class=\"jp-faq-item\"><div class=\"jp-faq-q\" onclick=\"jeezToggleFaq(this)\">What is the difference between an LPD and a scratch on a silicon wafer inspection report?<span class=\"jp-faq-icon\">+<\/span><\/div><div class=\"jp-faq-a\">Both LPDs and scratches are detected by the same laser-scanning surface inspection tool, but they have different morphologies. LPDs are roughly circular events (particles, pits, mounds) with a diameter comparable to the detection threshold (35\u201360 nm up to a few hundred nm). Scratches are elongated events with a high aspect ratio (length >> width) and a characteristic arc shape determined by the relative motion of the polishing head over the pad. Modern inspection software automatically classifies events by shape signature, separating LPD counts from scratch counts.<\/div><\/div>\n<div class=\"jp-faq-item\"><div class=\"jp-faq-q\" onclick=\"jeezToggleFaq(this)\">How do I reduce haze on polished silicon wafers?<span class=\"jp-faq-icon\">+<\/span><\/div><div class=\"jp-faq-a\">Haze reduction requires optimization of both the CMP step and the post-CMP cleaning. For CMP: reduce slurry abrasive concentration and particle size; lower applied pressure; use a softer polishing pad; avoid over-polishing (which triggers isotropic chemical roughening). For cleaning: ensure complete removal of organic slurry additives with SC-1; verify rinse water purity; prevent watermark formation during drying. For a complete process guide, see our article on achieving sub-nm surface roughness.<\/div><\/div>\n<\/div>\n<\/section>\n<hr class=\"jp-hr\">\n<div class=\"jp-cta\"><h2>Reduce CMP Defects with JEEZ High-Purity Slurries<\/h2><p>JEEZ CMP slurries are engineered with tightly controlled D99 particle size distributions and industry-leading colloidal stability to minimize killer particles and deliver consistent LPD performance. Request a product data sheet or defect benchmarking evaluation.<\/p>\n<a href=\"https:\/\/jeez-semicon.com\/ru\/contact\/\" target=\"_blank\" class=\"jp-cta-btn\">Contact JEEZ Technical Team<\/a>\n<\/div>\n<\/div>\n<script type=\"application\/ld+json\">{\"@context\":\"https:\/\/schema.org\",\"@type\":\"FAQPage\",\"mainEntity\":[{\"@type\":\"Question\",\"name\":\"What is the most common cause of scratch defects in silicon wafer CMP?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"The most common cause is large 'killer particles' \u2014 abrasive agglomerates above ~500 nm in the polishing slurry \u2014 that become trapped between the polishing pad and the wafer surface and are dragged across the wafer during rotation. These agglomerates form when slurry pH drifts outside the colloidal stability range, when slurry ages past its shelf life, or when settled particles in delivery lines are flushed forward. Point-of-use filtration at 0.2\u20130.5 \u03bcm is the primary preventive control.\"}},{\"@type\":\"Question\",\"name\":\"What are COPs and can they be eliminated entirely?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"COPs (Crystal-Originated Pits) are octahedral vacancy-cluster voids (50\u2013200 nm diameter) that form in the silicon crystal during Czochralski ingot growth. They are inherent to standard CZ silicon produced outside the 'perfect silicon' growth window. They can be eliminated by using COP-free silicon (grown with controlled V\/G ratio and nitrogen doping), or by hydrogen annealing polished wafers at 1150\u20131200\u00b0C, which fills near-surface COPs by surface migration. For advanced node epi-substrate applications, COP-free silicon is routinely specified.\"}},{\"@type\":\"Question\",\"name\":\"How is surface haze measured on polished silicon wafers?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"Haze is measured on laser-scanning surface inspection tools (e.g., KLA Surfscan SP3\/SP5) as the ratio of diffusely scattered light intensity to incident light intensity, expressed in parts per million (ppm). The measurement is spatially averaged over the wafer surface or reported as a map. Typical prime-grade 300mm silicon specification is haze below 0.03 ppm. AFM can characterize the spatial frequency components of roughness that contribute to haze, but laser-scanning inspection is the standard production measurement.\"}},{\"@type\":\"Question\",\"name\":\"What is the difference between an LPD and a scratch on a silicon wafer inspection report?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"Both LPDs and scratches are detected by the same laser-scanning surface inspection tool, but they have different morphologies. LPDs are roughly circular events (particles, pits, mounds) with a diameter comparable to the detection threshold (35\u201360 nm up to a few hundred nm). Scratches are elongated events with a high aspect ratio (length >> width) and a characteristic arc shape determined by the relative motion of the polishing head over the pad. Modern inspection software automatically classifies events by shape signature, separating LPD counts from scratch counts.\"}},{\"@type\":\"Question\",\"name\":\"How do I reduce haze on polished silicon wafers?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"Haze reduction requires optimization of both the CMP step and the post-CMP cleaning. For CMP: reduce slurry abrasive concentration and particle size; lower applied pressure; use a softer polishing pad; avoid over-polishing (which triggers isotropic chemical roughening). For cleaning: ensure complete removal of organic slurry additives with SC-1; verify rinse water purity; prevent watermark formation during drying. For a complete process guide, see our article on achieving sub-nm surface roughness.\"}}]}<\/script>\n<script>\nfunction jeezToggleFaq(el){\n  var a=el.nextElementSibling,o=a.classList.contains('jp-open');\n  document.querySelectorAll('.jp-faq-a').forEach(function(x){x.classList.remove('jp-open')});\n  document.querySelectorAll('.jp-faq-q').forEach(function(x){x.classList.remove('jp-open')});\n  if(!o){a.classList.add('jp-open');el.classList.add('jp-open');}\n}\n<\/script>","protected":false},"excerpt":{"rendered":"<p>\u2190 Back to: The Complete Guide to Silicon Wafer Polishing JEEZ Semiconductor Materials &nbsp;\u00b7&nbsp; Technical Guide &nbsp;\u00b7&nbsp; Updated June 2026 A comprehensive reference for engineers managing defect yield in silicon  &#8230;<\/p>","protected":false},"author":1,"featured_media":2291,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[9,59],"tags":[],"class_list":["post-2289","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-blog","category-industry"],"acf":[],"_links":{"self":[{"href":"https:\/\/jeez-semicon.com\/ru\/wp-json\/wp\/v2\/posts\/2289","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/jeez-semicon.com\/ru\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/jeez-semicon.com\/ru\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/ru\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/ru\/wp-json\/wp\/v2\/comments?post=2289"}],"version-history":[{"count":2,"href":"https:\/\/jeez-semicon.com\/ru\/wp-json\/wp\/v2\/posts\/2289\/revisions"}],"predecessor-version":[{"id":2292,"href":"https:\/\/jeez-semicon.com\/ru\/wp-json\/wp\/v2\/posts\/2289\/revisions\/2292"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/ru\/wp-json\/wp\/v2\/media\/2291"}],"wp:attachment":[{"href":"https:\/\/jeez-semicon.com\/ru\/wp-json\/wp\/v2\/media?parent=2289"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/jeez-semicon.com\/ru\/wp-json\/wp\/v2\/categories?post=2289"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/jeez-semicon.com\/ru\/wp-json\/wp\/v2\/tags?post=2289"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}