ILD Oxide CMP Slurry: TEOS Planarization Process & Slurry Selection Guide
Inter-layer dielectric (ILD) oxide CMP is the single highest-volume CMP application in semiconductor manufacturing. Understanding the process — its target films, slurry chemistry, uniformity requirements, and endpoint strategy — is foundational for any CMP engineer working in BEOL process integration. This guide covers everything you need to know about ILD oxide CMP slurry selection and process control. For a broader view of all oxide CMP slurry types and applications, see our Oxide CMP Slurry: Complete Technical Guide.
What Is ILD Oxide CMP?
Inter-layer dielectric (ILD) CMP is the planarization step applied to SiO2 dielectric films deposited between successive metal interconnect levels in back-end-of-line (BEOL) semiconductor processing. After each metal level — contact, M1, M2, and so on — a dielectric layer is deposited to electrically isolate the metal from the next level above. This deposited oxide inherits the topography of the metal features below it, creating height variations that, if left unaddressed, would propagate upward through the metal stack, progressively degrading the focal depth budget of each successive lithography step and increasing overlay error.
ILD CMP planarizes this oxide back to a globally flat surface, resetting the topographic baseline before the next metal level is patterned. It is the step that makes multilayer interconnect fabrication manufacturable — without it, the combination of depth-of-focus limitations and topography accumulation would make lithography impractical beyond two or three metal levels. A modern high-performance logic chip at the 3 nm node may have fifteen or more metal levels, each requiring at least one ILD CMP step.
Unlike STI CMP — which polishes to a nitride stop layer — ILD CMP operates with no hard stop layer. The process runs for a specified time or until a target thickness is confirmed by in-situ optical measurement. This makes uniformity control the defining process challenge: variations in removal rate across the wafer directly translate to final thickness non-uniformity, which affects the via resistance and capacitance of every interconnect on the die.
Target Films: TEOS, PECVD & HDP-CVD Oxide
Not all oxide films polished by ILD CMP are identical. The specific film type — its deposition method, density, stress state, and step coverage — affects how it polishes and what slurry specifications are required for consistent process performance.
PECVD TEOS Oxide
Plasma-enhanced CVD oxide deposited from tetraethyl orthosilicate (TEOS) precursors is the most common ILD film in BEOL processing. TEOS PECVD oxide is deposited at 350–450°C and produces a conformal, slightly tensile film with density close to thermal oxide (~2.2 g/cm3). It conforms to the topography of underlying metal features, creating the characteristic “bread-loaf” topography that ILD CMP must planarize. Standard ILD colloidal silica slurry at pH 10–11 polishes TEOS oxide at 1,000–2,500 Å/min under standard process conditions.
HDP-CVD Oxide
High-density plasma CVD oxide is used for gap-fill applications where narrow-pitch metal lines require void-free dielectric filling. HDP-CVD oxide is denser than PECVD TEOS (~2.3 g/cm3) and more compressively stressed. It polishes slightly slower than TEOS PECVD under identical slurry conditions — a process engineer qualifying a new slurry on HDP-CVD oxide must therefore characterize MRR separately from TEOS film data.
Doped Oxide Films (BPSG, PSG, FSG)
Borophosphosilicate glass (BPSG) and phosphosilicate glass (PSG) are used in pre-metal dielectric (PMD) applications and polish significantly faster than undoped TEOS oxide due to the hygroscopic, mechanically weaker nature of the doped matrix. Fluorosilicate glass (FSG) — a low-k dielectric used at 130–90 nm nodes — polishes similarly to TEOS oxide but with somewhat higher sensitivity to abrasive-induced surface damage. Each doped oxide variant requires independent MRR characterization for slurry qualification.
ILD CMP Process Flow & Integration
A typical BEOL ILD CMP process flow on a 300 mm fab tool (Applied Materials Reflexion or Ebara FREX) consists of several steps that together achieve the target oxide removal with acceptable uniformity and defectivity:
- Incoming oxide thickness measurement: Pre-CMP film thickness is measured by optical profilometry at 49–121 sites across the wafer. This baseline measurement, combined with the target post-CMP thickness, defines the required removal amount and the maximum allowable polish time.
- Bulk removal step: The primary polish step runs at 2–4 psi downforce, 80–100 RPM platen/head speed, with colloidal silica ILD slurry flowing at 200–250 mL/min. This step removes the bulk of the required oxide — typically 500–1,500 Å — at MRR of 1,500–2,500 Å/min.
- Endpoint detection: In-situ optical interferometry continuously monitors remaining oxide thickness. When the target thickness is reached (or predicted within the next few seconds of polishing based on current MRR), the endpoint system signals process termination.
- Over-polish step (optional): A brief low-pressure over-polish step at 1–1.5 psi with reduced head speed is sometimes added to improve uniformity after bulk removal without significantly altering mean remaining thickness.
- Post-CMP rinse: The wafer is rinsed on-platen with DI water before unloading to prevent slurry drying on the wafer surface.
- Post-CMP cleaning: The wafer proceeds to a dedicated cleaning station for particle removal and surface preparation before the next deposition step. For ILD colloidal silica processes, SC-1 (NH4OH:H2O2:H2O) clean with PVA brush scrubbing is standard.
Total ILD CMP cycle time (including loading, polish, rinse, and unloading) is typically 90–180 seconds per wafer, making it compatible with high-throughput production scheduling on 4-head tools processing 50–70 wafers per hour.
ILD Oxide Slurry Selection: Key Specifications
When evaluating or qualifying an ILD oxide CMP slurry, the following specifications drive process performance and must be independently measured on your specific tool platform and pad combination — not accepted from supplier datasheets alone:
| Specification | Typical Target (ILD, 300 mm) | 为何重要 |
|---|---|---|
| SiO2 MRR | 1,500–2,500 Å/min | Determines throughput; must be stable across pad lifetime |
| MRR Stability (lot-to-lot) | ±5% from target | Lot-to-lot drift shifts polish time and final thickness |
| WIWNU (1σ) | <3% at standard conditions | Directly determines interconnect thickness uniformity |
| 颗粒大小（D50） | 60–100 nm | Controls removal rate and surface roughness balance |
| Particle Size (D99) | <300 nm | Large particles are the primary cause of micro-scratches |
| pH (as-supplied) | 10.0–11.2 | Must match process window; drift causes MRR shift |
| Abrasive Concentration | 5–15 wt% | Higher concentration increases MRR and cost per liter |
| Surface Roughness (post-CMP) | Ra <0.15 nm | Roughness affects via resistance and adhesion in damascene |
| 划痕密度 | <0.05/cm² | Scratches propagate into next layer as yield-limiting defects |
| Shelf Life | 6–12 months | Shorter shelf life creates waste and inconsistency risk |
ILD slurry for advanced-node BEOL applications must also be evaluated for compatibility with exposed low-k dielectric sidewalls. At 14 nm and below, ultra-low-k (ULK) porous dielectrics with k < 2.5 are present during ILD CMP, and abrasive contact or aggressive pH chemistry can infiltrate pore networks and increase the effective dielectric constant. For low-k-compatible slurry selection, also refer to our guide on Post-CMP Cleaning for Oxide Slurry Processes, which covers clean chemistry compatibility with ULK films.
Process Parameters & Control
ILD oxide CMP process stability depends on controlling several interdependent hardware and consumable parameters. The most critical for production stability are:
Carrier Head Zone Pressure
Multi-zone carrier heads (typically 3–7 independent pressure zones) are the primary hardware lever for within-wafer uniformity correction. Zone 1 (center) and zone 6–7 (edge) typically require different pressures to compensate for pad wear profiles and edge-fast or edge-slow polishing tendencies. Zone pressure optimization is tool-specific and must be recharacterized after pad changes and during pad break-in.
Slurry pH Monitoring
Slurry pH on the polishing pad surface can drift from the as-supplied value due to dilution from backside rinse water, absorbed CO2 from ambient air, and thermal effects. pH drift of just ±0.5 units from the ILD process optimum (typically pH 10.5–11) causes measurable MRR shift and WIWNU widening. Fabs running advanced-node ILD CMP should consider point-of-use pH monitoring with alarm thresholds as part of their statistical process control (SPC) system.
Pad Break-In and Pad Lifetime Management
A freshly changed polishing pad — even after the standard conditioning break-in procedure — typically delivers 10–20% higher MRR than a pad at its steady-state operating condition. Polishing recipes must account for this by adjusting polish time or downforce during the break-in period. For process details and parameter tables, see our companion article: Oxide CMP Process Parameters: MRR, Within-Wafer Uniformity & Endpoint Detection Guide.
WIWNU & Pattern Density Effects
Within-wafer non-uniformity (WIWNU) is the primary yield-limiting process metric for ILD oxide CMP. It has two principal components: intrinsic WIWNU (from tool hardware asymmetry, pad wear distribution, and slurry delivery non-uniformity) and pattern-density-induced WIWNU (from differences in polishing rate between high-density and low-density die regions).
Pattern density effects arise because the local polishing rate at any point on the wafer depends not just on applied pressure and velocity (as Preston’s equation predicts) but on the density of raised oxide features in the local neighborhood. Raised features (above the average surface level) contact the pad directly and polish faster; recessed regions are shielded by the pad’s mechanical compliance and polish slower. As a result, high-density metal regions with frequent raised oxide features polish faster than low-density regions, creating systematic within-die and die-to-die thickness variation even with a perfectly uniform carrier head pressure.
Pattern-density-induced WIWNU is managed through two complementary strategies:
- Design-level mitigation: Inserting dummy metal fill features in sparse areas to equalize pattern density across the die; this is the most effective long-term approach and is standard in advanced-node BEOL design rules.
- Process-level mitigation: Adjusting slurry formulation selectivity (softer pads, lower-pressure recipes) to reduce the difference in polishing rate between dense and sparse areas; this has limited effectiveness and cannot fully replace design mitigation at advanced nodes.
Troubleshooting Common ILD CMP Issues
Any sudden MRR shift (>10% from control chart mean) in ILD CMP should trigger immediate investigation before the affected wafer lot is processed further. Common root causes are addressable if caught early; they become yield excursions if allowed to propagate through subsequent layers.
MRR decay mid-pad-life: The most common ILD CMP stability issue. Typically caused by pad glazing (reduction of micro-texture due to insufficient conditioning). Verify pad conditioner disk condition and downforce; increase conditioning frequency if MRR trend shows progressive decay.
Edge-fast polishing: Oxide removal rate significantly higher at wafer edge than center. Most commonly caused by carrier head retaining ring pressure imbalance or slurry drainage toward the wafer edge. Increase center-zone carrier head pressure and verify retaining ring conditioning.
Elevated scratch density: Sudden increase in post-CMP scratch counts. Immediately check point-of-use filter integrity (clogged filter bypasses can allow unfiltered slurry with large particle aggregates to reach the pad). Also check pad conditioning disk for embedded debris. Inspect slurry supply line for signs of dried slurry or contamination.
Lot-to-lot MRR variability: If MRR varies more than ±5% between slurry lots, request lot certificates from your supplier covering D50, D99, pH, and abrasive concentration. Incoming inspection with a reference test wafer is the standard practice for lot acceptance at advanced nodes. For defect management details, see: Oxide CMP Slurry Defects: Root Causes, Detection Methods & Yield Impact.
Frequently Asked Questions: ILD Oxide CMP Slurry
What type of slurry is used for ILD oxide CMP?
ILD oxide CMP uses colloidal silica (amorphous SiO2) abrasive slurries at pH 10–11, adjusted with KOH or NH4OH. Typical abrasive concentrations range from 5 to 15 wt%. These slurries deliver oxide MRR of 1,000–3,000 Å/min and are preferred for ILD applications due to their low defectivity, excellent surface finish, and simple post-CMP cleaning requirements with standard SC-1 chemistry.
Why does ILD CMP not use a stop layer?
Unlike STI CMP (which stops on Si3N4), ILD CMP polishes a blanket SiO2 film with no underlying stop material — because the ILD must be reduced to a precise remaining thickness (not fully removed). This means process termination is controlled by time, in-situ optical interferometry measuring real-time oxide thickness, or a combination of both. The absence of a hard stop layer makes ILD the most uniformity-sensitive CMP application in BEOL processing.
What causes WIWNU in ILD oxide CMP?
WIWNU in ILD CMP has two root causes: tool hardware non-uniformity (carrier head zone pressure distribution, pad wear profile, slurry delivery asymmetry) and pattern-density-induced non-uniformity (raised features in dense circuit areas polish faster than recessed areas in sparse regions). Advanced-node BEOL processes manage pattern-density effects through dummy metal fill at design level and through multi-zone carrier head pressure optimization at process level.
How often should ILD CMP slurry be qualified lot-to-lot?
For advanced-node BEOL applications, every incoming slurry lot should be tested against a reference test wafer measuring MRR, WIWNU, and scratch density before release for production use. In practice, fabs on SPC programs with established slurry suppliers may accept lots based on supplier certificate of analysis (CoA) data (D50, D99, pH, abrasive concentration) with periodic reference wafer testing, but full lot-by-lot testing is recommended during the first six months of a new supplier qualification.
What is the difference between KOH-based and NH₄OH-based ILD slurry?
Both KOH and NH4OH-based formulations deliver similar oxide MRR and WIWNU performance. The critical difference is metal ion contamination: KOH introduces potassium ions (K+) into the slurry, which can contaminate CMOS gate dielectric regions if present at sufficient concentration. NH4OH-based formulations are preferred for front-end-adjacent BEOL steps or any application where metal ion control is critical. KOH formulations offer superior pH stability and are preferred for pure BEOL steps where K+ contamination risk is negligible.
