Planarization Applications in IC Fabrication: STI, ILD, Cu Damascene & W Plug

01CMP in the IC Process Flow

A modern logic chip at the 2 nm node (June 2026) requires more than 25 individual CMP steps distributed across the front-end-of-line (FEOL) device formation and the back-end-of-line (BEOL) interconnect stack. Each CMP step targets a specific film system, achieves a specific planarization objective, and must meet a specific set of uniformity and defect specifications. Understanding each application — its purpose, process flow context, consumable requirements, and critical defect modes — is essential for anyone involved in advanced semiconductor process integration.

02STI CMP: Shallow Trench Isolation

STI CMP Process Details

Film Stack and Target

The incoming film stack for STI CMP is: Silicon (substrate) / Si₃N₄ (100–200 nm, hard mask) / Pad oxide SiO₂ (5–10 nm) / HDP-CVD SiO₂ (overburden, 300–600 nm above the Si₃N₄ surface). The CMP target is to remove the HDP-CVD oxide overburden and stop precisely on the Si₃N₄ hard mask, with WIWNU in the remaining nitride thickness of ±5–10 nm across the 300 mm wafer.

Slurry Requirements: High Selectivity Ceria

Standard STI CMP uses a fumed ceria (CeO₂) slurry at pH 4–7 with optional polymeric selectivity additives (polyacrylic acid). Target SiO₂:Si₃N₄ selectivity is 50:1 to >100:1. This high selectivity ensures that the polishing stops effectively on the nitride stop layer without consuming it — preserving the full nitride thickness for subsequent processing. Colloidal silica slurries (selectivity 3:1 to 10:1) are insufficient for STI CMP at sub-65 nm nodes where the nitride thickness budget is tight.

Critical Defect Modes

• Dishing: Over-polishing of wide oxide isolation regions (field oxide in sparse areas) below the nitride surface level. Controlled by optimizing over-polish time and selectivity.
• Erosion: Pattern-density-dependent thinning of nitride in dense STI arrays, causing the local oxide height to vary across the chip as a function of active area density. Managed by layout-level dummy fill rules and slurry selectivity optimization.
• Nitride loss: If selectivity drops below specification (e.g., due to slurry pH drift), excessive nitride removal can expose the pad oxide and even the silicon below, causing junction leakage or gate oxide quality degradation.

Impact on Device Performance

The remaining oxide height in STI trenches after CMP — the STI recess — directly affects transistor behavior. In FinFET devices, STI CMP determines the effective fin height above the isolation oxide, which controls transistor on-current (I_on) and threshold voltage. A WIWNU of 2 nm in fin height translates directly into 2 nm of drive current variation across the die — a critical parametric yield concern at advanced nodes.

03ILD CMP: Interlayer Dielectric Planarization

ILD Materials and Their CMP Challenges

The dielectric material used for ILD has evolved substantially as the semiconductor industry has driven toward lower dielectric constants (k) to reduce interconnect RC delay:

For ultra-low-k (ULK) porous dielectric ILD CMP, process conditions must be significantly modified compared to standard oxide CMP: reduced down-force (1–2 psi vs. 3–6 psi for dense oxide), compliant two-layer pad stack with soft top layer, surfactant-rich slurry chemistry to minimize mechanical stress at the dielectric surface, and strict avoidance of thermal or mechanical cycling that could collapse the porous structure. Delamination of ULK films at the pad interface is the primary yield-loss concern in ULK ILD CMP.

ILD CMP Uniformity Specifications

Post-CMP ILD thickness WIWNU is typically specified at ±5–10 nm (absolute) or <2% (relative to mean thickness) for standard oxide ILD, and ±3–5 nm for advanced ULK ILD where via depth variation directly impacts via resistance and RC performance. These specifications are enforced by in-line post-CMP reflectometry measurement and fed back into run-to-run control systems that adjust the next lot’s polishing time or pressure profile to compensate for drift.

04Tungsten Plug CMP

W CMP Process Flow

1. PMD deposition and planarization: CVD oxide PMD is deposited over the transistors and silicide contacts, then planarized by CMP. The planarized PMD surface is the starting surface for contact hole lithography and etch.
2. Contact hole etch: Anisotropic RIE etches contact holes through the PMD to the silicide contact. Hole depth uniformity is critical — a non-planar PMD causes depth variation that degrades tungsten fill quality.
3. TiN/Ti barrier deposition: 5–20 nm TiN or Ti/TiN liner deposited by PVD or ALD covers the contact hole sidewalls and bottom, providing adhesion and a diffusion barrier for the W fill.
4. CVD-W fill: Tungsten CVD fills the contact holes and deposits 200–400 nm overburden across the full wafer surface.
5. W CMP: Fumed alumina slurry (pH 2–4) with H₂O₂ removes the W overburden (step 1), transitions to barrier clearing (step 2, endpoint-controlled), and stops on the SiO₂ PMD surface.

Critical Defect Modes in W CMP

• Plug dishing: Over-polishing of W plugs below the PMD surface level, increasing contact resistance. Controlled by minimizing over-polish time and selecting slurry chemistry with moderate W:SiO₂ selectivity.
• Tungsten recess (seam voids): CVD-W deposition in high-aspect-ratio contacts sometimes leaves a seam void at the contact center. If CMP dishing exposes this void, the contact resistance increases sharply. Minimized by optimizing W nucleation chemistry and CVD conditions before CMP.
• Barrier metal residue: Incompletely cleared TiN/TiW on the PMD surface creates conductive shorts between adjacent contacts. Addressed by extending the clearing step duration or increasing the barrier removal rate through slurry pH optimization.

05Copper Damascene CMP

The Dual-Damascene Structure

Dual-damascene processing integrates the via (vertical) and trench (horizontal) metal levels into a single patterning and fill sequence. The ILD is patterned with both via holes and metal trenches in one combined lithography-and-etch sequence, then copper fills both simultaneously by electrochemical deposition (ECD). CMP removes the copper above the trench top and the barrier metal, leaving copper-filled trenches (the metal lines) and vias in a planar low-k dielectric surface. This dual-damascene approach, introduced with copper CMP at the 130 nm node, reduces process complexity compared to single-damascene (separate via and trench fill steps) while producing superior interconnect resistance and yield.

Two-Step Cu CMP in Detail

步骤 1：大量除铜

High-pressure, high-MRR polishing (typically 2–4 psi, 300–600 nm/min Cu MRR) removes the bulk copper overburden above the barrier layer. Colloidal silica slurry at pH 4–6 with H₂O₂ oxidizer (added at point-of-use). The endpoint for Step 1 is detected when the barrier metal is first exposed across the majority of the wafer — typically identified by a friction (motor current) change or a change in the optical EPD signal. Step 1 is stopped slightly before complete barrier exposure to preserve a thin copper over-layer (~50–100 nm) above the barrier, preventing copper from being polished over areas where the barrier is already exposed while the barrier in other areas is not yet cleared.

Step 2: Barrier Clearing and Final Planarization

Gentler polishing conditions (1–2 psi, reduced slurry flow) with a barrier-selective slurry formulation removes the remaining copper overburden and the TaN/Ta barrier layer, stopping on the low-k dielectric ILD. Higher BTA concentration (0.05–0.1 wt%) suppresses copper dissolution and dishing during this step. The Step 2 endpoint is the full exposure of the dielectric surface across the entire wafer — confirmed by optical EPD signal stabilization. Post-Step 2, the wafer surface should show copper lines at (or within 3–5 nm of) the dielectric level, with Ra <0.5 nm.

Dishing and Erosion: The Dominant Defect Modes

06Replacement Metal Gate (RMG) CMP

Replacement Metal Gate (RMG) — also called gate-last or high-k-last process — is the gate formation technique used in all leading-edge logic processes from 22 nm FinFET through current 2 nm GAA nanosheet. The RMG flow requires two CMP steps:

1. Dummy gate planarization CMP: After source/drain formation and silicide annealing, a thick ILD oxide is deposited over the dummy polysilicon gate. CMP planarizes this ILD to expose the top of the dummy gate — the reference surface from which the gate is removed and replaced. WIWNU in the remaining ILD thickness directly determines dummy gate height uniformity, which determines the work function consistency of the replacement gate across the die.
2. Metal gate CMP: After the dummy gate is removed (wet etch) and the high-k/metal gate stack (HfO₂/TiN/TaN/W or Co fill) is deposited and etched back, a final CMP step planarizes the gate metal level, leaving the high-k/metal gate stack flush with the surrounding ILD surface. Gate height WIWNU after this CMP directly impacts threshold voltage (V_T) distribution across the wafer — a key performance specification for high-speed logic.

07Through-Silicon Via (TSV) Reveal CMP

Through-Silicon Vias (TSVs) connect die vertically in 3D stacked memory (HBM, 3D DRAM) and logic-on-logic integration schemes. TSVs are typically formed by “via-first” or “via-middle” approaches — etching and copper-filling via structures before or during the device process — and are then revealed on the wafer back-side by grinding and CMP to expose the copper via tips after wafer thinning.

TSV reveal CMP removes the back-side silicon from the thinned wafer (~50–100 µm silicon remaining after grinding) down to the copper TSV tips, then polishes the silicon surface to expose the vias uniformly. The critical specification is the planarity of the silicon back-side relative to the copper TSV tops: excessive silicon over the TSVs (incomplete reveal) blocks electrical contact; excessive removal (over-polish) causes copper dishing in the via and mechanical stress concentration at the via perimeter that risks via cracking during subsequent back-side processing and packaging.

08Hybrid Bonding Planarization

Hybrid bonding is the most demanding CMP application in terms of surface finish requirements. In hybrid bonding for 3D IC integration (die-to-wafer or wafer-to-wafer), two bonding surfaces — each containing copper pads embedded in SiO₂ or SiCN dielectric — are brought into direct contact and bonded simultaneously at the Cu–Cu and dielectric–dielectric interfaces without any adhesive, solder, or underfill.

For this direct bonding to work at the atomic scale, both surfaces must be prepared by CMP to meet simultaneously: Ra below 0.3 nm (to enable spontaneous SiO₂-to-SiO₂ oxide fusion at room temperature); copper pad step height (recessed or protruding relative to the dielectric) of no more than ±2–3 nm; and particle density below 0.01 defects/cm² (any particle at the bond interface creates a void that prevents local bonding and reduces bonding yield). These specifications are at the absolute limit of what CMP can achieve, requiring fixed abrasive or ultra-soft pad systems, ultra-dilute polishing conditions, and extensive post-CMP surface characterization.

09Module Summary Table

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