Poreless CMP Pads vs. Porous Structure: Technology Comparison

发布于: 2026年4月7日查看次数161
Back to CMP Polishing Pads: The Complete Guide
Jizhi Electronic Technology — Technology Series

A detailed comparison of poreless and conventional porous CMP polishing pad architectures — examining slurry transport, defect performance, MRR consistency, process control requirements, and total cost of ownership for advanced node and specialty semiconductor applications.

📅 April 2026 ⏱ 13 min read 🏭 Jizhi Electronic Technology Co., Ltd.
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Written by Jizhi Electronic Technology Co., Ltd. — CMP pad manufacturer with both porous and poreless pad series in active production. Poreless pad qualification data reflects our current April 2026 customer qualification status.

The shift from conventional porous polyurethane pads to poreless pad architectures is the most significant structural change in CMP pad technology since the introduction of machined groove patterns in the mid-1990s. Poreless pads — with near-zero internal pore volume — eliminate several of the most fundamental performance limitations of conventional pads, particularly lot-to-lot Kp variation and pad-borne polymer debris generation. But they introduce new process control demands that must be understood before a transition is feasible.

This guide provides the rigorous, side-by-side comparison that process engineers need to evaluate whether poreless pads are the right choice for a specific CMP application. For background on pad material types more broadly, see: CMP Pad Materials: Polyurethane vs Other Options.

<3%
Kp coefficient of variation (lot-to-lot) achievable with poreless pads
~60%
Reduction in pad-borne polymer debris defects vs. conventional porous pads
2–3×
Cost premium of poreless pads vs. equivalent conventional pads (unit price)
<1%
Pore volume fraction in true poreless pads (vs. 20–30% in conventional porous PU)

1. Architectural Differences Explained

In a conventional porous CMP pad, hollow microspheres dispersed throughout the polyurethane matrix create a network of closed-cell micro-pores (20–50 µm diameter, 20–30% volume fraction) that serve as slurry reservoirs. When the pad surface is conditioned, the diamond dresser exposes cross-sections of these pores at the surface, creating an array of micro-cups that absorb and release slurry during polishing. This pore network is the primary slurry transport mechanism within the pad bulk, supplementing the groove-based macro-transport.

A poreless pad eliminates this internal pore network entirely. The polyurethane is cast from a pore-free formulation (no microspheres), producing a dense, homogeneous polymer matrix with pore volume fraction below 1–2%. The only slurry transport mechanism available is the groove network machined into the pad surface. From a materials science perspective, poreless pads are closer to a solid engineering polymer than to a foam — their mechanical behavior is more predictable, more consistent, and more thermally stable.

2. Slurry Transport: Pore vs. Groove

🔵 Porous Pad — Dual Transport

  • Groove channels: macro-transport, slurry delivery from pad edge to contact zone
  • Pore reservoir: micro-transport, continuous slurry replenishment between groove passes
  • Pore-derived slurry provides a buffer against transient slurry flow interruptions
  • Tolerant of slurry flow rate variations of ±20% with minimal MRR impact
  • Pore saturation time (1–3 minutes of pre-wet) required before polishing
  • Slurry utilization lower — significant volume absorbed into pores and not used at interface

⚡ Poreless Pad — Groove-Only Transport

  • Groove channels: sole slurry transport mechanism
  • No internal reservoir — slurry at interface is purely groove-delivered, not pad-stored
  • Sensitive to slurry flow interruption — MRR drops within seconds of flow stop
  • Requires slurry flow rate variation <±10% for stable MRR
  • No pre-wet saturation required — ready to polish immediately after installation
  • Higher slurry utilization — all delivered slurry reaches the interface directly via grooves

3. Defect Performance Comparison

The most compelling advantage of poreless pads is defect performance, particularly for polymer debris-related particle contamination. The comparison is stark:

缺陷类型Porous Pad PerformancePoreless Pad PerformanceAdvantage
Pad polymer debris (particles)Moderate — pore-wall fragments shed during conditioning and polishingVery low — no pore walls to fracture; dense matrix sheds minimal debrisPoreless: ~60% fewer pad-borne particles
微小划痕Dependent on conditioning — asperity distribution more variable lot-to-lotLower variability in asperity distribution — more consistent scratch performancePoreless: more predictable scratch baseline
Slurry particle residuesModerate — pore-resident slurry can release partially-spent particlesLower — all slurry is fresh from groove channels; no stale pore-resident particlesPoreless: fewer slurry residue defects
MRR-driven non-uniformityModerate — pore density variation across pad radius creates MRR radial variationVery low — groove-only transport has more predictable radial uniformityPoreless: lower radial MRR variation
Pitting from chemical stagnationPresent — pore-resident spent slurry can create chemical hotspotsEliminated — no stagnant slurry in poresPoreless: no pore-related pitting

4. MRR and Lot-to-Lot Consistency

The second major advantage of poreless pads is MRR lot-to-lot consistency — the ability to deliver the same removal rate from one pad lot to the next without recipe adjustment. This is where the pore structure of conventional pads creates a fundamental limitation: pore size distribution (mean diameter and coefficient of variation) varies between production lots despite tight manufacturing controls, causing Kp to shift by 5–15% between lots. This variation requires process engineers to perform removal rate verification on new pad lots and adjust recipe pressure accordingly.

Poreless pads, with no pore structure to vary, deliver Kp values with lot-to-lot CV below 3% — compared to 8–15% CV for conventional porous pads. In practical terms: a process running on a poreless pad in an APC (advanced process control) framework can use a fixed recipe without per-lot verification, reducing engineering overhead and the risk of yield excursion from a new pad lot that was not properly characterized before production release.

5. Process Control Requirements — The Poreless Challenge

The performance benefits of poreless pads come at the cost of significantly tighter process control requirements. These requirements must be evaluated honestly before committing to a poreless pad transition:

⚠️
Slurry Flow Rate Stability Is Non-Negotiable with Poreless Pads The pore reservoir in a conventional pad buffers against slurry flow variations of ±20% with minimal MRR impact — the stored slurry compensates for the supply interruption. A poreless pad has no buffer. A 15-second slurry flow interruption on a poreless pad will cause a measurable MRR step-down that may leave a wafer under-polished. Before transitioning to poreless pads, verify that your slurry delivery system can maintain flow rate variation below ±8% and has zero-interruption failsafe (continuous re-circulation loop, dual pump configuration, or equivalent).
  • Slurry flow rate stability: ±8% or better — no interruptions; continuous recirculation mandatory
  • Groove design: finer pitch mandatory — poreless pads require 1.5–2.5 mm groove pitch vs. 2.5–4.0 mm typical for porous pads, to compensate for the absent pore micro-transport
  • Conditioning protocol: gentler — poreless pads respond more acutely to conditioner down-force changes; over-conditioning raises Ra non-uniformly and creates scratch-prone zones
  • Pre-polish prep: simplified — no pore saturation pre-wet needed; pad is ready to polish immediately after installation and rinse

6. Conditioning Behavior: Key Differences

Conditioning behavior differs meaningfully between porous and poreless pads in three ways that process engineers must account for when transitioning:

  • Break-in time: Poreless pads have no skin layer to remove (the skin is the pad — it is already dense). Break-in is shorter (20–40 dummy wafers vs. 50–100 for porous pads) and MRR reaches stable state faster. However, the first few wafers after installation show slightly elevated debris as machining residue from groove cutting is flushed out.
  • Conditioning debris: Conditioning generates less polymer debris from poreless pads because there are no pore walls to fracture. However, the debris that is generated (polymer swarf from surface abrasion) is more consistent in particle size — it does not include the irregular pore-wall fragment shapes that make porous pad debris particularly prone to embedding in soft film surfaces.
  • Ra evolution with conditioning: Poreless pads develop lower steady-state Ra than equivalent-hardness porous pads under the same conditioning protocol, because they lack the pore-wall asperity enhancement that porous pads develop. This lower Ra means slightly lower MRR — but also slightly lower scratch generation. Conditioning intensity must be calibrated independently for poreless pads rather than carried over from a porous pad protocol.

7. Total Cost of Ownership Analysis

The unit price premium of poreless pads (2–3× higher) is the most immediate objection to their adoption. A complete TCO analysis often tells a different story:

Cost FactorPorous PadPoreless PadDirection of Advantage
Unit pad price (index)1.0×2.0–3.0×Porous
Lot qualification cost (engineering labor per lot)High — MRR verification and recipe adjustment per new lotLow — fixed recipe; APC compatiblePoreless
Yield loss from defect excursions (particle, scratch)Higher defect rate — more frequent excursions from pore debrisLower defect rate — especially for advanced node CMP stepsPoreless (if at advanced node)
Rework wafer costHigher at advanced node — each defective wafer costs $1,000–$10,000+Lower — fewer rework eventsPoreless (at advanced node)
Slurry consumptionHigher — significant slurry volume absorbed into poresLower — groove-only transport; higher slurry utilization efficiencyPoreless
APC recipe complexityHigher — lot-specific Kp adjustment requiredLower — fixed recipe possible with tight Kp tolerancePoreless

For high-value advanced node processes (7 nm and below) where wafer yield is critically important, poreless pads consistently show positive TCO versus conventional porous pads despite the unit price premium. For mature-node or research applications where defect density is more relaxed and pad cost is a primary concern, conventional porous pads remain the economically rational choice.

8. When to Use Each Architecture

✅ Use Conventional Porous Pads When:

  • Process node ≥14 nm where defect density targets are achievable with porous pads
  • Slurry delivery system cannot guarantee <±8% flow rate stability
  • Research or low-volume production where pad cost per wafer dominates TCO
  • Mature-node oxide CMP where defect requirements are relaxed
  • SiC substrate intermediate polishing (Stage 2) where MRR is more important than defect density
  • Process requires tolerance to occasional slurry flow interruptions

⚡ Use Poreless Pads When:

  • Process node ≤7 nm — defect density targets below 10 particles/wafer
  • EUV-layer dielectric CMP — any particle that prints in EUV exposure is catastrophic
  • APC framework requires per-lot recipe stability without Kp adjustment
  • Cu BEOL defect excursions are driven by polymer debris, confirmed by EDX
  • 3D NAND step-height CMP requiring ultra-consistent planarization from lot to lot
  • Slurry delivery system already optimized for high-flow-rate stability

9. Frequently Asked Questions

Are poreless pads compatible with standard CMP tools without modification?
Yes — poreless pads fit on standard CMP tools without hardware modification. The platen, carrier head, and conditioner arm are compatible. The required changes are process-side: finer-pitch groove specification (ordered from supplier), slurry flow rate stability verification and upgrading if necessary, and re-characterization of conditioning protocol. Poreless pads are available in the same form factor and sizes as conventional pads for all major tool platforms including Applied Materials Reflexion GT, Ebara FREX, and SKC/Kctech tools.
Can poreless pads be used for SiC CMP?
Yes, and they are increasingly preferred for SiC final CMP (Stage 3 — epitaxial-ready surface). The ultra-low defect density of poreless pads aligns well with the stringent surface requirements for SiC power device fabrication. The main consideration for SiC is that poreless pads require even more stable slurry delivery than in silicon CMP — SiC slurry (diamond or ceria + oxidizer) has a higher tendency to agglomerate under stagnant conditions, and the absence of pore buffering makes poreless pads more vulnerable to flow interruption on SiC. Ensure slurry recirculation is maintained at all times.
How do you verify that a pad is genuinely poreless vs. just very low-porosity?
Verification methods in order of rigor: (1) SEM cross-section — true poreless pads show a homogeneous dense polymer matrix with no visible pores at 500–1000× magnification; conventional pads show a clearly porous structure. (2) Mercury intrusion porosimetry — measures total pore volume fraction; true poreless pads show <2% pore volume. (3) Water absorption test — immerse pad section in DI water for 24 hours; porous pads absorb 5–15% of their mass; poreless pads absorb <1%. Always request SEM cross-section images and porosimetry data from your pad supplier before accepting a “poreless” claim.
Does Jizhi supply poreless CMP pads?
Yes. Jizhi’s poreless pad series is currently in active qualification at multiple customer fabs and is available for evaluation sampling as of April 2026. Our poreless pads use a polycarbonate-backbone PU matrix cast without microspheres, delivering pore volume fraction below 1.5% and lot-to-lot Kp CV below 3%. Available groove patterns include concentric (fine pitch 1.5–2.0 mm), XY grid, and spiral. Please contact our application engineering team to request evaluation samples and process characterization data.

Porous or Poreless — Jizhi Has Both

Jizhi Electronic Technology supplies conventional porous hard PU pads, soft subpads, and our advanced poreless pad series — with full characterization data and application engineering support to help you choose the right architecture for your process.

Browse CMP Polishing Pads Request Poreless Pad Samples

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