{"id":1661,"date":"2026-03-13T09:16:39","date_gmt":"2026-03-13T01:16:39","guid":{"rendered":"https:\/\/jeez-semicon.com\/?p=1661"},"modified":"2026-03-13T09:53:43","modified_gmt":"2026-03-13T01:53:43","slug":"polishing-templates-for-compound-semiconductor-wafers-gaas-inp-sapphire","status":"publish","type":"post","link":"https:\/\/jeez-semicon.com\/zh\/blog\/polishing-templates-for-compound-semiconductor-wafers-gaas-inp-sapphire\/","title":{"rendered":"Polishing Templates for Compound Semiconductor Wafers: GaAs, InP &amp; Sapphire"},"content":{"rendered":"<!DOCTYPE html>\n<html lang=\"en\">\n<head>\n<meta charset=\"UTF-8\" \/>\n<meta name=\"viewport\" content=\"width=device-width, initial-scale=1.0\" \/>\n\n<meta name=\"description\" content=\"Engineering guide to polishing templates for GaAs, InP, and sapphire wafer processing. Covers fracture risk, slurry chemistry compatibility, soft backing pad selection, EER design for III-V substrates, and substrate-specific specification parameters.\" \/>\n<meta name=\"keywords\" content=\"GaAs polishing template, InP wafer polishing template, sapphire polishing template, compound semiconductor polishing template, III-V wafer polishing fixture, GaAs CMP template, InP polishing fixture, sapphire substrate polishing template, compound semiconductor wafer polishing\" \/>\n<link rel=\"canonical\" href=\"https:\/\/jeez-semicon.com\/blog\/Polishing-Templates-for-Compound-Semiconductor-Wafers-GaAs-InP-Sapphire\" \/>\n\n<meta property=\"og:title\" content=\"Polishing Templates for Compound Semiconductor Wafers: GaAs, InP &#038; Sapphire\" \/>\n<meta property=\"og:description\" content=\"Substrate-specific polishing template engineering for GaAs, InP, and sapphire wafers. Covers fracture mechanics, bromine-based slurry compatibility, soft backing pad requirements, and EER design for III-V compound semiconductors.\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:url\" content=\"https:\/\/jeez-semicon.com\/blog\/Polishing-Templates-for-Compound-Semiconductor-Wafers-GaAs-InP-Sapphire\" \/>\n\n<script type=\"application\/ld+json\">\n{\n  \"@context\": \"https:\/\/schema.org\",\n  \"@graph\": [\n    {\n      \"@type\": \"Article\",\n      \"headline\": \"Polishing Templates for Compound Semiconductor Wafers: GaAs, InP & Sapphire\",\n      \"description\": \"Substrate-specific engineering guide for polishing templates used in GaAs, InP, and sapphire wafer processing, covering fracture risk mitigation, slurry chemistry compatibility, backing pad selection, EER design, and complete specification parameters.\",\n      \"author\": { \"@type\": \"Organization\", \"name\": \"Jizhi Electronic Technology Co., Ltd.\", \"url\": \"https:\/\/jeez-semicon.com\" },\n      \"publisher\": { \"@type\": \"Organization\", \"name\": \"Jizhi Electronic Technology Co., Ltd.\", \"url\": \"https:\/\/jeez-semicon.com\" },\n      \"mainEntityOfPage\": { \"@type\": \"WebPage\", \"@id\": \"https:\/\/jeez-semicon.com\/blog\/Polishing-Templates-for-Compound-Semiconductor-Wafers-GaAs-InP-Sapphire\" }\n    },\n    {\n      \"@type\": \"FAQPage\",\n      \"mainEntity\": [\n        {\n          \"@type\": \"Question\",\n          \"name\": \"Why do GaAs wafers require different polishing templates than silicon?\",\n          \"acceptedAnswer\": {\n            \"@type\": \"Answer\",\n            \"text\": \"GaAs has a fracture toughness approximately 25% that of silicon (0.44 MPa\u00b7m\u00bd vs 0.7\u20130.9 MPa\u00b7m\u00bd), making it highly susceptible to edge chipping and wafer cracking under stress concentrations. GaAs polishing also uses bromine-methanol or bromine-based acidic slurries that are chemically incompatible with standard FR-4 carrier plates, requiring G-10 or CXT-grade material. Additionally, GaAs wafers must not be subjected to thermal cycles, making waxless templates essential \u2014 wax mounting's 70\u201385\u00b0C bonding temperature causes differential thermal stress at the GaAs-wax interface that is a primary source of wafer cracking.\"\n          }\n        },\n        {\n          \"@type\": \"Question\",\n          \"name\": \"What backing pad hardness is recommended for GaAs and InP polishing?\",\n          \"acceptedAnswer\": {\n            \"@type\": \"Answer\",\n            \"text\": \"Soft backing pads (Shore A 30\u201350) are recommended for GaAs and InP polishing. The low fracture toughness of III-V compound semiconductors means that any stress concentration at the wafer edge \u2014 including those caused by a stiff backing pad transmitting carrier head pressure non-uniformities \u2014 can initiate edge chipping or subsurface cracking. Soft pads average out pressure non-uniformities and reduce stress concentrations at the wafer perimeter, significantly lowering breakage rates compared to medium or hard pad specifications used for silicon.\"\n          }\n        },\n        {\n          \"@type\": \"Question\",\n          \"name\": \"What slurry chemistry is used for GaAs polishing and how does it affect template material?\",\n          \"acceptedAnswer\": {\n            \"@type\": \"Answer\",\n            \"text\": \"GaAs polishing uses bromine-based slurries \u2014 typically bromine-methanol (0.05\u20130.5% Br\u2082 in methanol) or sodium hypobromite solutions \u2014 at mildly acidic to near-neutral pH (4\u20137). Bromine is a strong oxidant that attacks the epoxy resin in FR-4 carrier plates within 20\u201330 polishing cycles, causing surface degradation and eventual delamination. G-10 provides marginal improvement but is also inadequate for extended production use with bromine chemistry. CXT-grade or chemically resistant polymer templates are the recommended carrier plate material for production GaAs polishing.\"\n          }\n        },\n        {\n          \"@type\": \"Question\",\n          \"name\": \"Can sapphire wafer polishing use standard FR-4 polishing templates?\",\n          \"acceptedAnswer\": {\n            \"@type\": \"Answer\",\n            \"text\": \"Standard FR-4 templates can be used for sapphire polishing if the slurry pH is kept within the alkaline range (pH 8\u201312, standard colloidal silica). However, many sapphire polishing processes use acidic diamond slurries (pH 3\u20136) for initial planarization, which require G-10 minimum and CXT-grade preferred for production cycle counts above 50. Sapphire's very high hardness (Mohs 9) and the long polishing cycles required also favor harder backing pads (Shore A 65\u201375) than silicon SSP, and an EER is recommended for achieving the sub-2 mm edge exclusion required for LED and VCSEL wafer applications.\"\n          }\n        }\n      ]\n    }\n  ]\n}\n<\/script>\n\n<style>\n  @import url('https:\/\/fonts.googleapis.com\/css2?family=DM+Serif+Display:ital@0;1&family=DM+Sans:opsz,wght@9..40,300;9..40,400;9..40,500;9..40,600&family=JetBrains+Mono:wght@400;500&display=swap');\n\n  :root {\n    --navy:      #0a1628;\n    --navy-mid:  #112240;\n    --blue:      #1a56db;\n    --blue-lite: #3b82f6;\n    --cyan:      #06b6d4;\n    --slate:     #334155;\n    --muted:     #64748b;\n    --border:    #e2e8f0;\n    --bg:        #f8fafc;\n    --white:     #ffffff;\n    --accent:    #f59e0b;\n    --green:     #10b981;\n    --teal:      #0f766e;\n    --red:       #ef4444;\n    --gaas:      #0f766e;   \/* teal for GaAs *\/\n    --inp:       #0369a1; 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font-size: 11px; color: #5eead4; }\n\n  \/* \u2500\u2500 FAQ \u2500\u2500 *\/\n  .faq-item { border-bottom: 1px solid var(--border); padding: 20px 0; }\n  .faq-item:last-child { border-bottom: none; }\n  .faq-q { font-weight: 600; color: var(--navy-mid); font-size: 16px; margin-bottom: 10px; display: flex; gap: 10px; align-items: flex-start; }\n  .faq-q::before { content: 'Q'; font-family: 'JetBrains Mono', monospace; font-size: 12px; color: var(--white); background: var(--gaas); border-radius: 4px; padding: 2px 6px; flex-shrink: 0; margin-top: 1px; }\n  .faq-a { font-size: 15px; color: var(--slate); padding-left: 32px; }\n\n  \/* \u2500\u2500 CTA \u2500\u2500 *\/\n  .cta-banner { background: linear-gradient(135deg, #071a18 0%, #0a1628 100%); border-radius: var(--radius); padding: 44px 40px; text-align: center; color: var(--white); margin: 56px 0 0; box-shadow: var(--shadow-lg); position: relative; overflow: hidden; }\n  .cta-banner::before { content: ''; position: absolute; inset: 0; background: radial-gradient(ellipse at 65% 40%, rgba(15,118,110,.2) 0%, transparent 60%); pointer-events: none; }\n  .cta-banner h2 { font-family: 'DM Serif Display', serif; font-size: clamp(22px, 3.5vw, 30px); color: var(--white); margin: 0 0 12px; }\n  .cta-banner p { color: rgba(255,255,255,.72); font-size: 16px; max-width: 520px; margin: 0 auto 28px; }\n  .cta-btn { display: inline-flex; align-items: center; gap: 8px; background: #5eead4; color: var(--navy); text-decoration: none; font-weight: 600; font-size: 15px; padding: 14px 32px; border-radius: 8px; transition: opacity .2s, transform .15s; }\n  .cta-btn:hover { opacity: .9; transform: translateY(-1px); color: var(--navy); }\n\n  .back-to-pillar { display: inline-flex; align-items: center; gap: 8px; background: var(--bg); border: 1px solid var(--border); color: var(--slate); text-decoration: none; font-size: 13.5px; font-weight: 500; padding: 10px 18px; border-radius: 8px; margin: 40px 0 0; transition: border-color .2s, color .2s; }\n  .back-to-pillar::before { content: '\u2190'; color: var(--blue); }\n  .back-to-pillar:hover { border-color: var(--blue); color: var(--blue); }\n<\/style>\n<\/head>\n<body>\n\n<div class=\"hero\">\n  <div class=\"hero-eyebrow\">Compound Semiconductor Substrates<\/div>\n  <p class=\"hero-sub\">III-V compound semiconductors and sapphire demand polishing templates that silicon engineers rarely encounter: softer pads to protect fracture-prone crystals, chemically resistant carrier plates for bromine and acid slurries, and careful EER design for materials that chip rather than yield. This guide covers each substrate in full.<\/p>\n  <p class=\"hero-meta\">\n    <span>\u7531\u96c6\u667a\u7535\u5b50\u79d1\u6280\u6709\u9650\u516c\u53f8\u63d0\u4f9b.<\/span>\n    <span>\u00b7<\/span>\n    <span>\u534a\u5bfc\u4f53\u629b\u5149\u4e13\u5bb6<\/span>\n    <span>\u00b7<\/span>\n    <span>14 min read<\/span>\n  <\/p>\n<\/div>\n\n<div class=\"page-wrap\">\n\n  <nav class=\"breadcrumb\">\n    <a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/Polishing-Templates-for-Semiconductor-Silicon-Wafer-Processing\/\" target=\"_blank\">\u2190 \u629b\u5149\u6a21\u677f\uff1a\u5b8c\u6574\u6307\u5357<\/a>\n    <span>\/<\/span>\n    GaAs, InP &amp; Sapphire Templates\n  <\/nav>\n\n  <nav class=\"toc-box\">\n    <h2>\u76ee\u5f55<\/h2>\n    <ol class=\"toc-list\">\n      <li><a href=\"#why-different\">Why Compound Semiconductors Need Different Templates<\/a><\/li>\n      <li><a href=\"#fracture-risk\">Fracture Risk: The Primary Design Constraint<\/a><\/li>\n      <li><a href=\"#gaas\">GaAs Polishing Templates \u2014 Full Guide<\/a><\/li>\n      <li><a href=\"#inp\">InP Polishing Templates \u2014 Full Guide<\/a><\/li>\n      <li><a href=\"#sapphire\">Sapphire Polishing Templates \u2014 Full Guide<\/a><\/li>\n      <li><a href=\"#shared-principles\">Shared Design Principles Across All Three Substrates<\/a><\/li>\n      <li><a href=\"#slurry-compat\">Slurry Chemistry Compatibility Summary<\/a><\/li>\n      <li><a href=\"#comparison-table\">Side-by-Side Specification Comparison<\/a><\/li>\n      <li><a href=\"#handling\">Handling &amp; Loading Best Practices<\/a><\/li>\n      <li><a href=\"#faq\">\u5e38\u89c1\u95ee\u9898<\/a><\/li>\n    <\/ol>\n  <\/nav>\n\n  <!-- \u2550\u2550\u2550 SECTION 1 \u2550\u2550\u2550 -->\n  <h2 id=\"why-different\">Why Compound Semiconductors Need Different Templates Than Silicon<\/h2>\n\n  <p>Silicon wafer polishing is the reference process against which all other semiconductor polishing is measured \u2014 it runs at moderate pressures with alkaline slurries on a substrate that, while brittle, has enough fracture toughness to tolerate normal process variability without catastrophic yield loss. The polishing templates designed for silicon reflect these forgiving conditions: medium-hardness backing pads, FR-4 or G-10 carrier plates at alkaline pH, and process pressures that leave considerable margin before fracture risk becomes significant.<\/p>\n\n  <p>Compound semiconductors \u2014 GaAs, InP, and related III-V materials \u2014 and oxide substrates like sapphire do not share these forgiving properties. Each presents a distinct combination of challenges that requires deliberate template engineering rather than adaptation of the silicon template specification. Understanding <a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/Polishing-Templates-for-Semiconductor-Silicon-Wafer-Processing\/\" target=\"_blank\" class=\"text-link-pill\">\u629b\u5149\u6a21\u677f\u57fa\u7840<\/a> is the starting point, but the substrate-specific details covered in this article are what prevent the breakage rates, contamination failures, and edge exclusion problems that occur when silicon-derived template assumptions are applied to compound semiconductor processing.<\/p>\n\n  <hr class=\"divider\" \/>\n\n  <!-- \u2550\u2550\u2550 SECTION 2 \u2550\u2550\u2550 -->\n  <h2 id=\"fracture-risk\">Fracture Risk: The Primary Design Constraint for III-V Substrates<\/h2>\n\n  <p>The single most important property distinguishing III-V compound semiconductor substrates from silicon for polishing template design is fracture toughness \u2014 the material&#8217;s resistance to crack propagation once a stress concentration (such as an edge chip or surface scratch) initiates a crack.<\/p>\n\n  <div class=\"fragility-bars\">\n    <div class=\"frag-row\">\n      <span class=\"frag-label\">\u7845<\/span>\n      <div class=\"frag-track\"><div class=\"frag-fill frag-si\"><\/div><\/div>\n      <span class=\"frag-note\">0.7-0.9 MPa-m\u00bd<\/span>\n    <\/div>\n    <div class=\"frag-row\">\n      <span class=\"frag-label\">\u7837\u5316\u9553<\/span>\n      <div class=\"frag-track\"><div class=\"frag-fill frag-gaas\"><\/div><\/div>\n      <span class=\"frag-note\">0.44 MPa\u00b7m\u00bd<\/span>\n    <\/div>\n    <div class=\"frag-row\">\n      <span class=\"frag-label\">InP<\/span>\n      <div class=\"frag-track\"><div class=\"frag-fill frag-inp\"><\/div><\/div>\n      <span class=\"frag-note\">0.32 MPa\u00b7m\u00bd<\/span>\n    <\/div>\n    <div class=\"frag-row\">\n      <span class=\"frag-label\">\u84dd\u5b9d\u77f3<\/span>\n      <div class=\"frag-track\"><div class=\"frag-fill frag-sap\"><\/div><\/div>\n      <span class=\"frag-note\">2.0\u20133.0 MPa\u00b7m\u00bd<\/span>\n    <\/div>\n  <\/div>\n\n  <p>GaAs fracture toughness is approximately half that of silicon; InP is even lower, at roughly one-third. This means that stress concentrations which a silicon wafer tolerates without consequence \u2014 from carrier head pressure non-uniformity, from retaining ring contact, from an edge chip during loading \u2014 can propagate to full wafer fracture in GaAs or InP. Sapphire, by contrast, has higher fracture toughness than silicon, but its extreme hardness (Mohs 9.0) and near-chemical inertness create different challenges: very slow polishing rates, acidic slurry requirements, and long polishing cycles that stress template chemical compatibility.<\/p>\n\n  <p>The fracture risk from thermal stress is an additional, often overlooked factor for III-V substrates. GaAs has a coefficient of thermal expansion (CTE) of 5.73 \u00d7 10\u207b\u2076\/\u00b0C \u2014 more than twice silicon&#8217;s 2.6 \u00d7 10\u207b\u2076\/\u00b0C. When a GaAs wafer is bonded to a wax mount block using conventional wax mounting procedures at 70\u201385\u00b0C, the differential CTE between the wafer and the polishing block creates biaxial thermal stress during the cooling cycle that routinely causes wafer cracking in the 50\u2013200 \u00b5m thickness range. This is the primary reason waxless polishing templates are not merely preferred but effectively mandatory for production GaAs and InP polishing. The full waxless vs. wax comparison, including the CTE mismatch quantification, is in our <a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/Waxless-Polishing-Templates-vs-Wax-Mounting-Cost-Quality-Process-Comparison\/\" target=\"_blank\" class=\"text-link-pill\">waxless vs. wax mounting guide<\/a>.<\/p>\n\n  <hr class=\"divider\" \/>\n\n  <!-- \u2550\u2550\u2550 SECTION 3 \u2014 GaAs \u2550\u2550\u2550 -->\n  <h2 id=\"gaas\">GaAs Polishing Templates<\/h2>\n\n  <!-- substrate tabs -->\n  <div class=\"substrate-tabs\">\n    <div class=\"substrate-tab tab-gaas\">\u7837\u5316\u9553<\/div>\n  <\/div>\n  <div class=\"substrate-section\">\n    <div class=\"substrate-section-head gaas-head\">\n      <div>\n        <h3>Gallium Arsenide (GaAs) \u2014 Template Engineering Guide<\/h3>\n        <div class=\"sub-meta\">Applications: RF\/microwave ICs, laser diodes, solar cells, HBTs, pHEMTs<\/div>\n      <\/div>\n    <\/div>\n    <div class=\"substrate-section-body\">\n\n      <div class=\"prop-grid\">\n        <div class=\"prop-item\"><div class=\"prop-label\">Crystal structure<\/div><div class=\"prop-value\">Zinc blende<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">\u65ad\u88c2\u97e7\u6027<\/div><div class=\"prop-value danger\">0.44 MPa\u00b7m\u00bd (low)<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">\u83ab\u6c0f\u786c\u5ea6<\/div><div class=\"prop-value\">~3.5<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">CTE<\/div><div class=\"prop-value caution\">5.73 \u00d7 10\u207b\u2076\/\u00b0C<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">Cleavage planes<\/div><div class=\"prop-value danger\">{110} \u2014 easy cleavage<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">Wafer diameters<\/div><div class=\"prop-value\">50\u2013150 mm (production)<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">Typical thickness<\/div><div class=\"prop-value\">350\u2013625 \u00b5m<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">\u629b\u5149\u6ce5\u6d46<\/div><div class=\"prop-value caution\">Bromine-based, pH 4\u20137<\/div><\/div>\n      <\/div>\n\n      <h3 style=\"margin-top:8px\">The GaAs Polishing Challenge<\/h3>\n      <p>GaAs combines low fracture toughness with well-defined {110} cleavage planes that run parallel to the flat or notch on the wafer. Any stress concentration that exceeds the cleavage plane&#8217;s fracture toughness threshold \u2014 whether from mechanical contact at the wafer edge, from differential thermal expansion, or from polishing pad pressure non-uniformity \u2014 propagates instantly along the cleavage plane, splitting the wafer rather than creating a localized chip. This makes GaAs polishing less forgiving of edge stress than any other common semiconductor substrate.<\/p>\n\n      <p>The chemical challenge compounds the mechanical one. GaAs contains gallium and arsenic \u2014 both of which oxidize in aqueous environments. Standard alkaline silica slurries produce a Ga\u2082O\u2083\/As\u2082O\u2083 surface oxide that is not efficiently removed by silica abrasives, leading to unacceptably slow removal rates and surface contamination. Effective GaAs polishing requires bromine-based chemistry that dissolves the surface oxide chemically as it forms, maintaining a reactive surface for mechanical removal. This bromine chemistry is corrosive to FR-4 and G-10 carrier plate materials.<\/p>\n\n      <h3>Template Specification for GaAs<\/h3>\n\n      <p><strong>Carrier plate material: G-10 minimum, CXT preferred.<\/strong> Bromine-methanol slurry at pH 4\u20137 is marginal for G-10 (20\u201340% longer life than FR-4, but still limited at high cycle counts) and incompatible with FR-4. For production runs above 50 cycles per lot, CXT-grade is the recommended carrier plate material for GaAs polishing. G-10 is acceptable for low-volume R&amp;D use where template replacement frequency is not a cost constraint.<\/p>\n\n      <p><strong>Backing pad hardness: Shore A 30\u201350 (soft).<\/strong> This is the most important GaAs-specific template parameter. Soft pads serve two purposes: they average out carrier head pressure non-uniformities that would otherwise concentrate stress at the wafer edge, and they reduce the shear force applied to the wafer during lateral loading in the work hole. A medium-hard pad (Shore A 60\u201370, appropriate for silicon) produces edge pressure concentrations sufficient to initiate cleavage-plane fractures in GaAs at process pressures as low as 2\u20133 psi. Soft pad specification is non-negotiable for production GaAs polishing.<\/p>\n\n      <p><strong>Work-hole radial clearance: 0.15\u20130.25 mm.<\/strong> Tighter than the 0.3\u20130.5 mm standard for silicon. GaAs&#8217;s tendency to slide along cleavage planes means that excess lateral freedom in the work hole creates intermittent contact between the wafer edge and the work-hole wall during polishing, which is a crack initiation source. Tighter clearance prevents this contact while the soft backing pad provides the compliance needed for pressure uniformity.<\/p>\n\n      <p><strong>Process pressure: 1\u20133 psi maximum.<\/strong> GaAs polishing operates at the lower end of the SSP pressure range. Higher pressures increase both the removal rate and the fracture risk in proportion \u2014 the marginal yield improvement from higher pressure is rarely worth the breakage rate increase.<\/p>\n\n      <div class=\"spec-mini\">\n        <div class=\"spec-mini-title gaas-title\">GaAs Template \u2014 Specification Summary<\/div>\n        <div class=\"spec-mini-grid\">\n          <div class=\"spec-mini-item\"><div class=\"sl\">\u8f7d\u4f53\u6750\u6599<\/div><div class=\"sv\">CXT (preferred) \/ G-10<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">\u5e95\u57ab\u90b5\u6c0f A<\/div><div class=\"sv\">30\u201350 (soft)<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">\u5de5\u5b54\u95f4\u9699<\/div><div class=\"sv\">0.15\u20130.25 mm<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">\u5de5\u827a\u538b\u529b<\/div><div class=\"sv\">1\u20133 psi<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Waxless?<\/div><div class=\"sv\">Mandatory<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">EER height<\/div><div class=\"sv\">40\u2013100 \u00b5m<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Slurry pH range<\/div><div class=\"sv\">4-7<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">\u5178\u578b\u5faa\u73af\u5bff\u547d<\/div><div class=\"sv\">80-150 \u4e2a\u5faa\u73af<\/div><\/div>\n        <\/div>\n      <\/div>\n\n      <div class=\"callout warning\">\n        <span class=\"callout-icon\">\u26a0\ufe0f<\/span>\n        <div class=\"callout-body\">\n          <strong>GaAs EER Height: Conservative First-Iteration Approach<\/strong>\n          For GaAs, the EER height should be set conservatively (at the lower end of the 40\u2013100 \u00b5m range) in the first qualification iteration. An EER that over-corrects the edge pressure \u2014 increasing contact force at the wafer perimeter above the cleavage fracture threshold \u2014 can cause edge chipping that propagates into full wafer cracking. It is better to leave residual edge rolloff in iteration 1 and increase EER height in iteration 2 than to over-correct and fracture qualification wafers.\n        <\/div>\n      <\/div>\n\n    <\/div>\n  <\/div>\n\n  <!-- \u2550\u2550\u2550 SECTION 4 \u2014 InP \u2550\u2550\u2550 -->\n  <h2 id=\"inp\">InP Polishing Templates<\/h2>\n\n  <div class=\"substrate-tabs\">\n    <div class=\"substrate-tab tab-inp\">InP<\/div>\n  <\/div>\n  <div class=\"substrate-section\">\n    <div class=\"substrate-section-head inp-head\">\n      <div>\n        <h3>Indium Phosphide (InP) \u2014 Template Engineering Guide<\/h3>\n        <div class=\"sub-meta\">Applications: optical fiber telecom lasers, InGaAs photodetectors, mm-wave ICs, photonic integrated circuits<\/div>\n      <\/div>\n    <\/div>\n    <div class=\"substrate-section-body\">\n\n      <div class=\"prop-grid\">\n        <div class=\"prop-item\"><div class=\"prop-label\">Crystal structure<\/div><div class=\"prop-value\">Zinc blende<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">\u65ad\u88c2\u97e7\u6027<\/div><div class=\"prop-value danger\">0.32 MPa\u00b7m\u00bd (very low)<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">\u83ab\u6c0f\u786c\u5ea6<\/div><div class=\"prop-value\">~4.5<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">CTE<\/div><div class=\"prop-value caution\">4.6 \u00d7 10\u207b\u2076\/\u00b0C<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">Cleavage planes<\/div><div class=\"prop-value danger\">{110} \u2014 extremely easy<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">Wafer diameters<\/div><div class=\"prop-value\">50\u2013100 mm (production)<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">Typical thickness<\/div><div class=\"prop-value\">350\u2013625 \u00b5m<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">\u629b\u5149\u6ce5\u6d46<\/div><div class=\"prop-value caution\">Br\u2082\/HBr, NaOCl, pH 7\u201310<\/div><\/div>\n      <\/div>\n\n      <h3 style=\"margin-top:8px\">InP: The Most Fracture-Sensitive Production Substrate<\/h3>\n      <p>Indium phosphide has the lowest fracture toughness of any commonly produced semiconductor substrate \u2014 0.32 MPa\u00b7m\u00bd, approximately 45% of GaAs and less than half of silicon. This extreme brittleness, combined with well-defined {110} cleavage planes, makes InP the substrate where polishing template design decisions have the largest impact on breakage rate. InP wafers are expensive (typically 3\u20138\u00d7 the cost of equivalent-diameter GaAs) and are often processed in small lot sizes for telecom and photonic applications, making each breakage event economically significant.<\/p>\n\n      <p>The fracture propagation speed in InP is effectively instantaneous once the fracture toughness threshold is exceeded \u2014 there is no plastic deformation or crack arrest mechanism that might limit damage in a more ductile material. This means that template design for InP must be preventive rather than damage-limiting: the template must be engineered to prevent any stress concentration from reaching the fracture initiation threshold, because once initiated, fracture is total.<\/p>\n\n      <h3>Template Specification for InP<\/h3>\n\n      <p><strong>Carrier plate material: CXT-grade strongly recommended.<\/strong> InP polishing slurries \u2014 typically HBr\/Br\u2082-based (pH 5\u20137) or NaOCl-based alkaline chemistry \u2014 are corrosive to both FR-4 and G-10. CXT-grade is the production standard. Because InP lot sizes are typically small (25\u2013100 wafers\/lot), the higher template cost per unit is less significant relative to the wafer cost being protected.<\/p>\n\n      <p><strong>Backing pad hardness: Shore A 25\u201345 (ultra-soft).<\/strong> InP requires the softest backing pads used in any semiconductor polishing application. Even Shore A 50 pads, acceptable for GaAs, can produce sufficient edge pressure concentration to initiate cleavage in InP at 1\u20132 psi. Shore A 25\u201340 pads are recommended for production InP polishing. These ultra-soft pads significantly limit pressure uniformity and material removal rate efficiency \u2014 a deliberate trade-off that prioritizes breakage prevention over throughput optimization.<\/p>\n\n      <p><strong>Work-hole radial clearance: 0.15\u20130.20 mm.<\/strong> Tight clearance, as for GaAs, to prevent edge-wall contact. InP wafers typically have slightly less precise incoming diameter control than silicon prime wafers, so the clearance specification must account for OD variation \u2014 measure incoming wafer OD from each lot before specifying the work-hole diameter.<\/p>\n\n      <p><strong>Multi-wafer template design consideration.<\/strong> Many InP polishing templates are designed for single-wafer-per-carrier operation rather than the multi-cavity templates common for silicon, because the precise centering of each wafer in its work hole is more critical for InP than for more fracture-resistant substrates. In a multi-cavity template, small differences in work-hole centering between cavities create differential pressure profiles that increase cleavage risk for the off-center wafers.<\/p>\n\n      <div class=\"spec-mini\">\n        <div class=\"spec-mini-title inp-title\">InP Template \u2014 Specification Summary<\/div>\n        <div class=\"spec-mini-grid\">\n          <div class=\"spec-mini-item\"><div class=\"sl\">\u8f7d\u4f53\u6750\u6599<\/div><div class=\"sv\">CXT-grade (required)<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">\u5e95\u57ab\u90b5\u6c0f A<\/div><div class=\"sv\">25\u201345 (ultra-soft)<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">\u5de5\u5b54\u95f4\u9699<\/div><div class=\"sv\">0.15\u20130.20 mm<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">\u5de5\u827a\u538b\u529b<\/div><div class=\"sv\">0.5\u20132.0 psi<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Waxless?<\/div><div class=\"sv\">Mandatory<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">EER height<\/div><div class=\"sv\">30\u201380 \u00b5m (conservative)<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Slurry pH range<\/div><div class=\"sv\">5\u201310<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">\u5178\u578b\u5faa\u73af\u5bff\u547d<\/div><div class=\"sv\">100\u2013180 cycles<\/div><\/div>\n        <\/div>\n      <\/div>\n\n      <div class=\"callout danger\">\n        <span class=\"callout-icon\">\ud83d\udd34<\/span>\n        <div class=\"callout-body\">\n          <strong>InP Arsenic\/Phosphorus Handling \u2014 Safety Note<\/strong>\n          InP contains phosphorus and traces of indium that present occupational health hazards in polishing operations. Polishing slurry containing InP abrasion products must be handled as hazardous waste. This is a process safety consideration independent of template engineering, but it affects the template cleaning and disposal procedures at end-of-life \u2014 ensure your facility&#8217;s chemical waste management program covers InP polishing byproducts.\n        <\/div>\n      <\/div>\n\n    <\/div>\n  <\/div>\n\n  <!-- \u2550\u2550\u2550 SECTION 5 \u2014 Sapphire \u2550\u2550\u2550 -->\n  <h2 id=\"sapphire\">Sapphire Polishing Templates<\/h2>\n\n  <div class=\"substrate-tabs\">\n    <div class=\"substrate-tab tab-sap\">\u84dd\u5b9d\u77f3<\/div>\n  <\/div>\n  <div class=\"substrate-section\">\n    <div class=\"substrate-section-head sap-head\">\n      <div>\n        <h3>Sapphire (Al\u2082O\u2083) \u2014 Template Engineering Guide<\/h3>\n        <div class=\"sub-meta\">Applications: LED substrates (GaN-on-sapphire), VCSEL, RF filters, optical windows, power electronics<\/div>\n      <\/div>\n    <\/div>\n    <div class=\"substrate-section-body\">\n\n      <div class=\"prop-grid\">\n        <div class=\"prop-item\"><div class=\"prop-label\">Crystal structure<\/div><div class=\"prop-value\">Trigonal (corundum)<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">\u65ad\u88c2\u97e7\u6027<\/div><div class=\"prop-value ok\">2.0\u20133.0 MPa\u00b7m\u00bd (high)<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">\u83ab\u6c0f\u786c\u5ea6<\/div><div class=\"prop-value danger\">9.0 (near SiC)<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">CTE (c-axis)<\/div><div class=\"prop-value\">6.66 \u00d7 10\u207b\u2076\/\u00b0C<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">CTE anisotropy<\/div><div class=\"prop-value caution\">a-axis vs c-axis differ 8%<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">Wafer diameters<\/div><div class=\"prop-value\">50\u2013150 mm (LED volume)<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">Typical thickness<\/div><div class=\"prop-value\">430\u2013650 \u00b5m<\/div><\/div>\n        <div class=\"prop-item\"><div class=\"prop-label\">\u629b\u5149\u6ce5\u6d46<\/div><div class=\"prop-value caution\">Diamond\/SiC, pH 3\u20139<\/div><\/div>\n      <\/div>\n\n      <h3 style=\"margin-top:8px\">Sapphire: Hard, Chemically Inert, and Anisotropic<\/h3>\n      <p>Sapphire&#8217;s polishing challenges are the inverse of InP&#8217;s: where InP is dangerously fragile, sapphire is mechanically robust. The template design concern for sapphire is not breakage prevention but chemical compatibility with acidic diamond slurries, handling of the long polishing cycle times required by sapphire&#8217;s extreme hardness, and managing the anisotropic polishing behavior that results from sapphire&#8217;s trigonal crystal structure.<\/p>\n\n      <p>Sapphire&#8217;s CTE anisotropy \u2014 the a-axis and c-axis thermal expansion coefficients differ by approximately 8% \u2014 creates internal thermal stress when the wafer is heated or cooled non-uniformly. This anisotropy makes sapphire more susceptible to thermally-induced warping during extended polishing cycles than isotropic substrates. For polishing cycles exceeding 60 minutes, temperature control of the polishing table to \u00b12\u00b0C or better is recommended to prevent thermally-induced TTV excursions from sapphire warping during polishing \u2014 a process consideration that affects template selection indirectly through its interaction with the backing pad compliance.<\/p>\n\n      <h3>Template Specification for Sapphire<\/h3>\n\n      <p><strong>Carrier plate material: G-10 for mild acid slurry; CXT for diamond slurry below pH 5.<\/strong> Sapphire polishing uses diamond abrasive slurries at pH 3\u20139 depending on the polishing step. For initial coarse polishing with acidic diamond slurry (pH 3\u20135), CXT-grade is recommended. For final polishing with near-neutral to mildly alkaline silica slurry (pH 7\u20139), G-10 is adequate. FR-4 should be avoided for any sapphire polishing application using slurry below pH 8.<\/p>\n\n      <p><strong>Backing pad hardness: Shore A 60\u201375 (medium-hard).<\/strong> Unlike the III-V substrates, sapphire&#8217;s high fracture toughness allows the use of medium-hard backing pads without significant breakage risk. Harder pads improve TTV uniformity for sapphire&#8217;s long polishing cycles by maintaining more stable work-hole depth control under sustained load. Shore A 65\u201370 is the most common production specification for 2-inch and 4-inch sapphire LED substrates.<\/p>\n\n      <p><strong>EER for sub-2 mm edge exclusion.<\/strong> Sapphire LED substrate applications \u2014 particularly for 4-inch c-plane sapphire used in high-brightness LED production \u2014 often require sub-2 mm edge exclusion to maximize LED die count per wafer. EER design for sapphire follows the same principles as silicon, with EER heights in the 60\u2013150 \u00b5m range appropriate for sapphire&#8217;s process pressures (2\u20135 psi) and medium-hard backing pads.<\/p>\n\n      <p><strong>Multi-wafer templates for high-volume LED production.<\/strong> Sapphire LED substrate polishing at commercial scale uses multi-cavity templates (typically 3\u20137 wafers per carrier) to maximize polisher throughput. Multi-cavity sapphire templates require precise work-hole depth uniformity across all cavities (\u22645 \u00b5m variation between cavities) to prevent wafer-to-wafer TTV variation within a single polishing run. CMM verification of all work-hole depths on each template is required for production qualification.<\/p>\n\n      <div class=\"spec-mini\">\n        <div class=\"spec-mini-title sap-title\">Sapphire Template \u2014 Specification Summary<\/div>\n        <div class=\"spec-mini-grid\">\n          <div class=\"spec-mini-item\"><div class=\"sl\">\u8f7d\u4f53\u6750\u6599<\/div><div class=\"sv\">G-10 or CXT (pH-dependent)<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">\u5e95\u57ab\u90b5\u6c0f A<\/div><div class=\"sv\">60\u201375 (medium-hard)<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">\u5de5\u5b54\u95f4\u9699<\/div><div class=\"sv\">0.25\u20130.40 mm<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">\u5de5\u827a\u538b\u529b<\/div><div class=\"sv\">2\u20135 psi<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Waxless?<\/div><div class=\"sv\">Strongly preferred<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">EER height<\/div><div class=\"sv\">60\u2013150 \u00b5m<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">Slurry pH range<\/div><div class=\"sv\">3\u20139<\/div><\/div>\n          <div class=\"spec-mini-item\"><div class=\"sl\">\u5178\u578b\u5faa\u73af\u5bff\u547d<\/div><div class=\"sv\">80\u2013160 cycles<\/div><\/div>\n        <\/div>\n      <\/div>\n\n    <\/div>\n  <\/div>\n\n  <!-- \u2550\u2550\u2550 SECTION 6 \u2550\u2550\u2550 -->\n  <h2 id=\"shared-principles\">Shared Design Principles Across All Three Substrates<\/h2>\n\n  <p>Despite their different physical properties and polishing chemistry requirements, GaAs, InP, and sapphire polishing templates share three fundamental design principles that differentiate them from silicon polishing templates.<\/p>\n\n  <h3>1. Waxless Processing Is the Default, Not Optional<\/h3>\n  <p>All three substrates benefit from or require waxless polishing templates. For GaAs and InP, waxless processing eliminates the thermal stress during wax bonding and debonding that is a primary source of cleavage-plane fractures in production. For sapphire, waxless processing eliminates the risk of differential thermal expansion stress from sapphire&#8217;s CTE anisotropy during the wax cycle. The economic case for waxless processing \u2014 lower total cost per wafer, higher throughput, zero organic contamination \u2014 is covered in detail in our <a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/Waxless-Polishing-Templates-vs-Wax-Mounting-Cost-Quality-Process-Comparison\/\" target=\"_blank\" class=\"text-link-pill\">waxless vs. wax mounting comparison<\/a>.<\/p>\n\n  <h3>2. Chemical Compatibility Must Be Verified Against the Actual Slurry<\/h3>\n  <p>All three substrates use slurry chemistries that are incompatible with FR-4 and marginal for G-10. Specifying the carrier plate material as &#8220;standard FR-4&#8221; for any of these substrates is a process engineering error that will produce template failures at predictable cycle counts. The correct specification workflow \u2014 state slurry pH range and oxidant components, then select carrier plate material \u2014 is covered in our <a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/How-to-Specify-a-Polishing-Template-6-Parameters-Engineers-Must-Define\/\" target=\"_blank\" class=\"text-link-pill\">6 \u53c2\u6570\u89c4\u683c\u6307\u5357<\/a>.<\/p>\n\n  <h3>3. First-Article Qualification Must Include Breakage Rate Data<\/h3>\n  <p>For silicon templates, the primary qualification metrics are TTV, SFQR, and surface quality. For compound semiconductor and sapphire templates, breakage rate per 100 wafers polished is an additional mandatory qualification metric. A template that achieves excellent TTV but produces 2% wafer breakage in qualification is not a production-viable template, regardless of the flatness data. The backing pad Shore A specification and the EER height are the two template parameters most directly controllable to reduce breakage rate, and both must be validated against actual breakage data in qualification.<\/p>\n\n  <hr class=\"divider\" \/>\n\n  <!-- \u2550\u2550\u2550 SECTION 7 \u2550\u2550\u2550 -->\n  <h2 id=\"slurry-compat\">Slurry Chemistry Compatibility Summary<\/h2>\n\n  <div class=\"table-wrap\">\n    <table>\n      <thead>\n        <tr>\n          <th>\u57fa\u8d28<\/th>\n          <th>\u6ce5\u6d46\u5316\u5b66<\/th>\n          <th>pH \u503c\u8303\u56f4<\/th>\n          <th>FR-4<\/th>\n          <th>G-10<\/th>\n          <th>CXT<\/th>\n        <\/tr>\n      <\/thead>\n      <tbody>\n        <tr>\n          <td><strong>\u7837\u5316\u9553<\/strong><\/td>\n          <td>Bromine-methanol (Br\u2082\/MeOH)<\/td>\n          <td>4-7<\/td>\n          <td><span class=\"badge badge-red\">\u4e0d\u9002\u5408<\/span><\/td>\n          <td><span class=\"badge badge-amber\">\u8fb9\u7f18<\/span><\/td>\n          <td><span class=\"badge badge-green\">\u63a8\u8350<\/span><\/td>\n        <\/tr>\n        <tr>\n          <td><strong>\u7837\u5316\u9553<\/strong><\/td>\n          <td>NaOCl alkaline oxidant<\/td>\n          <td>9-11<\/td>\n          <td><span class=\"badge badge-amber\">\u8fb9\u7f18<\/span><\/td>\n          <td><span class=\"badge badge-green\">\u53ef\u4ee5\u63a5\u53d7<\/span><\/td>\n          <td><span class=\"badge badge-green\">\u63a8\u8350<\/span><\/td>\n        <\/tr>\n        <tr>\n          <td><strong>InP<\/strong><\/td>\n          <td>HBr \/ Br\u2082 acidic<\/td>\n          <td>5\u20137<\/td>\n          <td><span class=\"badge badge-red\">\u4e0d\u9002\u5408<\/span><\/td>\n          <td><span class=\"badge badge-amber\">\u8fb9\u7f18<\/span><\/td>\n          <td><span class=\"badge badge-green\">\u63a8\u8350<\/span><\/td>\n        <\/tr>\n        <tr>\n          <td><strong>InP<\/strong><\/td>\n          <td>NaOCl + citric acid<\/td>\n          <td>7\u20139<\/td>\n          <td><span class=\"badge badge-amber\">\u8fb9\u7f18<\/span><\/td>\n          <td><span class=\"badge badge-green\">\u53ef\u4ee5\u63a5\u53d7<\/span><\/td>\n          <td><span class=\"badge badge-green\">\u63a8\u8350<\/span><\/td>\n        <\/tr>\n        <tr>\n          <td><strong>\u84dd\u5b9d\u77f3<\/strong><\/td>\n          <td>\u91d1\u521a\u77f3\u78e8\u6599\uff0c\u9178\u6027<\/td>\n          <td>3-6<\/td>\n          <td><span class=\"badge badge-red\">\u4e0d\u9002\u5408<\/span><\/td>\n          <td><span class=\"badge badge-amber\">\u8fb9\u7f18<\/span><\/td>\n          <td><span class=\"badge badge-green\">\u63a8\u8350<\/span><\/td>\n        <\/tr>\n        <tr>\n          <td><strong>\u84dd\u5b9d\u77f3<\/strong><\/td>\n          <td>Colloidal silica, final polish<\/td>\n          <td>8\u201310<\/td>\n          <td><span class=\"badge badge-green\">\u53ef\u4ee5\u63a5\u53d7<\/span><\/td>\n          <td><span class=\"badge badge-green\">\u63a8\u8350<\/span><\/td>\n          <td><span class=\"badge badge-green\">\u63a8\u8350<\/span><\/td>\n        <\/tr>\n      <\/tbody>\n    <\/table>\n  <\/div>\n\n  <hr class=\"divider\" \/>\n\n  <!-- \u2550\u2550\u2550 SECTION 8 \u2550\u2550\u2550 -->\n  <h2 id=\"comparison-table\">Side-by-Side Specification Comparison<\/h2>\n\n  <div class=\"table-wrap\">\n    <table>\n      <thead>\n        <tr>\n          <th>\u53c2\u6570<\/th>\n          <th>\u7837\u5316\u9553<\/th>\n          <th>InP<\/th>\n          <th>\u84dd\u5b9d\u77f3<\/th>\n          <th>Si (reference)<\/th>\n        <\/tr>\n      <\/thead>\n      <tbody>\n        <tr>\n          <td><strong>\u627f\u8f7d\u677f\u6750\u6599<\/strong><\/td>\n          <td>CXT \/ G-10<\/td>\n          <td>CXT<\/td>\n          <td>CXT \/ G-10<\/td>\n          <td>FR-4 \/ G-10<\/td>\n        <\/tr>\n        <tr class=\"row-highlight\">\n          <td><strong>\u5e95\u57ab\u90b5\u6c0f A<\/strong><\/td>\n          <td><strong>30-50<\/strong><\/td>\n          <td><strong>25-45<\/strong><\/td>\n          <td><strong>60-75<\/strong><\/td>\n          <td>55\u201375<\/td>\n        <\/tr>\n        <tr>\n          <td><strong>\u5de5\u827a\u538b\u529b<\/strong><\/td>\n          <td>1\u20133 psi<\/td>\n          <td>0.5\u20132 psi<\/td>\n          <td>2\u20135 psi<\/td>\n          <td>2\u20135 psi<\/td>\n        <\/tr>\n        <tr>\n          <td><strong>\u5de5\u5b54\u95f4\u9699<\/strong><\/td>\n          <td>0.15\u20130.25 mm<\/td>\n          <td>0.15\u20130.20 mm<\/td>\n          <td>0.25\u20130.40 mm<\/td>\n          <td>0.25\u20130.50 mm<\/td>\n        <\/tr>\n        <tr>\n          <td><strong>EER height<\/strong><\/td>\n          <td>40\u2013100 \u00b5m<\/td>\n          <td>30\u201380 \u00b5m<\/td>\n          <td>60\u2013150 \u00b5m<\/td>\n          <td>50\u2013150 \u00b5m<\/td>\n        <\/tr>\n        <tr>\n          <td><strong>Waxless required?<\/strong><\/td>\n          <td><span class=\"badge badge-red\">Mandatory<\/span><\/td>\n          <td><span class=\"badge badge-red\">Mandatory<\/span><\/td>\n          <td><span class=\"badge badge-amber\">Strongly preferred<\/span><\/td>\n          <td><span class=\"badge badge-green\">Preferred<\/span><\/td>\n        <\/tr>\n        <tr>\n          <td><strong>Key failure mode<\/strong><\/td>\n          <td>Cleavage fracture<\/td>\n          <td>Cleavage fracture<\/td>\n          <td>Chemical compat.<\/td>\n          <td>TTV drift<\/td>\n        <\/tr>\n        <tr>\n          <td><strong>\u5178\u578b\u5faa\u73af\u5bff\u547d<\/strong><\/td>\n          <td>80-150<\/td>\n          <td>100\u2013180<\/td>\n          <td>80\u2013160<\/td>\n          <td>100-200<\/td>\n        <\/tr>\n      <\/tbody>\n    <\/table>\n  <\/div>\n\n  <hr class=\"divider\" \/>\n\n  <!-- \u2550\u2550\u2550 SECTION 9 \u2550\u2550\u2550 -->\n  <h2 id=\"handling\">Handling &amp; Loading Best Practices for Fragile Substrates<\/h2>\n\n  <p>Template design sets the mechanical boundary conditions for wafer polishing, but in-process handling \u2014 how the wafer is loaded into the template, transported to the polisher, and unloaded after polishing \u2014 is equally important for fragile III-V substrates. The best-engineered template cannot prevent breakage from handling errors that apply stress concentrations exceeding the wafer&#8217;s fracture toughness threshold.<\/p>\n\n  <h3>Loading Protocol for GaAs and InP<\/h3>\n  <p>Wet the backing pad with DI water as for standard waxless loading, but apply additional care to the wafer placement step. Lower the wafer into the work hole vertically rather than sliding it laterally \u2014 lateral placement drags the wafer edge across the work-hole wall and is the most common source of edge chips in fragile substrate loading. Use vacuum tweezers rated for the wafer diameter; finger contact with GaAs or InP wafers during loading introduces point-contact stress that can initiate subsurface cracks that become visible only after polishing. Allow 5\u201310 seconds of gentle pressure after placement to ensure the capillary adhesion is fully established before the assembly is moved.<\/p>\n\n  <h3>Release Protocol After Polishing<\/h3>\n  <p>Release GaAs and InP wafers by allowing the backing pad to partially dry \u2014 do not use mechanical release (spatula at the edge) for III-V substrates, as the edge-lift force required is sufficient to initiate cleavage-plane fractures. If the pad is slow to dry, a brief application of low-pressure compressed nitrogen at the wafer edge can accelerate the drying without applying mechanical stress. Once the wafer releases freely, transfer immediately to the post-polish cleaning bath without intermediate dry storage, as GaAs and InP surfaces oxidize rapidly in air and benefit from continuous wet processing.<\/p>\n\n  <div class=\"callout tip\">\n    <span class=\"callout-icon\">\ud83d\udca1<\/span>\n    <div class=\"callout-body\">\n      <strong>Work-Hole Edge Chamfer for Fragile Substrates<\/strong>\n      Specify a work-hole edge chamfer on templates for GaAs and InP \u2014 a small (0.1\u20130.2 mm) 45\u00b0 chamfer at the top of the work-hole opening. This chamfer eliminates the sharp corner at the work-hole entry that is otherwise the primary contact point during wafer loading, distributing any inadvertent edge contact over a larger area and reducing the peak stress below the fracture initiation threshold. This is a standard feature on Jizhi&#8217;s compound semiconductor templates and adds no lead time or cost premium.\n    <\/div>\n  <\/div>\n\n  <!-- Related articles -->\n  <div class=\"related-box\">\n    <h3>\ud83d\udcd6 \u76f8\u5173\u6280\u672f\u6587\u7ae0<\/h3>\n    <p>Complete your compound semiconductor polishing template knowledge with these guides:<\/p>\n    <div class=\"related-links\">\n      <a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/Polishing-Templates-for-Semiconductor-Silicon-Wafer-Processing\/\" target=\"_blank\">\u629b\u5149\u6a21\u677f\uff1a\u5b8c\u6574\u6307\u5357<\/a>\n      <a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/Waxless-Polishing-Templates-vs-Wax-Mounting-Cost-Quality-Process-Comparison\/\" target=\"_blank\">\u65e0\u8721\u5b89\u88c5\u4e0e\u6709\u8721\u5b89\u88c5<\/a>\n      <a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/FR-4-vs-G-10-Fiberglass-Polishing-Templates-Material-Properties-Selection-Guide\/\" target=\"_blank\">FR-4 vs G-10 vs CXT \u6750\u6599<\/a>\n      <a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/SiC-Wafer-Polishing-Templates-Chemically-Resistant-Solutions-for-Silicon-Carbide-Processing\/\" target=\"_blank\">\u78b3\u5316\u7845\u629b\u5149\u6a21\u677f<\/a>\n      <a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/Polishing-Templates-for-Glass-Wafers-Ceramic-Substrates-Key-Considerations\/\" target=\"_blank\">\u73bb\u7483\u548c\u9676\u74f7\u57fa\u5e95<\/a>\n      <a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/How-Polishing-Template-Edge-Design-Controls-Wafer-Edge-Profile-Reduces-Edge-Exclusion\/\" target=\"_blank\">\u8fb9\u7f18\u8f6e\u5ed3\u548c EER \u8bbe\u8ba1<\/a>\n      <a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/How-to-Specify-a-Polishing-Template-6-Parameters-Engineers-Must-Define\/\" target=\"_blank\">6 \u53c2\u6570\u89c4\u683c\u6307\u5357<\/a>\n    <\/div>\n  <\/div>\n\n  <hr class=\"divider\" \/>\n\n  <!-- \u2550\u2550\u2550 FAQ \u2550\u2550\u2550 -->\n  <h2 id=\"faq\">\u5e38\u89c1\u95ee\u9898<\/h2>\n\n  <div class=\"faq-item\">\n    <div class=\"faq-q\">Why do GaAs wafers require different polishing templates than silicon?<\/div>\n    <div class=\"faq-a\">GaAs has fracture toughness approximately half that of silicon (0.44 vs 0.7\u20130.9 MPa\u00b7m\u00bd) and well-defined {110} cleavage planes, making it highly susceptible to edge chipping and wafer cracking under stress concentrations. GaAs polishing uses bromine-based acidic slurries incompatible with FR-4 carrier plates. Wax mounting&#8217;s 70\u201385\u00b0C thermal cycle creates differential thermal expansion stress at the GaAs-block interface that is a primary source of cleavage fractures \u2014 making waxless templates effectively mandatory. These factors together require a fundamentally different template specification: softer backing pads, tighter work-hole clearance, chemically resistant carrier plate, and conservative EER design.<\/div>\n  <\/div>\n\n  <div class=\"faq-item\">\n    <div class=\"faq-q\">What backing pad hardness is recommended for GaAs and InP polishing?<\/div>\n    <div class=\"faq-a\">Shore A 30\u201350 (soft) for GaAs, and Shore A 25\u201345 (ultra-soft) for InP. These soft specifications are lower than any silicon polishing application because the primary design goal is stress concentration prevention rather than pressure uniformity optimization. A medium-hard pad (Shore A 60\u201370, correct for silicon) transmits carrier head pressure non-uniformities to the wafer edge at magnitudes sufficient to initiate cleavage fractures in GaAs at standard process pressures. For InP, which has even lower fracture toughness, an even softer pad is required.<\/div>\n  <\/div>\n\n  <div class=\"faq-item\">\n    <div class=\"faq-q\">What slurry chemistry is used for GaAs polishing and how does it affect template material?<\/div>\n    <div class=\"faq-a\">GaAs polishing uses bromine-based slurries \u2014 bromine-methanol (0.05\u20130.5% Br\u2082 in methanol) or sodium hypobromite \u2014 at pH 4\u20137. Bromine is a strong oxidant that attacks the epoxy resin in FR-4 carrier plates within 20\u201330 polishing cycles, causing surface degradation and delamination. G-10 provides marginal improvement. CXT-grade carrier plate material, with its inert seamless matrix, is the recommended choice for production GaAs polishing at cycle counts above 30.<\/div>\n  <\/div>\n\n  <div class=\"faq-item\">\n    <div class=\"faq-q\">Can sapphire wafer polishing use standard FR-4 polishing templates?<\/div>\n    <div class=\"faq-a\">Only for alkaline final-polish slurries (pH 8\u201312, colloidal silica). For the acidic diamond slurries (pH 3\u20136) used in sapphire coarse and intermediate polishing steps, FR-4 is chemically incompatible. G-10 is acceptable for moderate cycle counts at pH 5\u20136, but CXT-grade is recommended for production cycle counts above 50 with acid slurry. Sapphire&#8217;s high hardness also requires harder backing pads (Shore A 60\u201375) than the FR-4 template&#8217;s standard pad specification, so a substrate-specific template specification is required regardless of carrier plate material choice.<\/div>\n  <\/div>\n\n  <div class=\"faq-item\">\n    <div class=\"faq-q\">What is the work-hole edge chamfer and why is it important for III-V substrates?<\/div>\n    <div class=\"faq-a\">A work-hole edge chamfer is a small (0.1\u20130.2 mm) 45\u00b0 bevel machined at the top edge of the work-hole opening. Without this chamfer, the work-hole entry has a sharp corner that becomes the primary contact point when the wafer is lowered into the cavity during loading. For GaAs and InP, this sharp-corner contact concentrates the placement force into a small area of the wafer edge, potentially exceeding the local fracture toughness threshold. The chamfer distributes this contact force over a larger area, reducing peak stress below the fracture initiation level. It is a standard feature on Jizhi compound semiconductor templates.<\/div>\n  <\/div>\n\n  <!-- CTA -->\n  <div class=\"cta-banner\">\n    <h2>Get a Quote for Your Compound Semiconductor Polishing Templates<\/h2>\n    <p>Tell us your substrate type (GaAs \/ InP \/ Sapphire), wafer diameter, slurry chemistry, and process pressure \u2014 our engineering team will configure the right template specification and provide a quote within 48 hours.<\/p>\n    <a href=\"https:\/\/jeez-semicon.com\/zh\/contact\/\" class=\"cta-btn\" target=\"_blank\">\n      \u8054\u7cfb\u6211\u4eec\u83b7\u53d6\u62a5\u4ef7 \u2192\n    <\/a>\n  <\/div>\n\n  <a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/Polishing-Templates-for-Semiconductor-Silicon-Wafer-Processing\/\" target=\"_blank\" class=\"back-to-pillar\">\n    \u8fd4\u56de\u629b\u5149\u6a21\u677f\uff1a\u5b8c\u6574\u6307\u5357\n  <\/a>\n\n<\/div>\n<\/body>\n<\/html>","protected":false},"excerpt":{"rendered":"<p>Compound Semiconductor Substrates III-V compound semiconductors and sapphire demand polishing templates that silicon engineers rarely encounter: softer pads to protect fracture-prone crystals, chemically resistant carrier plates for bromine and acid  &#8230;<\/p>","protected":false},"author":1,"featured_media":1689,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[9,59],"tags":[],"class_list":["post-1661","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-blog","category-industry"],"acf":[],"_links":{"self":[{"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/posts\/1661","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/comments?post=1661"}],"version-history":[{"count":2,"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/posts\/1661\/revisions"}],"predecessor-version":[{"id":1663,"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/posts\/1661\/revisions\/1663"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/media\/1689"}],"wp:attachment":[{"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/media?parent=1661"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/categories?post=1661"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/tags?post=1661"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}