{"id":1758,"date":"2026-04-07T15:54:42","date_gmt":"2026-04-07T07:54:42","guid":{"rendered":"https:\/\/jeez-semicon.com\/?p=1758"},"modified":"2026-04-07T16:27:40","modified_gmt":"2026-04-07T08:27:40","slug":"what-is-a-cmp-polishing-pad-the-ultimate-guide","status":"publish","type":"post","link":"https:\/\/jeez-semicon.com\/zh\/blog\/what-is-a-cmp-polishing-pad-the-ultimate-guide\/","title":{"rendered":"What Is a CMP Polishing Pad? The Ultimate Guide"},"content":{"rendered":"<!-- ============================================================\n     CLUSTER 1 \u2014 What Is a CMP Polishing Pad? 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rgba(255,255,255,.55);margin-left:12px}\n.jz-btn-outline:hover{background:rgba(255,255,255,.1);color:#fff}\n\n\/* FAQ *\/\n.jz-faq{margin:28px 0}\n.jz-faq-item{border:1px solid var(--c-border);border-radius:var(--radius);margin-bottom:12px;overflow:hidden;background:var(--c-surface)}\n.jz-faq-q{padding:16px 20px;font-weight:600;font-size:15px;color:var(--c-primary-dark);display:flex;justify-content:space-between;align-items:center}\n.jz-faq-q::after{content:'+';font-size:20px;font-weight:300;color:var(--c-accent);flex-shrink:0}\n.jz-faq-a{padding:0 20px 16px;font-size:15px;color:var(--c-muted);line-height:1.7}\n\n\/* Definition box *\/\n.jz-definition{background:var(--c-surface);border:2px solid var(--c-primary);border-radius:var(--radius-lg);padding:28px 32px;margin:32px 0;position:relative}\n.jz-definition-label{position:absolute;top:-13px;left:24px;background:var(--c-primary);color:#fff;font-size:11px;font-weight:700;letter-spacing:.1em;text-transform:uppercase;padding:3px 12px;border-radius:4px;font-family:var(--font-mono)}\n.jz-definition p{font-size:17px;line-height:1.75;color:var(--c-text);margin-bottom:0;font-style:italic}\n\n@media(max-width:640px){\n  .jz-hero{padding:36px 24px 32px}\n  .jz-cta-banner{padding:32px 22px}\n  .jz-related{padding:24px 18px}\n  .jz-btn-outline{margin-left:0;margin-top:10px;display:inline-block}\n}\n<\/style>\n\n<div class=\"jz-art\">\n\n<!-- Back to Pillar -->\n<a class=\"jz-back\" href=\"https:\/\/jeez-semicon.com\/zh\/blog\/CMP-Polishing-Pads-The-Complete-Guide\/\" target=\"_blank\">Back to CMP Polishing Pads: The Complete Guide<\/a>\n\n<!-- Hero -->\n<div class=\"jz-hero\">\n  <div class=\"jz-hero-kicker\">Jizhi Electronic Technology \u2014 Fundamentals Series<\/div>\n  <p class=\"jz-hero-lead\">A clear, technically grounded explanation of CMP polishing pads \u2014 what they are, what they are made of, how they fit into the semiconductor fabrication process, and why they are among the most consequential consumables in modern chip manufacturing.<\/p>\n  <div class=\"jz-hero-meta\">\n    <span>\ud83d\udcc5 April 2026<\/span>\n    <span>\u23f1 14 min read<\/span>\n    <span>\ud83c\udfed Jizhi Electronic Technology Co., Ltd.<\/span>\n  <\/div>\n<\/div>\n\n<!-- Tags -->\n<div class=\"jz-tags\">\n  <span class=\"jz-tag\">CMP Polishing Pad<\/span>\n  <span class=\"jz-tag\">What Is CMP<\/span>\n  <span class=\"jz-tag\">Chemical Mechanical Planarization<\/span>\n  <span class=\"jz-tag\">Semiconductor Consumables<\/span>\n  <span class=\"jz-tag\">Wafer Fabrication<\/span>\n  <span class=\"jz-tag\">Beginner Guide<\/span>\n<\/div>\n\n<!-- Trust bar -->\n<div class=\"jz-trust\">\n  <div class=\"jz-trust-badge\">R&amp;D<br>Verified<\/div>\n  <div class=\"jz-trust-text\">\n    <strong>Written by Jizhi Electronic Technology Co., Ltd.<\/strong> \u2014 manufacturer and supplier of CMP polishing pads for wafer fabs, semiconductor equipment makers, research institutions, and OEM manufacturers. Technical content reviewed by our in-house process engineering team. April 2026.\n  <\/div>\n<\/div>\n\n<!-- TOC -->\n<div class=\"jz-toc\">\n  <div class=\"jz-toc-title\">\ud83d\udccb \u76ee\u5f55<\/div>\n  <ol>\n    <li><a href=\"#definition\">Defining a CMP Polishing Pad<\/a><\/li>\n    <li><a href=\"#context\">CMP in Semiconductor Manufacturing<\/a><\/li>\n    <li><a href=\"#anatomy\">Anatomy of a CMP Polishing Pad<\/a><\/li>\n    <li><a href=\"#types\">The Four Main Pad Types<\/a><\/li>\n    <li><a href=\"#role\">The Pad&#8217;s Role in the Polishing System<\/a><\/li>\n    <li><a href=\"#key-properties\">Key Physical Properties Explained<\/a><\/li>\n    <li><a href=\"#lifespan\">Pad Lifespan and End-of-Life<\/a><\/li>\n    <li><a href=\"#history\">A Brief History of CMP Pad Development<\/a><\/li>\n    <li><a href=\"#faq\">FAQ<\/a><\/li>\n  <\/ol>\n<\/div>\n\n<!-- Intro -->\n<p>If you have ever asked &#8220;what is a CMP polishing pad?&#8221; \u2014 whether you are a process engineer new to planarization, a procurement professional evaluating suppliers, or a researcher entering the semiconductor materials field \u2014 this guide provides the definitive, technically accurate answer. We cover not just the object itself but the broader context that makes it so important: why semiconductor devices need planarization, how the pad interacts with slurry and wafer to achieve atomically smooth surfaces, and what differentiates one pad from another.<\/p>\n\n<p>CMP (chemical mechanical planarization, sometimes called chemical mechanical polishing) polishing pads are the workhorses of modern chip manufacturing. They are used at dozens of steps in the fabrication of logic chips, memory devices, power semiconductors, and compound semiconductor substrates. Yet they remain largely invisible to the public \u2014 unrecognized consumables inside the multi-billion-dollar machines that make the electronics era possible.<\/p>\n\n<div class=\"jz-stats\">\n  <div class=\"jz-stat\"><div class=\"jz-stat-num\">30+<\/div><div class=\"jz-stat-label\">CMP steps in a leading-edge logic process flow (5 nm and below)<\/div><\/div>\n  <div class=\"jz-stat\"><div class=\"jz-stat-num\">300 mm<\/div><div class=\"jz-stat-label\">Standard wafer diameter for high-volume logic and memory production<\/div><\/div>\n  <div class=\"jz-stat\"><div class=\"jz-stat-num\">&lt;1 nm<\/div><div class=\"jz-stat-label\">Surface roughness (Ra) target for advanced node dielectric CMP<\/div><\/div>\n  <div class=\"jz-stat\"><div class=\"jz-stat-num\">~40%<\/div><div class=\"jz-stat-label\">Share of CMP consumable spend attributable to polishing pads at a typical fab<\/div><\/div>\n<\/div>\n\n<!-- \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 SECTION 1 \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 -->\n<h2 id=\"definition\">1. Defining a CMP Polishing Pad<\/h2>\n\n<div class=\"jz-definition\">\n  <div class=\"jz-definition-label\">Definition<\/div>\n  <p>A CMP polishing pad is a precision-engineered consumable disc, typically made from polyurethane or a polyurethane-composite material, that is mounted on the rotating platen of a chemical mechanical planarization tool. It provides the working surface against which a semiconductor wafer is pressed and rotated in the presence of a chemically reactive abrasive slurry, removing material from the wafer surface to achieve nanometer-scale planarity.<\/p>\n<\/div>\n\n<p>Breaking that definition down:<\/p>\n\n<div class=\"jz-card-grid\">\n  <div class=\"jz-card\">\n    <div class=\"jz-card-icon\">\ud83d\udd35<\/div>\n    <h4>Precision-engineered<\/h4>\n    <p>Every physical property of the pad \u2014 hardness, porosity, surface texture, groove geometry \u2014 is deliberately controlled during manufacturing, not incidental. Small changes in pad properties directly shift process outcomes.<\/p>\n  <\/div>\n  <div class=\"jz-card\">\n    <div class=\"jz-card-icon\">\ud83d\udd04<\/div>\n    <h4>Consumable disc<\/h4>\n    <p>Pads are single-use items that wear out over hundreds to thousands of wafer polishing cycles and must be periodically replaced \u2014 a significant and recurring cost in fab operations.<\/p>\n  <\/div>\n  <div class=\"jz-card\">\n    <div class=\"jz-card-icon\">\u2699\ufe0f<\/div>\n    <h4>Mounted on a rotating platen<\/h4>\n    <p>The pad is bonded (via pressure-sensitive adhesive) to a large rotating platen \u2014 typically 20\u201330 inches in diameter on 300 mm production tools \u2014 which provides the controlled rotational motion.<\/p>\n  <\/div>\n  <div class=\"jz-card\">\n    <div class=\"jz-card-icon\">\ud83c\udfaf<\/div>\n    <h4>Nanometer-scale planarity<\/h4>\n    <p>The end goal of CMP is a surface flat enough for the next lithography exposure step \u2014 deviations of even a few nanometers in surface height across a 300 mm wafer can put features outside the depth of focus of the lithography tool.<\/p>\n  <\/div>\n<\/div>\n\n<!-- \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 SECTION 2 \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 -->\n<h2 id=\"context\">2. CMP in Semiconductor Manufacturing: Why Planarization Matters<\/h2>\n\n<p>To understand a CMP polishing pad, you first need to understand the problem it solves. Semiconductor devices are built up in three dimensions by depositing and patterning dozens of thin film layers on a silicon wafer. Each deposition step adds material that conforms to and amplifies the topography already present on the wafer surface. After just a few process layers, the wafer surface is no longer flat \u2014 it has hills and valleys corresponding to underlying device structures, with height variations that can range from a few tens of nanometers to several micrometers.<\/p>\n\n<p>This topography creates two serious manufacturing problems:<\/p>\n\n<div class=\"jz-two-col\">\n  <div class=\"jz-col-box\">\n    <h4>\ud83d\udd2c Lithography Depth of Focus<\/h4>\n    <ul>\n      <li>Modern DUV and EUV lithography tools have extremely shallow depth of focus \u2014 often less than 100 nm for sub-10 nm nodes<\/li>\n      <li>If the wafer surface has height variations larger than the depth of focus, parts of the pattern will be out of focus and print incorrectly<\/li>\n      <li>CMP is the primary technique for flattening the surface between lithography levels, ensuring every exposure prints on a flat, in-focus surface<\/li>\n    <\/ul>\n  <\/div>\n  <div class=\"jz-col-box\">\n    <h4>\ud83d\udd29 Metal Line Continuity<\/h4>\n    <ul>\n      <li>Metal interconnect layers are deposited into trenches and vias etched into dielectric films<\/li>\n      <li>After metal deposition, the surface is covered with excess metal that must be removed \u2014 leaving metal only inside the trenches and vias<\/li>\n      <li>CMP removes the excess metal selectively, leaving a flat surface with embedded metal lines \u2014 a process called damascene metallization<\/li>\n      <li>Without CMP, there would be no reliable way to build multi-level copper interconnects<\/li>\n    <\/ul>\n  <\/div>\n<\/div>\n\n<div class=\"jz-callout info\">\n  <div class=\"jz-callout-icon\">\u2139\ufe0f<\/div>\n  <div class=\"jz-callout-body\">\n    <strong>CMP Was Invented Because Nothing Else Could Solve the Planarity Problem<\/strong>\n    IBM introduced CMP into production IC manufacturing in the early 1990s, specifically to enable the multi-level metal interconnect structures that deep-submicron devices required. Prior planarization techniques \u2014 etch-back, spin-on glass, reflow \u2014 could partially flatten local topography but could not achieve the global planarity that sub-0.5 \u00b5m lithography demanded. CMP&#8217;s combination of chemical and mechanical action proved uniquely capable of achieving global planarization, and the pad-slurry system at its heart has been refined continuously ever since.\n  <\/div>\n<\/div>\n\n<!-- \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 SECTION 3 \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 -->\n<h2 id=\"anatomy\">3. Anatomy of a CMP Polishing Pad<\/h2>\n\n<p>A CMP polishing pad is deceptively simple in appearance \u2014 a flat disc of polymeric material, typically 20\u201330 inches in diameter and 1\u20133 mm thick. But its internal structure is precisely engineered at the microscale. Understanding the anatomy of a pad explains why not all pads perform the same way, even when made from superficially similar materials.<\/p>\n\n<h3>The Polymer Matrix<\/h3>\n<p>The bulk of a standard CMP pad consists of a closed-cell polyurethane foam. Polyurethane (PU) is synthesized by reacting a diisocyanate with a polyol in the presence of a chain extender, forming a cross-linked polymer network. The mechanical properties \u2014 stiffness, hardness, elasticity, creep resistance \u2014 are tunable over a wide range by adjusting the PU formulation. For CMP pads, the key control parameters are the isocyanate-to-polyol ratio (NCO\/OH index), the type of polyol (polyester vs. polyether vs. polycarbonate), and the cross-link density.<\/p>\n\n<h3>The Pore Structure<\/h3>\n<p>Within the PU matrix, hollow microspheres (typically 20\u201350 \u00b5m in diameter) are dispersed during the casting process. These microspheres expand or remain intact during curing, creating a network of closed-cell micro-pores throughout the pad volume. The pores serve a critical functional role: they act as micro-reservoirs that hold slurry at the pad-wafer interface during polishing. As the pad surface wears during conditioning, new pores are exposed, continuously replenishing the surface&#8217;s slurry-holding capacity.<\/p>\n\n<div class=\"jz-callout tip\">\n  <div class=\"jz-callout-icon\">\ud83d\udca1<\/div>\n  <div class=\"jz-callout-body\">\n    <strong>Pore Size Distribution Is a Quality Fingerprint<\/strong>\n    The diameter, density, and spatial uniformity of pores are among the tightest quality control parameters in CMP pad manufacturing. A wide pore size distribution leads to variable slurry uptake across the pad surface, which translates directly to within-wafer removal rate non-uniformity. Premium pads \u2014 and those from suppliers with robust QC programs like Jizhi Electronic Technology \u2014 specify and test pore size distribution from every production lot.\n  <\/div>\n<\/div>\n\n<h3>The Surface Texture and Asperities<\/h3>\n<p>The polishing surface of the pad is not perfectly smooth. At the microscale, it is covered with asperities \u2014 small protrusions of polymer material that constitute the true contact points with the wafer. Asperity height, density, and sharpness determine how effectively the pad transmits force to abrasive particles in the slurry and how aggressively it abrades the wafer surface. Fresh pads have a relatively compact, smooth skin layer that must be removed during the break-in (conditioning) process to expose the underlying asperity-rich sub-surface.<\/p>\n\n<h3>The Groove Network<\/h3>\n<p>Machined into the top surface of the pad is a network of grooves \u2014 channels typically 0.3\u20130.8 mm deep and 0.25\u20131.0 mm wide, arranged in patterns such as concentric rings (K-groove), XY grids, or Archimedean spirals. Grooves serve as highways for slurry transport: they channel fresh slurry from the pad edge to the center of the wafer-pad contact zone and carry spent slurry and removal byproducts outward and away. Groove design is a major differentiator between pad types \u2014 for a full analysis, see our article on <a class=\"jz-link-chip\" href=\"https:\/\/jeez-semicon.com\/zh\/blog\/CMP-Pad-Groove-Design-and-Slurry-Distribution\/\" target=\"_blank\">CMP Pad Groove Design and Slurry Distribution<\/a>.<\/p>\n\n<h3>The Backing Layer and PSA<\/h3>\n<p>Most production pads include a backing layer \u2014 a thin film of polyethylene terephthalate (PET) or a foam subpad material \u2014 laminated to the bottom of the polishing layer. The backing provides dimensional stability and a flat mounting surface. A pressure-sensitive adhesive (PSA) on the bottom of the backing bonds the pad to the platen. PSA quality and peel strength are critical: pad delamination during polishing is a serious process excursion that can scratch or contaminate wafers.<\/p>\n\n<!-- \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 SECTION 4 \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 -->\n<h2 id=\"types\">4. The Four Main Types of CMP Polishing Pads<\/h2>\n\n<p>CMP polishing pads are not one-size-fits-all. The industry has developed four distinct pad architectures, each optimized for different aspects of the planarization challenge. For a detailed comparison of pad selection criteria, see our guide: <a class=\"jz-link-chip\" href=\"https:\/\/jeez-semicon.com\/zh\/blog\/Hard-vs-Soft-CMP-Polishing-Pads-Selection-Guide\/\" target=\"_blank\">Hard vs. Soft CMP Polishing Pads: Selection Guide<\/a>.<\/p>\n\n<div class=\"jz-table-wrap\">\n  <table class=\"jz-table\">\n    <thead>\n      <tr>\n        <th>Type<\/th>\n        <th>Shore D Hardness<\/th>\n        <th>Primary Strength<\/th>\n        <th>\u5178\u578b\u7528\u4f8b<\/th>\n      <\/tr>\n    <\/thead>\n    <tbody>\n      <tr>\n        <td><strong>Hard polyurethane (Type I)<\/strong><\/td>\n        <td>55\u201365<\/td>\n        <td>High planarization efficiency, stable MRR<\/td>\n        <td>Oxide ILD, W plug, STI \u2014 any step needing aggressive step-height removal<\/td>\n      <\/tr>\n      <tr>\n        <td><strong>Soft polyurethane \/ subpad (Type II)<\/strong><\/td>\n        <td>30\u201345<\/td>\n        <td>Within-wafer uniformity, low shear on fragile films<\/td>\n        <td>Cu BEOL, low-k dielectric, barrier metal, final finishing<\/td>\n      <\/tr>\n      <tr>\n        <td><strong>Composite \/ stacked (Type III)<\/strong><\/td>\n        <td>Combined stack: effective 45\u201358<\/td>\n        <td>Best of both: planarization efficiency + uniformity<\/td>\n        <td>300 mm production with bow\/warp correction requirements<\/td>\n      <\/tr>\n      <tr>\n        <td><strong>Specialty \/ poreless (Type IV)<\/strong><\/td>\n        <td>60\u201370<\/td>\n        <td>Ultra-low defect density, highly consistent Kp<\/td>\n        <td>Advanced nodes (&lt;7 nm), EUV-layer CMP, SiC substrates<\/td>\n      <\/tr>\n    <\/tbody>\n  <\/table>\n<\/div>\n\n<p>Jizhi Electronic Technology manufactures all four pad types, with in-house R&amp;D capabilities for custom formulations targeting non-standard substrates including SiC, GaN, and sapphire. For our SiC-specific pad technology, see: <a class=\"jz-link-chip\" href=\"https:\/\/jeez-semicon.com\/zh\/blog\/SiC-CMP-Polishing-Pads-for-Third-Generation-Semiconductors\/\" target=\"_blank\">SiC CMP Polishing Pads for Third-Generation Semiconductors<\/a>.<\/p>\n\n<!-- \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 SECTION 5 \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 -->\n<h2 id=\"role\">5. The Pad&#8217;s Role in the Complete CMP Polishing System<\/h2>\n\n<p>A CMP polishing pad does not operate in isolation. It is one component in a tightly coupled system, and its performance cannot be fully understood apart from the other elements. The four primary system components are:<\/p>\n\n<div class=\"jz-steps\">\n  <div class=\"jz-step\">\n    <div class=\"jz-step-num\">1<\/div>\n    <div class=\"jz-step-body\">\n      <h4>The Polishing Tool (CMP Equipment)<\/h4>\n      <p>Industrial CMP tools from Applied Materials (Reflexion), Ebara (FREX), or SKC (now Kctech) provide the mechanical motion: counter-rotating platen and carrier head, controlled down-force (1\u20136 psi), and slurry delivery system. The pad is mounted on the platen. Tool geometry and process recipe parameters (pressure, velocity, slurry flow rate) define the operating conditions the pad must perform under.<\/p>\n    <\/div>\n  <\/div>\n  <div class=\"jz-step\">\n    <div class=\"jz-step-num\">2<\/div>\n    <div class=\"jz-step-body\">\n      <h4>The CMP Slurry<\/h4>\n      <p>Slurry is a colloidal suspension of abrasive particles (silica, ceria, alumina, or diamond, depending on the application) in a chemically reactive aqueous medium. The slurry is continuously dispensed onto the pad surface during polishing. Slurry chemistry \u2014 pH, oxidizer type and concentration, complexing agents \u2014 controls the chemical softening of the target film, while the abrasive particles provide mechanical cutting. Pad-slurry compatibility is critical: the wrong combination can cause MRR collapse or defect spikes. To understand how slurry and pad interact, see: <a class=\"jz-link-chip\" href=\"https:\/\/jeez-semicon.com\/zh\/blog\/How-CMP-Polishing-Pads-Work\/\" target=\"_blank\">How CMP Polishing Pads Work<\/a>.<\/p>\n    <\/div>\n  <\/div>\n  <div class=\"jz-step\">\n    <div class=\"jz-step-num\">3<\/div>\n    <div class=\"jz-step-body\">\n      <h4>The Polishing Pad<\/h4>\n      <p>The pad is the mechanical intermediary between the tool and the wafer. It transmits the applied force, distributes the slurry, and provides the asperity surface that engages abrasive particles with the wafer film. The pad&#8217;s hardness, porosity, and groove pattern determine how effectively it does each of these things.<\/p>\n    <\/div>\n  <\/div>\n  <div class=\"jz-step\">\n    <div class=\"jz-step-num\">4<\/div>\n    <div class=\"jz-step-body\">\n      <h4>The Pad Conditioner<\/h4>\n      <p>A diamond disk dresser, pressed against the pad surface either during or between wafer polishes, continuously abrades the pad surface to remove glazed material, re-open pores, and restore the asperity height distribution. Without conditioning, pad performance decays rapidly. The conditioning process is inseparable from pad management \u2014 for the full picture, read: <a class=\"jz-link-chip\" href=\"https:\/\/jeez-semicon.com\/zh\/blog\/CMP-Pad-Conditioning-and-Lifespan-Management\/\" target=\"_blank\">CMP Pad Conditioning and Lifespan Management<\/a>.<\/p>\n    <\/div>\n  <\/div>\n<\/div>\n\n<!-- \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 SECTION 6 \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 -->\n<h2 id=\"key-properties\">6. Key Physical Properties of a CMP Polishing Pad \u2014 Explained<\/h2>\n\n<p>When engineers specify or compare CMP polishing pads, they use a set of standard physical property measurements. Understanding what these properties mean \u2014 and why they matter \u2014 is essential for anyone selecting or qualifying a pad. For a deep dive into how these properties influence material removal rate, see: <a class=\"jz-link-chip\" href=\"https:\/\/jeez-semicon.com\/zh\/blog\/CMP-Material-Removal-Rate-and-Pad-Parameters\/\" target=\"_blank\">CMP Material Removal Rate and Pad Parameters<\/a>.<\/p>\n\n<div class=\"jz-table-wrap\">\n  <table class=\"jz-table\">\n    <thead>\n      <tr>\n        <th>\u8d22\u4ea7<\/th>\n        <th>\u6d4b\u91cf\u65b9\u6cd5<\/th>\n        <th>\u5178\u578b\u8303\u56f4<\/th>\n        <th>\u8fc7\u7a0b\u5f71\u54cd<\/th>\n      <\/tr>\n    <\/thead>\n    <tbody>\n      <tr>\n        <td><strong>Hardness (Shore D)<\/strong><\/td>\n        <td>ASTM D2240 durometer<\/td>\n        <td>30\u201370 Shore D<\/td>\n        <td>Controls asperity contact force, planarization efficiency, and scratch risk. Higher = more aggressive.<\/td>\n      <\/tr>\n      <tr>\n        <td><strong>Compressibility (%)<\/strong><\/td>\n        <td>% thickness change under 25 kPa load<\/td>\n        <td>0.5\u20138%<\/td>\n        <td>Governs wafer-scale conformance. Higher compressibility improves edge-to-center uniformity on bowed wafers.<\/td>\n      <\/tr>\n      <tr>\n        <td><strong>Elastic recovery (%)<\/strong><\/td>\n        <td>% recovery after load removal<\/td>\n        <td>55\u201390%<\/td>\n        <td>Low recovery = creep and pad drift during long polishing runs, leading to MRR drift over a campaign.<\/td>\n      <\/tr>\n      <tr>\n        <td><strong>Pore size (\u00b5m, mean)<\/strong><\/td>\n        <td>Optical cross-section image analysis<\/td>\n        <td>20\u201380 \u00b5m<\/td>\n        <td>Larger pores increase slurry retention but reduce contact area. Must be matched to slurry particle size.<\/td>\n      <\/tr>\n      <tr>\n        <td><strong>Surface roughness (Ra)<\/strong><\/td>\n        <td>Profilometer or AFM on conditioned surface<\/td>\n        <td>1\u201310 \u00b5m (conditioned)<\/td>\n        <td>Higher Ra = more asperities = higher MRR and higher scratch risk. Controlled via conditioning protocol.<\/td>\n      <\/tr>\n      <tr>\n        <td><strong>\u539a\u5ea6\uff08\u6beb\u7c73\uff09<\/strong><\/td>\n        <td>Contact gauge, 5-point measurement<\/td>\n        <td>1.2\u20133.0 mm<\/td>\n        <td>Determines total usable pad life. Minimum usable thickness (end-of-life) is typically 0.5\u20130.8 mm above backing.<\/td>\n      <\/tr>\n      <tr>\n        <td><strong>Groove depth \/ width (mm)<\/strong><\/td>\n        <td>Profilometer trace across groove cross-section<\/td>\n        <td>Depth: 0.3\u20130.8 mm; Width: 0.25\u20131.0 mm<\/td>\n        <td>Controls slurry transport rate, uniformity of slurry film, and thermal dissipation. See groove design guide.<\/td>\n      <\/tr>\n    <\/tbody>\n  <\/table>\n<\/div>\n\n<div class=\"jz-callout warn\">\n  <div class=\"jz-callout-icon\">\u26a0\ufe0f<\/div>\n  <div class=\"jz-callout-body\">\n    <strong>No Single Property Predicts Performance \u2014 Context Is Everything<\/strong>\n    A pad with Shore D 60 hardness is not universally &#8220;better&#8221; or &#8220;worse&#8221; than one at Shore D 45. Performance is determined by the interaction of all pad properties with the specific slurry chemistry, tool configuration, and target film. Always evaluate pads through process characterization on your actual application, not from spec sheets alone. Jizhi&#8217;s application engineering team provides characterization data packages for each pad-slurry combination we supply.\n  <\/div>\n<\/div>\n\n<!-- \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 SECTION 7 \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 -->\n<h2 id=\"lifespan\">7. Pad Lifespan, End-of-Life Indicators, and Replacement<\/h2>\n\n<p>A CMP polishing pad is a consumable with a finite and measurable useful life. Understanding how pad performance evolves over its lifetime \u2014 and recognizing the indicators that signal end-of-life \u2014 is as important as selecting the right pad in the first place.<\/p>\n\n<h3>The Three Phases of Pad Life<\/h3>\n\n<div class=\"jz-steps\">\n  <div class=\"jz-step\">\n    <div class=\"jz-step-num\">1<\/div>\n    <div class=\"jz-step-body\">\n      <h4>Break-In Phase (Wafers 1\u201350 approximately)<\/h4>\n      <p>The pad surface skin is progressively removed by conditioning, exposing the asperity-rich sub-surface. Removal rate rises from a low initial value to a stable working level. This phase produces high process variability and should be performed using dummy (non-product) wafers or low-value monitor wafers. Skipping proper break-in is one of the most common causes of early-pad-life yield excursions.<\/p>\n    <\/div>\n  <\/div>\n  <div class=\"jz-step\">\n    <div class=\"jz-step-num\">2<\/div>\n    <div class=\"jz-step-body\">\n      <h4>Stable Working Phase (Majority of Pad Life)<\/h4>\n      <p>The pad delivers consistent, repeatable removal rates and within-wafer uniformity. Conditioning maintains the asperity surface in a stable state. This is the phase where production wafers should be polished. The duration of this phase \u2014 measured in wafer count \u2014 is the primary pad life metric.<\/p>\n    <\/div>\n  <\/div>\n  <div class=\"jz-step\">\n    <div class=\"jz-step-num\">3<\/div>\n    <div class=\"jz-step-body\">\n      <h4>End-of-Life Phase<\/h4>\n      <p>As total pad thickness decreases toward the minimum usable threshold, the pad&#8217;s mechanical response changes \u2014 reduced compressibility, altered asperity distribution \u2014 leading to drifting removal rate and degraded uniformity. Key end-of-life signals: MRR decline &gt;15% from stable-state baseline; WIWNU increase &gt;2% (1\u03c3); pad thickness below minimum specification; increasing scratch density on post-CMP inspection.<\/p>\n    <\/div>\n  <\/div>\n<\/div>\n\n<!-- \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 SECTION 8 \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 -->\n<h2 id=\"history\">8. A Brief History of CMP Pad Development<\/h2>\n\n<p>The history of CMP polishing pads mirrors the history of semiconductor device scaling \u2014 each new generation of technology has demanded something the existing pad could not fully deliver, driving a new wave of materials innovation.<\/p>\n\n<h3>1990s \u2014 The Birth of Production CMP<\/h3>\n<p>IBM&#8217;s introduction of CMP for inter-layer dielectric planarization at the 0.35 \u00b5m node catalyzed a new industry. The first production pads were non-woven fiber composites \u2014 essentially industrial polishing felts \u2014 adapted from the optics and magnetic disk polishing industries. These early pads delivered acceptable results for oxide CMP at mature design rules but lacked the hardness and uniformity control needed for the decade ahead.<\/p>\n\n<h3>Late 1990s \u2013 2000s \u2014 Polyurethane Becomes the Standard<\/h3>\n<p>Rodel&#8217;s IC1000\u2122 polyurethane pad established the template that remains dominant today. The closed-cell PU foam provided higher hardness, tunable porosity, and \u2014 critically \u2014 better lot-to-lot consistency than fiber composites. As copper damascene replaced aluminum metallization (starting at the 0.18 \u00b5m node), new softer pad formulations were developed to protect the fragile low-k dielectrics used in Cu BEOL processes.<\/p>\n\n<h3>2010s \u2014 Stacked Pads and Sub-20 nm Challenges<\/h3>\n<p>The transition to 300 mm wafers and sub-20 nm nodes raised the bar for within-wafer uniformity and defect control beyond what single-layer pads could reliably achieve. Two-layer stacked pad configurations \u2014 hard top pad bonded to soft subpad \u2014 became standard at leading fabs. Simultaneously, the emergence of 3D NAND and FinFET architectures introduced new topography profiles and film stacks that required custom groove designs and pad formulations. For information on how today&#8217;s semiconductor fabs use CMP pads across their process flows, visit our overview of <a class=\"jz-link-chip\" href=\"https:\/\/jeez-semicon.com\/zh\/blog\/Semiconductor-CMP-Polishing-Pads\/\" target=\"_blank\">Semiconductor CMP Polishing Pads<\/a>.<\/p>\n\n<h3>2020s \u2014 SiC, Advanced Nodes, and Domestic Supply Chain Development<\/h3>\n<p>The current era is defined by three converging pressures. First, the explosive growth of SiC power devices \u2014 driven by EV adoption and industrial electrification \u2014 demands pad formulations for materials far harder and more chemically inert than silicon. Second, gate-all-around (GAA) transistor architectures at 3 nm and below create planarization challenges \u2014 step heights, film stresses, and selectivity requirements \u2014 that push conventional pads to their limits. Third, geopolitical supply chain diversification is driving rapid qualification of domestically produced pads across Asia, with companies like Jizhi Electronic Technology investing heavily in R&amp;D and manufacturing scale to meet this demand.<\/p>\n\n<p>For material-by-material comparisons of modern pad options, see: <a class=\"jz-link-chip\" href=\"https:\/\/jeez-semicon.com\/zh\/blog\/CMP-Pad-Materials-Polyurethane-vs-Other-Options\/\" target=\"_blank\">CMP Pad Materials: Polyurethane vs Other Options<\/a>.<\/p>\n\n<!-- \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 FAQ \u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550 -->\n<h2>9. Frequently Asked Questions<\/h2>\n\n<div class=\"jz-faq\">\n  <div class=\"jz-faq-item\">\n    <div class=\"jz-faq-q\">Is CMP polishing pad the same as a polishing cloth?<\/div>\n    <div class=\"jz-faq-a\">They are related but distinct. In general optics and metalworking, &#8220;polishing cloth&#8221; refers to any soft textile used with abrasive compounds. CMP polishing pads are a highly specialized subset: precisely formulated polyurethane or composite discs with controlled porosity, hardness, and groove geometry, manufactured to semiconductor-grade specifications. They are engineered for nanometer-precision material removal from silicon and compound semiconductor wafers, not general surface finishing.<\/div>\n  <\/div>\n  <div class=\"jz-faq-item\">\n    <div class=\"jz-faq-q\">What size are CMP polishing pads?<\/div>\n    <div class=\"jz-faq-a\">Pad diameter is determined by the CMP tool&#8217;s platen size. The most common sizes in semiconductor production are: 20-inch (508 mm) diameter pads for 200 mm wafer tools; 30-inch (762 mm) diameter pads for 300 mm wafer production tools (e.g., Applied Materials Reflexion GT); and smaller pads (6\u201312 inch diameter) for R&amp;D, university, and substrate preparation tools. Pad thickness ranges from approximately 1.2 mm (thin pads for soft applications) to 3.0 mm (standard production pads).<\/div>\n  <\/div>\n  <div class=\"jz-faq-item\">\n    <div class=\"jz-faq-q\">Can CMP pads be reused after a polishing run?<\/div>\n    <div class=\"jz-faq-a\">Pads are designed for multiple polishing runs per pad lifetime \u2014 a single pad processes hundreds to over a thousand wafers before reaching end-of-life. However, once a pad reaches its end-of-life criteria (minimum thickness, excessive MRR drift, or unacceptable uniformity), it is replaced entirely. Pads are not &#8220;recharged&#8221; or refurbished \u2014 they are single-use consumables in the sense that each pad serves a defined production campaign from installation to end-of-life and is then discarded.<\/div>\n  <\/div>\n  <div class=\"jz-faq-item\">\n    <div class=\"jz-faq-q\">What is the difference between the polishing pad and the conditioner disk?<\/div>\n    <div class=\"jz-faq-a\">The polishing pad is the consumable surface that contacts the wafer during CMP. The conditioner disk is a separate consumable \u2014 a metallic disk with embedded diamond abrasive particles \u2014 used to abrade and refresh the surface of the polishing pad. The conditioner disk does not contact the wafer directly. Both are consumables that wear out and must be replaced, but on different timescales: a single conditioner disk typically outlasts multiple polishing pads.<\/div>\n  <\/div>\n  <div class=\"jz-faq-item\">\n    <div class=\"jz-faq-q\">Where can I buy CMP polishing pads for production or research use?<\/div>\n    <div class=\"jz-faq-a\">Jizhi Electronic Technology Co., Ltd. supplies CMP polishing pads for production fabs, semiconductor equipment makers, research institutions, and OEM manufacturers. Our product range covers hard polyurethane pads, soft subpads, SiC-specific formulations, and custom OEM solutions. We maintain in-stock inventory for rapid delivery, with standard 3\u20137 day lead times for Asia-Pacific destinations. Visit our <a href=\"https:\/\/jeez-semicon.com\/zh\/semi-categories\/polishing-pad\/\" target=\"_blank\">CMP Polishing Pads product page<\/a> or <a href=\"https:\/\/jeez-semicon.com\/zh\/contact\/\" target=\"_blank\">contact our team<\/a> for pricing and technical consultation.<\/div>\n  <\/div>\n<\/div>\n\n<!-- Related Articles -->\n<div class=\"jz-related\">\n  <div class=\"jz-related-title\">\ud83d\udcda Continue Reading \u2014 CMP Pad Deep Dives<\/div>\n  <div class=\"jz-related-grid\">\n    <div class=\"jz-related-item\">\n      <div class=\"jz-related-cat\">PILLAR \u2014 COMPLETE GUIDE<\/div>\n      <a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/CMP-Polishing-Pads-The-Complete-Guide\/\" target=\"_blank\">CMP Polishing Pads: The Complete Guide<\/a>\n    <\/div>\n    <div class=\"jz-related-item\">\n      <div class=\"jz-related-cat\">FUNDAMENTALS<\/div>\n      <a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/How-CMP-Polishing-Pads-Work\/\" target=\"_blank\">How CMP Polishing Pads Work<\/a>\n    <\/div>\n    <div class=\"jz-related-item\">\n      <div class=\"jz-related-cat\">MATERIALS<\/div>\n      <a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/CMP-Pad-Materials-Polyurethane-vs-Other-Options\/\" target=\"_blank\">CMP Pad Materials: Polyurethane vs Other Options<\/a>\n    <\/div>\n    <div class=\"jz-related-item\">\n      <div class=\"jz-related-cat\">SELECTION<\/div>\n      <a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/Hard-vs-Soft-CMP-Polishing-Pads-Selection-Guide\/\" target=\"_blank\">Hard vs. Soft CMP Polishing Pads: Selection Guide<\/a>\n    <\/div>\n    <div class=\"jz-related-item\">\n      <div class=\"jz-related-cat\">ENGINEERING<\/div>\n      <a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/CMP-Pad-Groove-Design-and-Slurry-Distribution\/\" target=\"_blank\">CMP Pad Groove Design and Slurry Distribution<\/a>\n    <\/div>\n    <div class=\"jz-related-item\">\n      <div class=\"jz-related-cat\">APPLICATIONS<\/div>\n      <a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/SiC-CMP-Polishing-Pads-for-Third-Generation-Semiconductors\/\" target=\"_blank\">SiC CMP Polishing Pads for Third-Generation Semiconductors<\/a>\n    <\/div>\n    <div class=\"jz-related-item\">\n      <div class=\"jz-related-cat\">OPERATIONS<\/div>\n      <a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/CMP-Pad-Conditioning-and-Lifespan-Management\/\" target=\"_blank\">CMP Pad Conditioning and Lifespan Management<\/a>\n    <\/div>\n    <div class=\"jz-related-item\">\n      <div class=\"jz-related-cat\">PROCESS<\/div>\n      <a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/CMP-Material-Removal-Rate-and-Pad-Parameters\/\" target=\"_blank\">CMP Material Removal Rate and Pad Parameters<\/a>\n    <\/div>\n    <div class=\"jz-related-item\">\n      <div class=\"jz-related-cat\">QUALITY<\/div>\n      <a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/CMP-Pad-Defect-Control-Scratches-and-Uniformity\/\" target=\"_blank\">CMP Pad Defect Control: Scratches and Uniformity<\/a>\n    <\/div>\n    <div class=\"jz-related-item\">\n      <div class=\"jz-related-cat\">TECHNOLOGY<\/div>\n      <a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/Poreless-CMP-Pads-vs-Porous-Structure\/\" target=\"_blank\">Poreless CMP Pads vs. Porous Structure<\/a>\n    <\/div>\n    <div class=\"jz-related-item\">\n      <div class=\"jz-related-cat\">SOURCING<\/div>\n      <a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/CMP-Polishing-Pad-Brands-Comparison\/\" target=\"_blank\">CMP Polishing Pad Brands Comparison<\/a>\n    <\/div>\n    <div class=\"jz-related-item\">\n      <div class=\"jz-related-cat\">PROCUREMENT<\/div>\n      <a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/CMP-Polishing-Pad-Price-Factors-and-Buying-Guide\/\" target=\"_blank\">CMP Polishing Pad Price Factors and Buying Guide<\/a>\n    <\/div>\n  <\/div>\n<\/div>\n\n<!-- CTA Banner -->\n<div class=\"jz-cta-banner\">\n  <h2>Looking for a Reliable CMP Polishing Pad Supplier?<\/h2>\n  <p>Jizhi Electronic Technology manufactures hard pads, soft subpads, SiC-specific pads, and custom OEM formulations \u2014 with full technical support, rapid delivery, and batch-level quality documentation. Trusted by wafer fabs, equipment makers, and research institutions worldwide.<\/p>\n  <a class=\"jz-btn jz-btn-white\" href=\"https:\/\/jeez-semicon.com\/zh\/semi-categories\/polishing-pad\/\" target=\"_blank\">Browse CMP Polishing Pads<\/a>\n  <a class=\"jz-btn jz-btn-outline\" href=\"https:\/\/jeez-semicon.com\/zh\/contact\/\" target=\"_blank\">Contact Our Engineers<\/a>\n<\/div>\n\n<!--\n  \u2554\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\n  \u2551  SEO NOTES \u2014 Cluster 1\n  \u2560\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\n  \u2551  Title tag:  What Is a CMP Polishing Pad? The Ultimate Guide (2026) | Jizhi\n  \u2551  Meta desc:  A clear, technically accurate guide to CMP polishing pads \u2014\n  \u2551              definition, anatomy, types, key properties, and history.\n  \u2551              From Jizhi Electronic Technology, trusted CMP pad supplier.\n  \u2551  Focus KW:   what is a CMP polishing pad\n  \u2551  Secondary:  CMP pad definition, chemical mechanical planarization pad,\n  \u2551              CMP pad types, polyurethane polishing pad semiconductor\n  \u2551  Schema:     Article + FAQPage\n  \u2551  Intent:     Informational (primary), Commercial investigation (secondary)\n  \u255a\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\u2550\n-->\n\n<\/div><!-- .jz-art -->","protected":false},"excerpt":{"rendered":"<p>Back to CMP Polishing Pads: The Complete Guide Jizhi Electronic Technology \u2014 Fundamentals Series A clear, technically grounded explanation of CMP polishing pads \u2014 what they are, what they are  &#8230;<\/p>","protected":false},"author":1,"featured_media":1806,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[9,59],"tags":[],"class_list":["post-1758","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-blog","category-industry"],"acf":[],"_links":{"self":[{"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/posts\/1758","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/comments?post=1758"}],"version-history":[{"count":2,"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/posts\/1758\/revisions"}],"predecessor-version":[{"id":1760,"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/posts\/1758\/revisions\/1760"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/media\/1806"}],"wp:attachment":[{"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/media?parent=1758"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/categories?post=1758"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/tags?post=1758"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}