{"id":1798,"date":"2026-04-07T15:56:02","date_gmt":"2026-04-07T07:56:02","guid":{"rendered":"https:\/\/jeez-semicon.com\/?p=1798"},"modified":"2026-04-07T16:29:43","modified_gmt":"2026-04-07T08:29:43","slug":"semiconductor-cmp-polishing-pads-applications-across-the-full-ic-process-flow","status":"publish","type":"post","link":"https:\/\/jeez-semicon.com\/zh\/blog\/semiconductor-cmp-polishing-pads-applications-across-the-full-ic-process-flow\/","title":{"rendered":"Semiconductor CMP Polishing Pads: Applications Across the Full IC Process Flow"},"content":{"rendered":"<!-- ============================================================\n     CLUSTER 14 \u2014 Semiconductor CMP Polishing Pads | Jizhi Electronic Technology | April 2026 | \/blog\/Semiconductor-CMP-Polishing-Pads\n     ============================================================ -->\n<style>\n@import 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18px}.jz-btn-outline{margin-left:0;margin-top:10px;display:inline-block}}\n<\/style>\n\n<div class=\"jz-art\">\n<a class=\"jz-back\" href=\"https:\/\/jeez-semicon.com\/zh\/blog\/CMP-Polishing-Pads-The-Complete-Guide\/\" target=\"_blank\">Back to CMP Polishing Pads: The Complete Guide<\/a>\n\n<div class=\"jz-hero\">\n  <div class=\"jz-hero-kicker\">Jizhi Electronic Technology \u2014 Applications Series<\/div>\n  <p class=\"jz-hero-lead\">A complete step-by-step guide to how CMP polishing pads are deployed across the full semiconductor IC manufacturing process \u2014 from shallow trench isolation to advanced BEOL copper interconnects, 3D NAND, and emerging heterogeneous integration applications.<\/p>\n  <div class=\"jz-hero-meta\">\n    <span>\ud83d\udcc5 April 2026<\/span>\n    <span>\u23f1 14 min read<\/span>\n    <span>\ud83c\udfed Jizhi Electronic Technology Co., Ltd.<\/span>\n  <\/div>\n<\/div>\n\n<div class=\"jz-tags\">\n  <span class=\"jz-tag\">Semiconductor CMP<\/span>\n  <span class=\"jz-tag\">IC Fabrication<\/span>\n  <span class=\"jz-tag\">STI CMP<\/span>\n  <span class=\"jz-tag\">Cu BEOL<\/span>\n  <span class=\"jz-tag\">W Plug CMP<\/span>\n  <span class=\"jz-tag\">3D NAND CMP<\/span>\n  <span class=\"jz-tag\">Wafer Polishing<\/span>\n  <span class=\"jz-tag\">Process Flow<\/span>\n<\/div>\n\n<div class=\"jz-trust\">\n  <div class=\"jz-trust-badge\">\u8fc7\u7a0b<br>Flow<\/div>\n  <div class=\"jz-trust-text\"><strong>Written by Jizhi Electronic Technology Co., Ltd.<\/strong> \u2014 CMP pad manufacturer supplying wafer fabs, semiconductor equipment makers, and research institutions. Application data reflects current April 2026 best practice across 28 nm to 3 nm IC fabrication process flows.<\/div>\n<\/div>\n\n<div class=\"jz-toc\">\n  <div class=\"jz-toc-title\">\ud83d\udccb \u76ee\u5f55<\/div>\n  <ol>\n    <li><a href=\"#why-multiple-steps\">Why Modern ICs Need 30+ CMP Steps<\/a><\/li>\n    <li><a href=\"#feol\">Front-End-of-Line CMP Steps<\/a><\/li>\n    <li><a href=\"#beol\">Back-End-of-Line CMP: Copper Interconnect<\/a><\/li>\n    <li><a href=\"#memory\">CMP in 3D NAND and DRAM Manufacturing<\/a><\/li>\n    <li><a href=\"#packaging\">Advanced Packaging CMP<\/a><\/li>\n    <li><a href=\"#pad-map\">CMP Pad Selection Map: Full Process Flow<\/a><\/li>\n    <li><a href=\"#faq\">FAQ<\/a><\/li>\n  <\/ol>\n<\/div>\n\n<p>Modern semiconductor manufacturing is fundamentally multi-material and three-dimensional. A leading-edge logic chip fabricated at 3\u20135 nm contains transistors made from silicon, silicon germanium, hafnium oxide, titanium nitride, and tungsten \u2014 all in the same active device layer. Above those transistors are 12\u201318 metal interconnect levels built from copper embedded in low-k dielectric, connected by tungsten vias, and isolated by silicon nitride etch stop layers. Each of these material boundaries represents a CMP step.<\/p>\n\n<p>The result is that a modern 300 mm wafer running through a leading-edge logic process flow will undergo more than 30 individual CMP operations before it is ready for packaging. Each step uses a different pad specification, different slurry chemistry, and different process recipe \u2014 optimized for the specific material being planarized and the step-height challenge it presents.<\/p>\n\n<p>For an introduction to what CMP pads are and how they work, see: <a class=\"jz-link-chip\" href=\"https:\/\/jeez-semicon.com\/zh\/blog\/What-Is-a-CMP-Polishing-Pad-The-Ultimate-Guide\/\" target=\"_blank\">What Is a CMP Polishing Pad? The Ultimate Guide<\/a>.<\/p>\n\n<div class=\"jz-stats\">\n  <div class=\"jz-stat\"><div class=\"jz-stat-num\">30+<\/div><div class=\"jz-stat-label\">Individual CMP steps in a leading-edge 3\u20135 nm logic process flow<\/div><\/div>\n  <div class=\"jz-stat\"><div class=\"jz-stat-num\">12\u201318<\/div><div class=\"jz-stat-label\">Metal interconnect levels in advanced logic \u2014 each requiring CMP<\/div><\/div>\n  <div class=\"jz-stat\"><div class=\"jz-stat-num\">~8%<\/div><div class=\"jz-stat-label\">Of total wafer processing time at a leading fab spent in CMP operations<\/div><\/div>\n  <div class=\"jz-stat\"><div class=\"jz-stat-num\">3\u20138<\/div><div class=\"jz-stat-label\">Different pad SKUs needed to cover the full CMP step library at a logic fab<\/div><\/div>\n<\/div>\n\n<h2 id=\"why-multiple-steps\">1. Why Modern ICs Need 30+ CMP Steps<\/h2>\n<p>The need for so many CMP steps in modern IC manufacturing arises from three simultaneous trends: device scaling, architectural complexity, and material diversification. As transistor gates have shrunk below 10 nm, the tolerance for any surface non-planarity between process steps has become vanishingly small \u2014 the depth of focus of EUV lithography (used for the most critical pattern levels) is measured in tens of nanometers. Any surface deviation larger than this causes patterning errors. CMP is the only process that reliably delivers the global planarization required at each critical level.<\/p>\n\n<p>The multi-level copper interconnect stack is equally demanding. Each copper level requires: (1) a CMP step to planarize the ILD dielectric before copper trench etching; (2) a CMP step to remove excess copper after electroplating; and (3) often a CMP step to clear the barrier metal and finalize the surface for the next level&#8217;s dielectric deposition. Multiply this three-step sequence across 12\u201318 metal levels and the copper CMP alone accounts for 36\u201354 individual polish operations.<\/p>\n\n<h2 id=\"feol\">2. Front-End-of-Line (FEOL) CMP Steps<\/h2>\n\n<div class=\"jz-table-wrap\">\n  <table class=\"jz-table\">\n    <thead><tr><th>FEOL CMP Step<\/th><th>\u76ee\u6807\u7535\u5f71<\/th><th>\u4e3b\u8981\u6311\u6218<\/th><th>Recommended Pad Type<\/th><\/tr><\/thead>\n    <tbody>\n      <tr><td><strong>Shallow Trench Isolation (STI)<\/strong><\/td><td>TEOS or HDP oxide over Si\u2083N\u2084 stop layer<\/td><td>High incoming step height (200\u2013500 nm); must stop on nitride with high selectivity; no dishing of active areas<\/td><td>Hard PU (Shore D 60\u201365) + high-selectivity ceria slurry; IC1000-equivalent or JZ-H65<\/td><\/tr>\n      <tr><td><strong>Pre-Metal Dielectric (PMD) planarization<\/strong><\/td><td>BPSG or undoped silicate glass over gate structures<\/td><td>Very high incoming topography from gate stacks; must achieve &gt;80% step-height reduction in single pass<\/td><td>Hard PU (Shore D 62\u201366) + silica slurry; aggressive planarization recipe<\/td><\/tr>\n      <tr><td><strong>Gate dielectric polish<\/strong><\/td><td>High-k dielectric (HfO\u2082) over poly or metal gate<\/td><td>Very thin target film (&lt;3 nm); extremely low removal rate needed; ultra-low scratch tolerance<\/td><td>Very soft PU (Shore D 28\u201335) + colloidal silica; ultra-low pressure<\/td><\/tr>\n      <tr><td><strong>Dummy gate removal (gate-last FinFET)<\/strong><\/td><td>Polysilicon dummy gate and sacrificial dielectric<\/td><td>High topography; must expose gate top without damaging gate dielectric; tight WIWNU<\/td><td>Medium-hard PU (Shore D 50\u201358) with stacked configuration<\/td><\/tr>\n      <tr><td><strong>Contact hole pre-fill planarization<\/strong><\/td><td>ILD oxide before contact etch<\/td><td>Must achieve flat surface for lithography of deep sub-20 nm contacts<\/td><td>Hard PU (Shore D 58\u201362) + standard ceria; standard oxide CMP recipe<\/td><\/tr>\n    <\/tbody>\n  <\/table>\n<\/div>\n\n<h2 id=\"beol\">3. Back-End-of-Line (BEOL) CMP: Copper Interconnect<\/h2>\n<p>The BEOL copper interconnect stack is the most CMP-intensive part of any IC process flow, and the most demanding in terms of pad selection \u2014 because the target films (Cu, Ta, TaN, low-k SiCOH) are soft, fragile, and prone to scratch and corrosion defects that directly affect electrical performance. For a detailed discussion of the hard vs. soft pad choice in BEOL, see: <a class=\"jz-link-chip\" href=\"https:\/\/jeez-semicon.com\/zh\/blog\/Hard-vs-Soft-CMP-Polishing-Pads-Selection-Guide\/\" target=\"_blank\">Hard vs. Soft CMP Polishing Pads: Selection Guide<\/a>.<\/p>\n\n<div class=\"jz-table-wrap\">\n  <table class=\"jz-table\">\n    <thead><tr><th>BEOL CMP Step<\/th><th>\u76ee\u6807\u7535\u5f71<\/th><th>Critical Requirement<\/th><th>\u57ab\u5b50\u7c7b\u578b<\/th><\/tr><\/thead>\n    <tbody>\n      <tr><td><strong>ILD oxide planarization (pre-trench)<\/strong><\/td><td>SiCOH low-k dielectric (k 2.4\u20133.0)<\/td><td>Flat surface for trench litho; must not crack or delaminate low-k<\/td><td>Medium-soft PU (Shore D 42\u201352) + stacked subpad; reduced pressure<\/td><\/tr>\n      <tr><td><strong>Cu bulk overburden removal (Step 1)<\/strong><\/td><td>Electroplated copper (2\u20135 \u00b5m overburden)<\/td><td>Fast removal of excess Cu; protect low-k beneath barrier; minimize dishing<\/td><td>Medium-soft PU (Shore D 38\u201348) + BTA-based Cu slurry; moderate pressure<\/td><\/tr>\n      <tr><td><strong>Cu \/ barrier clearing and buff (Step 2)<\/strong><\/td><td>Residual Cu + TaN\/Ta barrier; low-k surface<\/td><td>Clear barrier with minimal dishing and erosion; Ra &lt; 0.5 nm; scratch density &lt;5\/wafer<\/td><td>Very soft PU (Shore D 28\u201336) + colloidal silica barrier slurry; ultra-low pressure (&lt;1.5 psi)<\/td><\/tr>\n      <tr><td><strong>Via fill planarization (W)<\/strong><\/td><td>CVD tungsten over TiN barrier<\/td><td>Clear W to ILD; high W-to-TiN selectivity; no W plug recess (dishing)<\/td><td>Hard PU (Shore D 58\u201364) + H\u2082O\u2082\/ferric catalyst slurry; standard IC1000-equivalent<\/td><\/tr>\n      <tr><td><strong>Inter-metal dielectric (IMD) planarization<\/strong><\/td><td>Low-k SiCOH or extreme low-k (k &lt; 2.5)<\/td><td>Fragile porous dielectric \u2014 shear force must be below delamination threshold<\/td><td>Ultra-soft PU (Shore D 24\u201332) + very low pressure (&lt;1 psi); stacked configuration mandatory<\/td><\/tr>\n    <\/tbody>\n  <\/table>\n<\/div>\n\n<h2 id=\"memory\">4. CMP in 3D NAND and DRAM Manufacturing<\/h2>\n<p>Memory chip manufacturing presents distinct CMP challenges compared to logic. In 3D NAND flash \u2014 where 100\u2013256 alternating oxide\/nitride (or oxide\/polysilicon) layer pairs are deposited and etched in a high-aspect-ratio stack \u2014 the CMP requirements are driven by planarization uniformity rather than selectivity. Any within-wafer thickness variation in the planarized stack directly propagates as variation in cell threshold voltage, affecting device reliability and data retention.<\/p>\n\n<ul>\n  <li><strong>3D NAND oxide-nitride stack planarization:<\/strong> Hard pads (Shore D 60\u201365) with ceria slurry; extremely tight WIWNU target (&lt;0.5% 1\u03c3) achieved by precise groove design and in-situ endpoint control<\/li>\n  <li><strong>3D NAND channel hole fill (polysilicon):<\/strong> Medium-hard pad with silica slurry; must remove excess polysilicon uniformly from a surface with hundreds of etched holes per \u00b5m\u00b2<\/li>\n  <li><strong>DRAM capacitor node planarization:<\/strong> Hard pad with high-selectivity slurry; extremely deep-aspect-ratio structures require excellent step-height reduction<\/li>\n  <li><strong>DRAM peripheral circuit planarization:<\/strong> Standard oxide CMP \u2014 similar to FEOL logic; IC1000-equivalent hard pads with ceria slurry<\/li>\n<\/ul>\n\n<h2 id=\"packaging\">5. Advanced Packaging CMP<\/h2>\n<p>The transition to advanced packaging architectures \u2014 chiplet-based heterogeneous integration, 2.5D interposers, 3D-IC stacking with through-silicon vias (TSVs) \u2014 has created an entirely new set of CMP applications that sit at the boundary between wafer fabrication and packaging. These applications are growing rapidly as of April 2026, driven by the AI chip market&#8217;s demand for high-bandwidth memory (HBM) stacking and die-to-die interconnect.<\/p>\n\n<div class=\"jz-card-grid\">\n  <div class=\"jz-card\">\n    <div class=\"jz-card-icon\">\ud83d\udd17<\/div>\n    <h4>TSV (Through-Silicon Via) CMP<\/h4>\n    <p>After TSV copper filling, CMP removes the copper overburden and reveals the TSV tops. Requires excellent local planarity around each TSV to enable die-to-die bonding. Soft pad + fine-pitch groove pattern for best uniformity around high-aspect-ratio TSV structures.<\/p>\n  <\/div>\n  <div class=\"jz-card\">\n    <div class=\"jz-card-icon\">\ud83c\udfd7\ufe0f<\/div>\n    <h4>Redistribution Layer (RDL) CMP<\/h4>\n    <p>Cu RDL lines on organic or glass substrates require CMP to achieve flat surfaces for multi-layer fan-out wafer-level packaging. Lower substrate stiffness compared to silicon wafers demands very soft, highly compliant pads that adapt to substrate bow without edge-center loading issues.<\/p>\n  <\/div>\n  <div class=\"jz-card\">\n    <div class=\"jz-card-icon\">\ud83e\udde9<\/div>\n    <h4>Hybrid Bonding Surface Preparation<\/h4>\n    <p>Direct copper-to-copper hybrid bonding (used in HBM4 and advanced 3D-IC) requires atomically smooth Cu bond pads \u2014 Ra &lt; 0.5 nm and step height below 2 nm relative to the surrounding dielectric. The most demanding surface quality specification in semiconductor CMP. Requires poreless pads with fine abrasive slurry at ultra-low pressure.<\/p>\n  <\/div>\n  <div class=\"jz-card\">\n    <div class=\"jz-card-icon\">\ud83d\udd32<\/div>\n    <h4>Interposer Planarization<\/h4>\n    <p>Silicon interposers for 2.5D integration require multiple CMP steps for their embedded wiring layers \u2014 similar to standard IC BEOL CMP but often on thinner substrates that are more prone to warpage. Stacked pad configuration with a compliant subpad is essential for interposer CMP.<\/p>\n  <\/div>\n<\/div>\n\n<h2 id=\"pad-map\">6. CMP Pad Selection Map: Full Process Flow Summary<\/h2>\n<div class=\"jz-table-wrap\">\n  <table class=\"jz-table\">\n    <thead><tr><th>Process Step Category<\/th><th>Hardness Range<\/th><th>Jizhi Product<\/th><th>Key Slurry<\/th><\/tr><\/thead>\n    <tbody>\n      <tr><td>STI, PMD oxide CMP<\/td><td>Shore D 60\u201366 (hard)<\/td><td>JZ-H65<\/td><td>High-selectivity ceria, pH 7\u20139<\/td><\/tr>\n      <tr><td>Standard oxide ILD (mature node)<\/td><td>Shore D 58\u201362 (hard)<\/td><td>JZ-H60<\/td><td>Ceria or silica, pH 10\u201311<\/td><\/tr>\n      <tr><td>Tungsten plug\/via CMP<\/td><td>Shore D 60\u201365 (hard)<\/td><td>JZ-H60 \/ JZ-H65<\/td><td>H\u2082O\u2082 + Fe catalyst, pH 2\u20134<\/td><\/tr>\n      <tr><td>Cu bulk overburden (BEOL Step 1)<\/td><td>Shore D 38\u201348 (medium-soft)<\/td><td>JZ-S38<\/td><td>BTA + H\u2082O\u2082, pH 4\u20137<\/td><\/tr>\n      <tr><td>Cu \/ barrier buff (BEOL Step 2)<\/td><td>Shore D 26\u201336 (very soft)<\/td><td>JZ-S28<\/td><td>Colloidal silica, pH 7\u20139<\/td><\/tr>\n      <tr><td>Low-k, ultra-thin films<\/td><td>Shore D 24\u201332 (ultra-soft)<\/td><td>JZ-S28 (low pressure)<\/td><td>Ultra-fine silica, pH 7<\/td><\/tr>\n      <tr><td>SiC substrate (Stage 2)<\/td><td>Shore D 63\u201368 (specialty)<\/td><td>JZ-SiC-I<\/td><td>Diamond 0.1\u20130.5 \u00b5m + H\u2082O\u2082<\/td><\/tr>\n      <tr><td>SiC substrate (Stage 3 final)<\/td><td>Shore D 53\u201360 (specialty)<\/td><td>JZ-SiC-II<\/td><td>Ceria + KMnO\u2084 0.5\u20131.5%<\/td><\/tr>\n      <tr><td>TSV \/ RDL \/ hybrid bonding<\/td><td>Shore D 28\u201342 (soft)<\/td><td>JZ-S38 \/ Custom<\/td><td>Ultra-fine Cu slurry, pH 4\u20137<\/td><\/tr>\n    <\/tbody>\n  <\/table>\n<\/div>\n\n<div class=\"jz-callout cta\">\n  <div class=\"jz-callout-icon\">\ud83c\udfed<\/div>\n  <div class=\"jz-callout-body\">\n    <strong>Jizhi&#8217;s Full-Process Pad Portfolio<\/strong>\n    Jizhi Electronic Technology supplies CMP polishing pads for every step in the semiconductor IC manufacturing process \u2014 from FEOL STI oxide CMP to BEOL Cu buff, and from mature-node production to advanced packaging hybrid bonding. Contact our application engineering team to identify the optimal pad specification for each step in your process flow. <a href=\"https:\/\/jeez-semicon.com\/zh\/contact\/\" target=\"_blank\">Discuss your process flow \u2192<\/a>\n  <\/div>\n<\/div>\n\n<h2>7. Frequently Asked Questions<\/h2>\n<div class=\"jz-faq\">\n  <div class=\"jz-faq-item\">\n    <div class=\"jz-faq-q\">How many different pad SKUs does a typical fab need to maintain in inventory?<\/div>\n    <div class=\"jz-faq-a\">A mature-node fab (28 nm and above) typically maintains 3\u20135 pad SKUs: one or two hard oxide\/W CMP pads (possibly with and without endpoint window), one or two soft Cu BEOL pads (bulk and buff steps), and optionally a specialty pad for non-standard materials. A leading-edge logic fab (7 nm and below) maintains 5\u20138 SKUs: multiple hard pad variants for different oxide CMP steps, poreless pads for the most defect-sensitive steps, multiple soft Cu pads for different BEOL levels, and potentially a specialty pad for cobalt or ruthenium barrier CMP. Research fabs and packaging facilities add further SKUs for substrate, TSV, and RDL applications.<\/div>\n  <\/div>\n  <div class=\"jz-faq-item\">\n    <div class=\"jz-faq-q\">Can the same pad be used for both STI and Cu BEOL CMP?<\/div>\n    <div class=\"jz-faq-a\">No \u2014 these two step categories require almost opposite pad hardness specifications. STI CMP needs a hard pad (Shore D 60\u201365) for planarization efficiency and nitride selectivity; Cu BEOL buff CMP needs a very soft pad (Shore D 26\u201336) for defect protection and uniformity. Using an STI-optimized hard pad for Cu buff CMP will cause low-k delamination and excessive scratch generation. Using a Cu buff soft pad for STI will result in inadequate step-height reduction and potential nitride faceting. Separate dedicated pads for each step category are mandatory in production environments.<\/div>\n  <\/div>\n  <div class=\"jz-faq-item\">\n    <div class=\"jz-faq-q\">How is CMP used in hybrid bonding for advanced packaging?<\/div>\n    <div class=\"jz-faq-a\">Direct hybrid bonding \u2014 where bare silicon and copper bond pads are brought into atomic contact without solder \u2014 requires the bonding surfaces to be flat to within 1\u20132 nm step height between the Cu pad and surrounding SiO\u2082 and within Ra &lt; 0.5 nm on the copper surfaces. CMP is performed immediately before bonding using ultra-fine slurry (colloidal silica, d50 ~20\u201340 nm) and a poreless or ultra-low-defect soft pad at very low pressure (&lt;1 psi). The bond immediately after CMP must be protected from any contamination \u2014 post-CMP cleaning and wafer storage protocols are extremely tight. Jizhi is developing a dedicated hybrid bonding CMP pad series to be released in late 2026.<\/div>\n  <\/div>\n<\/div>\n\n<div class=\"jz-related\">\n  <div class=\"jz-related-title\">\ud83d\udcda Continue Reading<\/div>\n  <div class=\"jz-related-grid\">\n    <div class=\"jz-related-item\"><div class=\"jz-related-cat\">PILLAR<\/div><a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/CMP-Polishing-Pads-The-Complete-Guide\/\" target=\"_blank\">CMP Polishing Pads: The Complete Guide<\/a><\/div>\n    <div class=\"jz-related-item\"><div class=\"jz-related-cat\">FUNDAMENTALS<\/div><a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/What-Is-a-CMP-Polishing-Pad-The-Ultimate-Guide\/\" target=\"_blank\">What Is a CMP Polishing Pad? The Ultimate Guide<\/a><\/div>\n    <div class=\"jz-related-item\"><div class=\"jz-related-cat\">SELECTION<\/div><a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/Hard-vs-Soft-CMP-Polishing-Pads-Selection-Guide\/\" target=\"_blank\">Hard vs. Soft CMP Polishing Pads: Selection Guide<\/a><\/div>\n    <div class=\"jz-related-item\"><div class=\"jz-related-cat\">APPLICATIONS<\/div><a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/SiC-CMP-Polishing-Pads-for-Third-Generation-Semiconductors\/\" target=\"_blank\">SiC CMP Polishing Pads for Third-Generation Semiconductors<\/a><\/div>\n    <div class=\"jz-related-item\"><div class=\"jz-related-cat\">CUSTOMIZATION<\/div><a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/Custom-CMP-Polishing-Pad-Solutions\/\" target=\"_blank\">Custom CMP Polishing Pad Solutions<\/a><\/div>\n    <div class=\"jz-related-item\"><div class=\"jz-related-cat\">QUALITY<\/div><a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/CMP-Pad-Defect-Control-Scratches-and-Uniformity\/\" target=\"_blank\">CMP Pad Defect Control: Scratches and Uniformity<\/a><\/div>\n  <\/div>\n<\/div>\n\n<div class=\"jz-cta-banner\">\n  <h2>CMP Pads for Every Step in Your Process Flow<\/h2>\n  <p>Jizhi Electronic Technology supplies hard oxide pads, soft Cu BEOL pads, SiC-specific formulations, and custom OEM solutions \u2014 covering the full CMP step library from FEOL to advanced packaging. Process characterization data included with every shipment.<\/p>\n  <a class=\"jz-btn jz-btn-white\" href=\"https:\/\/jeez-semicon.com\/zh\/semi-categories\/polishing-pad\/\" target=\"_blank\">Browse CMP Polishing Pads<\/a>\n  <a class=\"jz-btn jz-btn-outline\" href=\"https:\/\/jeez-semicon.com\/zh\/contact\/\" target=\"_blank\">Map Pads to Your Process Flow<\/a>\n<\/div>\n<\/div>","protected":false},"excerpt":{"rendered":"<p>Back to CMP Polishing Pads: The Complete Guide Jizhi Electronic Technology \u2014 Applications Series A complete step-by-step guide to how CMP polishing pads are deployed across the full semiconductor IC  &#8230;<\/p>","protected":false},"author":1,"featured_media":1819,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[9,59],"tags":[],"class_list":["post-1798","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-blog","category-industry"],"acf":[],"_links":{"self":[{"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/posts\/1798","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/comments?post=1798"}],"version-history":[{"count":2,"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/posts\/1798\/revisions"}],"predecessor-version":[{"id":1800,"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/posts\/1798\/revisions\/1800"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/media\/1819"}],"wp:attachment":[{"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/media?parent=1798"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/categories?post=1798"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/tags?post=1798"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}