{"id":2460,"date":"2026-07-16T13:17:46","date_gmt":"2026-07-16T05:17:46","guid":{"rendered":"https:\/\/jeez-semicon.com\/?p=2460"},"modified":"2026-07-16T13:28:53","modified_gmt":"2026-07-16T05:28:53","slug":"sti-cmp-slurry-ceria-chemistry-sio2-si3n4-selectivity-advanced-node-guide","status":"publish","type":"post","link":"https:\/\/jeez-semicon.com\/zh\/blog\/sti-cmp-slurry-ceria-chemistry-sio2-si3n4-selectivity-advanced-node-guide\/","title":{"rendered":"STI CMP Slurry: Ceria Chemistry, SiO\u2082:Si\u2083N\u2084 Selectivity &amp; Advanced Node Guide"},"content":{"rendered":"<p><style>\r\n\/* JEEZ Oxide CMP Cluster Article | Jizhi Electronic Technology Co., Ltd. | jeez-semicon.com *\/\r\n#jeez-ocmp *, #jeez-ocmp *::before, #jeez-ocmp *::after { box-sizing: border-box; }\r\n#jeez-ocmp { font-family: 'Inter', system-ui, -apple-system, sans-serif; font-size: 1rem; line-height: 1.78; color: #1E293B; max-width: 100%; }\r\n#jeez-ocmp h1 { font-family: 'Syne', sans-serif; font-size: clamp(1.75rem, 5vw, 2.875rem); font-weight: 800; line-height: 1.12; color: #0B2444; letter-spacing: -0.025em; margin: 0 0 1.125rem; padding: 0; }\r\n#jeez-ocmp h2 { font-family: 'Syne', sans-serif; font-size: clamp(1.2rem, 3vw, 1.625rem); font-weight: 700; color: #0B2444; margin: 3rem 0 1rem; padding: 0 0 0 1.125rem; position: relative; scroll-margin-top: 90px; }\r\n#jeez-ocmp h2::before { content: ''; position: absolute; left: 0; top: 0.15em; bottom: 0.1em; width: 4px; background: linear-gradient(180deg, #1A6EFF, #0A4DCC); border-radius: 2px; }\r\n#jeez-ocmp h3 { font-family: 'Syne', sans-serif; font-size: clamp(1rem, 2.5vw, 1.2rem); font-weight: 700; color: #0B2444; margin: 1.875rem 0 0.75rem; padding: 0; }\r\n#jeez-ocmp h4 { font-family: 'Syne', sans-serif; font-size: 0.9375rem; font-weight: 700; color: #0F3870; margin: 1.375rem 0 0.5rem; padding: 0; }\r\n#jeez-ocmp p { margin: 0 0 1.2rem; color: #334155; }\r\n#jeez-ocmp ul, #jeez-ocmp ol { margin: 0.5rem 0 1.2rem; padding-left: 1.5rem; }\r\n#jeez-ocmp li { margin-bottom: 0.45rem; color: #334155; }\r\n#jeez-ocmp strong { font-weight: 600; color: #0B2444; }\r\n#jeez-ocmp em { font-style: italic; }\r\n#jeez-ocmp a { color: #1A6EFF; text-decoration: none; transition: color 0.15s; }\r\n#jeez-ocmp a:hover { color: #0A4DCC; text-decoration: underline; }\r\n#jeez-ocmp sub, #jeez-ocmp sup { font-size: 72%; line-height: 0; position: relative; vertical-align: baseline; }\r\n#jeez-ocmp sub { bottom: -0.25em; }\r\n#jeez-ocmp sup { top: -0.5em; }\r\n.ocmp-meta { display: flex; flex-wrap: wrap; align-items: center; gap: 0.5rem 1.5rem; padding: 0.875rem 0 1.5rem; border-bottom: 1px solid #E2EAF4; margin-bottom: 2rem; font-size: 0.8125rem; color: #64748B; }\r\n.ocmp-lead { font-size: 1.0625rem; line-height: 1.8; color: #2D4060; margin-bottom: 1.375rem; }\r\n.ocmp-toc { background: #F5F8FF; border: 1px solid #CDD8F8; border-radius: 12px; padding: 1.75rem 2rem; margin: 0 0 2.75rem; }\r\n.ocmp-toc-title { font-family: 'Syne', sans-serif; font-weight: 700; font-size: 0.75rem; text-transform: uppercase; letter-spacing: 0.1em; color: #1A6EFF; margin: 0 0 1rem; }\r\n.ocmp-toc ol { list-style: none; padding: 0; margin: 0; display: grid; grid-template-columns: repeat(auto-fill, minmax(240px, 1fr)); gap: 0.4rem 2rem; counter-reset: toc-counter; }\r\n.ocmp-toc ol li { counter-increment: toc-counter; display: flex; align-items: baseline; gap: 0.625rem; font-size: 0.875rem; line-height: 1.4; }\r\n.ocmp-toc ol li::before { content: counter(toc-counter); font-family: 'Syne', sans-serif; font-weight: 700; font-size: 0.675rem; color: #fff; background: #1A6EFF; min-width: 18px; height: 18px; border-radius: 50%; display: inline-flex; align-items: center; justify-content: center; flex-shrink: 0; }\r\n.ocmp-toc a { color: #2D4A7A; text-decoration: none; transition: color 0.15s; }\r\n.ocmp-toc a:hover { color: #1A6EFF; }\r\n.ocmp-box { border-radius: 10px; padding: 1.125rem 1.375rem; margin: 1.75rem 0; font-size: 0.9375rem; }\r\n.ocmp-box p { margin: 0; color: inherit; }\r\n.ocmp-box ul { margin: 0.375rem 0 0; }\r\n.ocmp-box-label { font-family: 'Syne', sans-serif; font-size: 0.7rem; font-weight: 700; text-transform: uppercase; letter-spacing: 0.08em; margin: 0 0 0.375rem; display: block; }\r\n.ocmp-box.info { background: #EEF4FF; border-left: 3px solid #1A6EFF; color: #1E3A6A; }\r\n.ocmp-box.info .ocmp-box-label { color: #1A6EFF; }\r\n.ocmp-box.key { background: #ECFDF5; border-left: 3px solid #059669; color: #1A3A2E; }\r\n.ocmp-box.key .ocmp-box-label { color: #059669; }\r\n.ocmp-box.caution { background: #FFFBEB; border-left: 3px solid #D97706; color: #44290A; }\r\n.ocmp-box.caution .ocmp-box-label { color: #B45309; }\r\n.ocmp-table-wrap { overflow-x: auto; margin: 1.75rem 0; border-radius: 12px; border: 1px solid #DDE5F0; box-shadow: 0 1px 3px rgba(0,0,0,0.06); }\r\n.ocmp-table-wrap table { width: 100%; border-collapse: collapse; font-size: 0.875rem; min-width: 480px; }\r\n.ocmp-table-wrap thead th { background: #0B2444; color: #D0DEFA; font-family: 'Syne', sans-serif; font-weight: 600; font-size: 0.74rem; text-transform: uppercase; letter-spacing: 0.055em; padding: 0.875rem 1rem; text-align: left; white-space: nowrap; }\r\n.ocmp-table-wrap thead th:first-child { border-radius: 11px 0 0 0; }\r\n.ocmp-table-wrap thead th:last-child { border-radius: 0 11px 0 0; }\r\n.ocmp-table-wrap tbody td { padding: 0.75rem 1rem; border-bottom: 1px solid #EEF2FA; color: #334155; vertical-align: top; line-height: 1.55; }\r\n.ocmp-table-wrap tbody tr:last-child td { border-bottom: none; }\r\n.ocmp-table-wrap tbody tr:nth-child(even) td { background: #F7F9FD; }\r\n.ocmp-table-wrap tbody tr:hover td { background: #EEF4FF; transition: background 0.12s; }\r\n.ocmp-td-label { font-weight: 600; color: #0B2444; white-space: nowrap; }\r\n.ocmp-compare { display: grid; grid-template-columns: 1fr 1fr; gap: 1.25rem; margin: 1.75rem 0; }\r\n.ocmp-compare-col { border: 1px solid #E2E8F0; border-radius: 10px; padding: 1.375rem 1.5rem; background: #fff; }\r\n.ocmp-compare-col-title { font-family: 'Syne', sans-serif; font-size: 0.9375rem; font-weight: 700; padding-bottom: 0.625rem; margin: 0 0 0.875rem; border-bottom-width: 2px; border-bottom-style: solid; }\r\n.ocmp-compare-col.blue .ocmp-compare-col-title { color: #1A6EFF; border-bottom-color: #1A6EFF; }\r\n.ocmp-compare-col.teal .ocmp-compare-col-title { color: #059669; border-bottom-color: #059669; }\r\n.ocmp-compare-col.amber .ocmp-compare-col-title { color: #D97706; border-bottom-color: #D97706; }\r\n.ocmp-compare-col ul { padding-left: 1.125rem; margin: 0; }\r\n.ocmp-compare-col li { font-size: 0.875rem; margin-bottom: 0.45rem; color: #334155; }\r\n.ocmp-back { background: #F5F8FF; border: 1px solid #C8D8F8; border-radius: 10px; padding: 1.125rem 1.5rem; margin: 2.5rem 0; font-size: 0.9rem; color: #2D4A7A; }\r\n.ocmp-back a { color: #1A6EFF; font-weight: 600; }\r\n.ocmp-faq { margin: 1.5rem 0 2rem; }\r\n.ocmp-faq-item { border: 1px solid #E2EAF4; border-radius: 10px; margin-bottom: 0.75rem; overflow: hidden; }\r\n.ocmp-faq-q { font-family: 'Syne', sans-serif; font-weight: 700; font-size: 0.9375rem; color: #0B2444; padding: 1.125rem 1.25rem; background: #F5F8FF; display: block; margin: 0; border-bottom: 1px solid #E2EAF4; line-height: 1.45; }\r\n.ocmp-faq-a { padding: 1rem 1.25rem; font-size: 0.9rem; color: #334155; margin: 0; line-height: 1.72; }\r\n.ocmp-hr { border: none; border-top: 1px solid #E2EAF4; margin: 2.5rem 0; }\r\n@media (max-width: 640px) {\r\n  .ocmp-compare { grid-template-columns: 1fr; }\r\n  .ocmp-toc ol { grid-template-columns: 1fr; }\r\n  #jeez-ocmp h2 { margin-top: 2.25rem; }\r\n}\r\n<\/style><\/p>\r\n<article id=\"jeez-ocmp\">\r\n<div class=\"ocmp-meta\">\ud83d\udcc5 July 2026\u00b7\u23f1 19 min read\u00b7\u270d\ufe0f JEEZ Technical Team<\/div>\r\n<p class=\"ocmp-lead\">Shallow trench isolation (STI) CMP is among the most technically demanding polishing steps in front-end-of-line semiconductor processing. The requirement to achieve SiO<sub>2<\/sub>:Si<sub>3<\/sub>N<sub>4<\/sub> selectivity ratios of 50:1 to 200:1 while maintaining sub-nanometer uniformity across a 300 mm wafer distinguishes STI from all other oxide CMP applications. This article provides a complete technical guide to STI CMP slurry \u2014 ceria chemistry, selectivity mechanisms, PAA additives, process integration, and advanced-node challenges. For a broad introduction to oxide CMP slurry types, see our <a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/oxide-cmp-slurry\/\" target=\"_blank\" rel=\"noopener noreferrer\">Oxide CMP Slurry: Complete Technical Guide<\/a>.<\/p>\r\n<nav class=\"ocmp-toc\" aria-label=\"\u76ee\u5f55\">\r\n<p class=\"ocmp-toc-title\">\u76ee\u5f55<\/p>\r\n<ol>\r\n<li><a href=\"#sti-what\">What Is STI CMP and Why Is It Critical?<\/a><\/li>\r\n<li><a href=\"#sti-selectivity\">The Selectivity Imperative<\/a><\/li>\r\n<li><a href=\"#sti-ceria\">Ceria Chemistry &amp; the Ce\u2013O\u2013Si Mechanism<\/a><\/li>\r\n<li><a href=\"#sti-paa\">PAA Additives &amp; Selectivity Enhancement<\/a><\/li>\r\n<li><a href=\"#sti-flow\">STI CMP Process Flow<\/a><\/li>\r\n<li><a href=\"#sti-advanced\">FinFET &amp; GAA Advanced Node Requirements<\/a><\/li>\r\n<li><a href=\"#sti-defects\">Dishing, Erosion &amp; Defect Management<\/a><\/li>\r\n<li><a href=\"#sti-faq\">\u5e38\u89c1\u95ee\u9898<\/a><\/li>\r\n<\/ol>\r\n<\/nav>\r\n<h2 id=\"sti-what\">What Is STI CMP and Why Is It Critical?<\/h2>\r\n<p>Shallow trench isolation (STI) is the transistor-level isolation architecture used in all CMOS devices manufactured at the 250 nm node and below. STI structures are formed by etching shallow trenches into the silicon substrate (typically 200\u2013400 nm deep), growing a thin thermal oxide liner on the trench walls, and then depositing a TEOS-based oxide gap-fill to completely fill the trenches and cover the surface with an oxide overburden above the original silicon plane.<\/p>\r\n<p>STI CMP removes this oxide overburden to reveal a planar surface that is flush with (or slightly above) the original silicon-nitride surface, while preserving the oxide fill inside the trench. The Si<sub>3<\/sub>N<sub>4<\/sub> hard mask \u2014 deposited before trench etching to protect the active transistor areas \u2014 must be preserved intact after CMP, because it defines the boundaries between active and isolation regions. Even a few nanometers of excess nitride removal can displace the active\/isolation boundary and degrade transistor performance.<\/p>\r\n<p>The STI CMP step determines: (1) the planarity of the starting surface for gate patterning; (2) the height of the isolation oxide relative to the active silicon surface (critical for gate overlap and leakage control); and (3) the uniformity of the nitride mask remaining after CMP (critical for fin height in FinFET devices). Any process failure in STI CMP can propagate through every subsequent FEOL step, making it one of the most yield-sensitive steps in logic device fabrication.<\/p>\r\n<h2 id=\"sti-selectivity\">The Selectivity Imperative<\/h2>\r\n<p>SiO<sub>2<\/sub>:Si<sub>3<\/sub>N<sub>4<\/sub> selectivity is the defining performance metric for STI CMP slurry. It is defined as the ratio of the oxide removal rate to the nitride removal rate under the same process conditions:<\/p>\r\n<p><em>Selectivity = MRR(SiO<sub>2<\/sub>) \/ MRR(Si<sub>3<\/sub>N<sub>4<\/sub>)<\/em><\/p>\r\n<p>For mature nodes (180 nm to 45 nm), selectivity ratios of 30:1 to 50:1 are generally adequate \u2014 the nitride budget is large enough to absorb some loss. But as device scaling has progressed to 14 nm, 7 nm, 5 nm, and below, the total nitride budget available after STI CMP has shrunk dramatically:<\/p>\r\n<div class=\"ocmp-box info\"><span class=\"ocmp-box-label\">Selectivity vs. Node<\/span>\r\n<p>At the 45 nm node, the nitride budget after STI allows ~5 nm loss. At the 7 nm FinFET node, it allows ~2 nm. At the 3 nm GAA node, allowable nitride loss is 1 nm or less \u2014 requiring SiO<sub>2<\/sub>:Si<sub>3<\/sub>N<sub>4<\/sub> selectivity consistently above 150:1.<\/p>\r\n<\/div>\r\n<p>Colloidal silica slurry achieves selectivity of only 5:1 to 15:1 \u2014 completely insufficient for any STI application. Only ceria (CeO<sub>2<\/sub>) abrasives, through their unique surface chemistry, can deliver the selectivity ratios required for modern STI CMP. This is why ceria is the only commercially viable abrasive for STI slurry.<\/p>\r\n<h2 id=\"sti-ceria\">Ceria Chemistry &amp; the Ce\u2013O\u2013Si Mechanism<\/h2>\r\n<p>Cerium oxide (CeO<sub>2<\/sub>, ceria) polishes SiO<sub>2<\/sub> through a mechanism fundamentally different from the mechanical abrasion that dominates colloidal silica polishing. Ceria particles interact chemically with the SiO<sub>2<\/sub> surface via a <strong>Ce\u2013O\u2013Si surface bonding mechanism<\/strong>:<\/p>\r\n<ol>\r\n<li>Cerium ions at the ceria particle surface (particularly Ce<sup>3+<\/sup> species) form temporary Ce\u2013O\u2013Si bridging bonds with SiO<sub>2<\/sub> surface hydroxyls (Si\u2013OH groups)<\/li>\r\n<li>The Si\u2013O\u2013Ce bond is substantially stronger than the Si\u2013O\u2013Si bond in the bulk SiO<sub>2<\/sub>, enabling mechanical detachment of SiO<sub>2<\/sub> surface units at lower applied pressures than silica abrasive requires<\/li>\r\n<li>The detached SiO<sub>2<\/sub> unit (carrying a Ce ion) is released into solution, where hydrolysis breaks the Ce\u2013O\u2013Si bond and regenerates the ceria surface for further bonding<\/li>\r\n<\/ol>\r\n<p>This chemical tooth-gear mechanism gives ceria its dramatically higher per-particle oxide removal efficiency compared to silica. At equal weight concentrations, ceria removes SiO<sub>2<\/sub> approximately 3\u20135\u00d7 faster than silica. This is why STI slurries use only 0.5\u20132 wt% ceria versus 5\u201315 wt% silica for ILD: the higher removal efficiency of ceria allows adequate MRR at much lower abrasive concentration.<\/p>\r\n<p>Critically, the Ce\u2013O\u2013Si mechanism operates selectively on SiO<sub>2<\/sub>: Si<sub>3<\/sub>N<sub>4<\/sub> surfaces do not present the accessible Si\u2013OH groups required for Ce\u2013O\u2013Si bond formation, so nitride surfaces experience primarily mechanical abrasion (much weaker than the chemical mechanism) from the low-concentration ceria particles. The intrinsic SiO<sub>2<\/sub>:Si<sub>3<\/sub>N<sub>4<\/sub> selectivity of ceria without additives is approximately 10:1 to 30:1 \u2014 enhanced significantly by the PAA additives described in the next section.<\/p>\r\n<p>The Ce<sup>3+<\/sup>\/Ce<sup>4+<\/sup> ratio on the ceria particle surface is a critical quality parameter: Ce<sup>3+<\/sup> sites are believed to be the primary active centers for Ce\u2013O\u2013Si bond formation. CMP-grade ceria suppliers manage calcination temperature, atmosphere, and surface treatment to optimize this ratio, and it is a key differentiator between high-performance and commodity ceria slurry products.<\/p>\r\n<h2 id=\"sti-paa\">PAA Additives &amp; Selectivity Enhancement<\/h2>\r\n<p>Anionic polymer additives \u2014 most commonly polyacrylic acid (PAA) \u2014 are added to ceria STI slurries to dramatically increase SiO<sub>2<\/sub>:Si<sub>3<\/sub>N<sub>4<\/sub> selectivity beyond the intrinsic ceria level. PAA at molecular weights of 1,000\u2013100,000 g\/mol functions through two simultaneous mechanisms:<\/p>\r\n<h3>Ceria Particle Stabilization<\/h3>\r\n<p>At STI slurry pH (5\u20138), ceria particles are positively charged (isoelectric point of CeO<sub>2<\/sub> ~pH 9). PAA (anionic at pH &gt; ~4.5) adsorbs onto the ceria particle surface through electrostatic attraction, providing a steric and electrostatic stabilization layer that prevents ceria particle aggregation. This stabilization function is critical for defect control: aggregated ceria clusters above ~0.5 \u00b5m in diameter are the primary source of micro-scratches in STI CMP.<\/p>\r\n<h3>Si<sub>3<\/sub>N<sub>4<\/sub> Surface Passivation<\/h3>\r\n<p>PAA also adsorbs onto Si<sub>3<\/sub>N<sub>4<\/sub> surfaces, creating a polymer passivation layer that physically blocks ceria abrasive contact with the nitride. This passivation layer is what pushes selectivity from the intrinsic ceria level (~20:1) to the 50:1\u2013200:1 range required for advanced STI.<\/p>\r\n<p>The PAA concentration is one of the most process-sensitive parameters in STI slurry formulation. A 20% increase in PAA concentration can raise selectivity from 80:1 to 150:1, but simultaneously reduce oxide MRR by 15\u201325% due to passivation of SiO<sub>2<\/sub> surfaces as well. The formulator must carefully calibrate PAA concentration to meet both the selectivity target (set by the nitride budget) and the throughput requirement (set by the oxide removal rate target). For a comparison of how abrasive choice affects selectivity, see: <a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/Colloidal-Silica-vs-Ceria-Abrasive-Oxide-CMP-Selection-Guide\/\" target=\"_blank\" rel=\"noopener noreferrer\">Colloidal Silica vs. Ceria Abrasive in Oxide CMP: A Practical Selection Guide<\/a>.<\/p>\r\n<h2 id=\"sti-flow\">STI CMP Process Flow<\/h2>\r\n<p>The STI CMP process flow on a 300 mm production tool typically consists of two distinct polishing steps designed to balance bulk removal speed against final selectivity and defect performance:<\/p>\r\n<h3>Step 1: Bulk Oxide Removal<\/h3>\r\n<p>The first step uses the STI slurry at standard conditions (1\u20133 psi, 80\u2013110 RPM) to remove the bulk of the oxide overburden above the nitride level. This step can also be performed with a higher-MRR ILD colloidal silica slurry if the overburden is large (&gt;500 \u00c5 above nitride plane) and the tool supports rapid slurry changeover. Motor current sensors on the polishing motor begin tracking the friction signature of the wafer surface to detect approach of the nitride layer.<\/p>\r\n<h3>Step 2: Selectivity-Controlled Touch-Up<\/h3>\r\n<p>As the polishing surface approaches the nitride plane (detected by motor current trend), the process transitions to a lower-pressure, higher-selectivity step. This step exploits the maximum selectivity of the ceria\/PAA system to remove the final oxide overburden while minimizing nitride loss. Optical endpoint detection monitors the nitride surface signature to confirm CMP completion. This two-step approach allows the bulk step to run at higher throughput while the selectivity step controls final quality metrics.<\/p>\r\n<h2 id=\"sti-advanced\">FinFET &amp; GAA Advanced Node Requirements<\/h2>\r\n<p>The transition from planar transistors to FinFET and Gate-All-Around (GAA) architectures has progressively tightened STI CMP requirements in ways that demand continuous innovation in slurry formulation.<\/p>\r\n<h3>FinFET STI: Fin Height Uniformity<\/h3>\r\n<p>In FinFET devices (Intel 22 nm through 5 nm), silicon fins are formed within the STI trench network. The final fin height after STI CMP is determined by the difference between the polished nitride surface height and the silicon floor of the STI trench \u2014 a quantity that is sensitive to both nitride removal uniformity and oxide dishing inside narrow fin-to-fin isolation gaps. At 7 nm FinFET, fin height uniformity must be held within \u00b10.5 nm across the wafer (a WIWNU requirement of &lt;0.5 nm 1\u03c3), requiring STI slurry selectivity consistently above 100:1 combined with WIWNU &lt;1.5%.<\/p>\r\n<h3>GAA Nanosheet: Sub-1 nm Nitride Budget<\/h3>\r\n<p>At sub-3 nm GAA nodes in production in 2025\u20132026, stacked nanosheet transistors introduce STI-like isolation steps with nitride budgets that approach the measurement uncertainty of standard metrology tools. Slurry SiO<sub>2<\/sub>:Si<sub>3<\/sub>N<sub>4<\/sub> selectivity above 150:1 is required, and endpoint precision at the angstrom level (optical interferometry with sub-5 \u00c5 3\u03c3 precision) is necessary. For a full analysis of STI and oxide CMP challenges at these nodes, see: <a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/Oxide-CMP-Slurry-Advanced-Nodes-FinFET-3D-NAND-GAA-Integration\/\" target=\"_blank\" rel=\"noopener noreferrer\">Oxide CMP Slurry for Advanced Nodes: FinFET, 3D NAND &amp; GAA Integration<\/a>.<\/p>\r\n<h2 id=\"sti-defects\">Dishing, Erosion &amp; Defect Management<\/h2>\r\n<p><strong>Dishing:<\/strong> In STI CMP, oxide dishing occurs when the polishing pad conforms to the wide isolation trench geometry and continues polishing the oxide fill below the surrounding nitride level. Dishing is most severe in wide features (&gt;1 \u00b5m isolation width) and is controlled by using higher-selectivity (and therefore softer, more selective) polishing conditions for the final touch-up step. Harder pads reduce dishing by resisting conformance to the trench, but must be balanced against uniformity requirements.<\/p>\r\n<p><strong>Erosion:<\/strong> STI erosion refers to the loss of Si<sub>3<\/sub>N<sub>4<\/sub> hard mask thickness in dense active-area arrays, caused by pattern-density-dependent polishing rate variation. Dense arrays present more ceria abrasive contact events per unit area than sparse features, increasing nitride removal rate locally despite high bulk selectivity. Erosion is managed through dummy active-area insertion in design-rule-sparse regions and through slurry selectivity optimization.<\/p>\r\n<p><strong>Ceria residue:<\/strong> Ceria particles that form Ce\u2013O\u2013Si bonds with the polished SiO<sub>2<\/sub> surface can persist through standard rinse steps and create particle contamination events if not removed by dedicated post-CMP cleaning. See our guide on <a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/Post-CMP-Cleaning-Oxide-Slurry-Chemistry-Equipment-Integration-Guide\/\" target=\"_blank\" rel=\"noopener noreferrer\">Post-CMP Cleaning for Oxide Slurry Processes<\/a> for ceria residue removal protocols. For a complete analysis of STI CMP defect types and detection, see: <a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/Oxide-CMP-Slurry-Defects-Root-Causes-Detection-Yield-Impact\/\" target=\"_blank\" rel=\"noopener noreferrer\">Oxide CMP Slurry Defects: Root Causes, Detection Methods &amp; Yield Impact<\/a>.<\/p>\r\n<div class=\"ocmp-back\">\u2190 Part of the JEEZ Oxide CMP Slurry series. Return to the <a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/oxide-cmp-slurry\/\" target=\"_blank\" rel=\"noopener noreferrer\">Oxide CMP Slurry: Complete Technical &amp; Procurement Guide<\/a><\/div>\r\n<hr class=\"ocmp-hr\" \/>\r\n<h2 id=\"sti-faq\">Frequently Asked Questions: STI CMP Slurry<\/h2>\r\n<div class=\"ocmp-faq\">\r\n<div class=\"ocmp-faq-item\">\r\n<p class=\"ocmp-faq-q\">Why must STI CMP use ceria slurry rather than colloidal silica?<\/p>\r\n<p class=\"ocmp-faq-a\">STI CMP requires SiO<sub>2<\/sub>:Si<sub>3<\/sub>N<sub>4<\/sub> selectivity of 50:1 to 200:1 to stop precisely on the Si<sub>3<\/sub>N<sub>4<\/sub> hard mask while removing oxide overburden. Colloidal silica achieves only 5:1 to 15:1 selectivity \u2014 using it for STI would result in excessive nitride removal and transistor defects. Ceria&#8217;s Ce\u2013O\u2013Si chemical bonding mechanism selectively accelerates oxide removal while leaving nitride largely inert, enabling the high selectivity STI demands.<\/p>\r\n<\/div>\r\n<div class=\"ocmp-faq-item\">\r\n<p class=\"ocmp-faq-q\">What is the role of polyacrylic acid (PAA) in STI ceria slurry?<\/p>\r\n<p class=\"ocmp-faq-a\">PAA serves two functions: it stabilizes ceria particles by adsorbing onto their positively-charged surface (preventing aggregation and micro-scratch defects), and it passivates Si<sub>3<\/sub>N<sub>4<\/sub> surfaces by forming a polymer blocking layer that reduces ceria contact with nitride. Together these effects increase SiO<sub>2<\/sub>:Si<sub>3<\/sub>N<sub>4<\/sub> selectivity from the intrinsic ceria level of ~20:1 to 50:1\u2013200:1. PAA concentration must be precisely controlled \u2014 a 20% change can shift selectivity by 2\u00d7.<\/p>\r\n<\/div>\r\n<div class=\"ocmp-faq-item\">\r\n<p class=\"ocmp-faq-q\">What is STI dishing and how is it controlled?<\/p>\r\n<p class=\"ocmp-faq-a\">STI dishing is the concave profile that develops in oxide-filled isolation trenches when the polishing pad conforms to the trench geometry and continues removing oxide below the surrounding nitride level. It is most severe in wide isolation features (&gt;1 \u00b5m). Control strategies include using harder polishing pads for reduced pad conformance, transitioning to a higher-selectivity low-pressure final step, and optimizing PAA concentration to reduce the mechanical removal contribution relative to chemical selectivity.<\/p>\r\n<\/div>\r\n<div class=\"ocmp-faq-item\">\r\n<p class=\"ocmp-faq-q\">What SiO\u2082:Si\u2083N\u2084 selectivity is required at the 5 nm FinFET node?<\/p>\r\n<p class=\"ocmp-faq-a\">At 5 nm FinFET, the total allowable nitride loss after STI CMP is approximately 2 nm, with fin height uniformity required within \u00b10.5 nm. These requirements translate to a need for SiO<sub>2<\/sub>:Si<sub>3<\/sub>N<sub>4<\/sub> selectivity consistently above 100:1, combined with WIWNU below 1.5% (1\u03c3). Achieving this requires advanced dual-polymer additive ceria formulations with point-of-use dilution protocols for in-situ selectivity fine-tuning.<\/p>\r\n<\/div>\r\n<div class=\"ocmp-faq-item\">\r\n<p class=\"ocmp-faq-q\">What is STI erosion and how is it different from dishing?<\/p>\r\n<p class=\"ocmp-faq-a\">STI erosion is the non-uniform thinning of the Si<sub>3<\/sub>N<sub>4<\/sub> hard mask in dense active-area arrays due to pattern-density-dependent polishing rate variation \u2014 the dense array presents more abrasive contact events than sparse regions, increasing local nitride removal despite high bulk selectivity. Dishing occurs within individual wide isolation features. Erosion occurs across groups of closely-spaced active areas. Both can occur simultaneously and are managed through design-level dummy pattern insertion and process-level selectivity optimization.<\/p>\r\n<\/div>\r\n<\/div>\r\n<\/article>\r\n<p><script type=\"application\/ld+json\">\r\n{\"@context\":\"https:\/\/schema.org\",\"@type\":\"FAQPage\",\"mainEntity\":[\r\n{\"@type\":\"Question\",\"name\":\"Why must STI CMP use ceria slurry rather than colloidal silica?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"STI CMP requires SiO2:Si3N4 selectivity of 50:1 to 200:1 to stop on the Si3N4 hard mask. Colloidal silica achieves only 5:1 to 15:1. Ceria's Ce-O-Si bonding mechanism selectively accelerates oxide removal while leaving nitride largely inert, enabling the high selectivity STI demands.\"}},\r\n{\"@type\":\"Question\",\"name\":\"What is the role of polyacrylic acid (PAA) in STI ceria slurry?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"PAA stabilizes ceria particles against aggregation and passivates Si3N4 surfaces with a polymer blocking layer. Together these effects increase selectivity from the intrinsic ceria level of ~20:1 to 50:1-200:1. A 20% change in PAA concentration can shift selectivity by 2x.\"}},\r\n{\"@type\":\"Question\",\"name\":\"What is STI dishing and how is it controlled?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"STI dishing is a concave profile in oxide-filled isolation trenches from pad conformance. Control strategies include harder polishing pads, a high-selectivity low-pressure final step, and optimized PAA concentration.\"}},\r\n{\"@type\":\"Question\",\"name\":\"What SiO2:Si3N4 selectivity is required at the 5 nm FinFET node?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"At 5 nm FinFET, selectivity consistently above 100:1 is required, with WIWNU below 1.5% (1sigma). This requires advanced dual-polymer additive ceria formulations with point-of-use dilution protocols.\"}},\r\n{\"@type\":\"Question\",\"name\":\"What is STI erosion?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"STI erosion is non-uniform Si3N4 thinning in dense active-area arrays from pattern-density-dependent polishing rate variation. Unlike dishing (within wide features), erosion occurs across groups of closely-spaced active areas and is managed through dummy pattern insertion and selectivity optimization.\"}}\r\n]}<\/script><\/p>","protected":false},"excerpt":{"rendered":"<p>\ud83d\udcc5 July 2026\u00b7\u23f1 19 min read\u00b7\u270d\ufe0f JEEZ Technical Team Shallow trench isolation (STI) CMP is among the most technically demanding polishing steps in front-end-of-line semiconductor processing. The requirement to achieve  &#8230;<\/p>","protected":false},"author":1,"featured_media":2462,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[9,59],"tags":[],"class_list":["post-2460","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-blog","category-industry"],"acf":[],"_links":{"self":[{"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/posts\/2460","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/comments?post=2460"}],"version-history":[{"count":3,"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/posts\/2460\/revisions"}],"predecessor-version":[{"id":2493,"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/posts\/2460\/revisions\/2493"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/media\/2462"}],"wp:attachment":[{"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/media?parent=2460"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/categories?post=2460"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/tags?post=2460"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}