{"id":2484,"date":"2026-07-16T13:18:16","date_gmt":"2026-07-16T05:18:16","guid":{"rendered":"https:\/\/jeez-semicon.com\/?p=2484"},"modified":"2026-07-16T13:32:35","modified_gmt":"2026-07-16T05:32:35","slug":"post-cmp-cleaning-oxide-slurry-chemistry-equipment-integration-guide","status":"publish","type":"post","link":"https:\/\/jeez-semicon.com\/zh\/blog\/post-cmp-cleaning-oxide-slurry-chemistry-equipment-integration-guide\/","title":{"rendered":"Post-CMP Cleaning for Oxide Slurry Processes: Chemistry, Equipment &amp; Integration Guide"},"content":{"rendered":"<p><style>\r\n\/* JEEZ Oxide CMP Cluster Article | Jizhi Electronic Technology Co., Ltd. | jeez-semicon.com *\/\r\n#jeez-ocmp *, #jeez-ocmp *::before, #jeez-ocmp *::after { box-sizing: border-box; }\r\n#jeez-ocmp { font-family: 'Inter', system-ui, -apple-system, sans-serif; font-size: 1rem; line-height: 1.78; color: #1E293B; max-width: 100%; }\r\n#jeez-ocmp h1 { font-family: 'Syne', sans-serif; font-size: clamp(1.75rem, 5vw, 2.875rem); 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font-weight: 700; font-size: 0.9375rem; color: #0B2444; padding: 1.125rem 1.25rem; background: #F5F8FF; display: block; margin: 0; border-bottom: 1px solid #E2EAF4; line-height: 1.45; }\r\n.ocmp-faq-a { padding: 1rem 1.25rem; font-size: 0.9rem; color: #334155; margin: 0; line-height: 1.72; }\r\n.ocmp-hr { border: none; border-top: 1px solid #E2EAF4; margin: 2.5rem 0; }\r\n@media (max-width: 640px) {\r\n  .ocmp-compare { grid-template-columns: 1fr; }\r\n  .ocmp-toc ol { grid-template-columns: 1fr; }\r\n  #jeez-ocmp h2 { margin-top: 2.25rem; }\r\n}\r\n<\/style><\/p>\r\n<article id=\"jeez-ocmp\">\r\n<div class=\"ocmp-meta\">\ud83d\udcc5 July 2026\u00b7\u23f1 17 min read\u00b7\u270d\ufe0f JEEZ Technical Team<\/div>\r\n<p class=\"ocmp-lead\">Post-CMP cleaning is an integral, yield-critical step in every oxide CMP process flow. The objective is complete removal of residual slurry particles, polishing byproducts, and surface contamination from the wafer before the next process step. The technical demands of post-CMP cleaning differ substantially between colloidal silica ILD processes and ceria STI processes \u2014 and using the wrong clean chemistry is a common root cause of persistent particle contamination and device-level yield loss. This guide covers the complete framework for oxide CMP post-clean process design. For an overview of oxide CMP slurry types, see our <a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/oxide-cmp-slurry\/\" target=\"_blank\" rel=\"noopener noreferrer\">Oxide CMP Slurry: Complete Technical Guide<\/a>.<\/p>\r\n<nav class=\"ocmp-toc\" aria-label=\"\u76ee\u5f55\">\r\n<p class=\"ocmp-toc-title\">\u76ee\u5f55<\/p>\r\n<ol>\r\n<li><a href=\"#pcc-why\">Why Post-CMP Cleaning Is Critical<\/a><\/li>\r\n<li><a href=\"#pcc-silica\">Cleaning for Colloidal Silica (ILD) Processes<\/a><\/li>\r\n<li><a href=\"#pcc-ceria\">Cleaning for Ceria (STI) Processes<\/a><\/li>\r\n<li><a href=\"#pcc-chemistry\">Chemistry Selection Guide<\/a><\/li>\r\n<li><a href=\"#pcc-equipment\">Equipment: Brush Scrubbers &amp; Megasonics<\/a><\/li>\r\n<li><a href=\"#pcc-ulk\">Ultra-Low-k Dielectric Compatibility<\/a><\/li>\r\n<li><a href=\"#pcc-integration\">Process Integration &amp; Qualification<\/a><\/li>\r\n<li><a href=\"#pcc-faq\">\u5e38\u89c1\u95ee\u9898<\/a><\/li>\r\n<\/ol>\r\n<\/nav>\r\n<h2 id=\"pcc-why\">Why Post-CMP Cleaning Is Critical<\/h2>\r\n<p>During oxide CMP, the wafer surface accumulates several categories of contamination that must be completely removed before the next deposition or lithography step:<\/p>\r\n<ul>\r\n<li><strong>Slurry abrasive particles:<\/strong> Colloidal silica or ceria nanoparticles present on the surface in the tens to hundreds of millions per wafer after polishing, depending on slurry concentration and rinse effectiveness. Even sub-50 nm particles can cause process integration problems in subsequent deposition steps if not removed.<\/li>\r\n<li><strong>Polishing byproducts:<\/strong> Dissolved SiO<sub>2<\/sub> (silicic acid Si(OH)<sub>4<\/sub>), Ce ion complexes (from ceria polishing), and pH adjustment chemicals (KOH, NH<sub>4<\/sub>OH, organic acids) remain in the residual slurry film after polishing and must be removed.<\/li>\r\n<li><strong>Organic residues:<\/strong> Surfactants, polymer additives (PAA, polyethylene glycol variants), and dispersants from the slurry formulation can adsorb onto the polished SiO<sub>2<\/sub> surface and create organic contamination at levels detectable by XPS or TOF-SIMS.<\/li>\r\n<li><strong>Pad debris:<\/strong> Microscopic fragments of polyurethane polishing pad material released during conditioning and polishing can be present on the wafer surface.<\/li>\r\n<\/ul>\r\n<p>Any of these contamination types, if not removed before the next process step, can affect device performance, reliability, or patterning accuracy. The most acute consequence is in FEOL: ceria or silica particles remaining on the wafer surface between STI CMP and gate oxide deposition can puncture the &lt;2 nm gate dielectric and create catastrophic device shorts. For the context of how these defects affect yield, see: <a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/Oxide-CMP-Slurry-Defects-Root-Causes-Detection-Yield-Impact\/\" target=\"_blank\" rel=\"noopener noreferrer\">Oxide CMP Slurry Defects: Root Causes, Detection Methods &amp; Yield Impact<\/a>.<\/p>\r\n<h2 id=\"pcc-silica\">Cleaning for Colloidal Silica (ILD) Processes<\/h2>\r\n<p>Post-CMP cleaning after ILD oxide CMP with colloidal silica slurry is the more straightforward of the two cleaning challenges. At the alkaline pH (10\u201311) of ILD polishing, colloidal silica particles carry a strong negative surface charge (zeta potential \u201320 to \u201340 mV). The polished SiO<sub>2<\/sub> surface is also negatively charged at alkaline pH. The electrostatic repulsion between the particles and the surface is the primary force resisting particle adhesion \u2014 but at near-zero distance (on the pad surface), van der Waals attraction overcomes the electrostatic repulsion and causes adsorption.<\/p>\r\n<h3>Standard ILD Clean Protocol<\/h3>\r\n<p>The standard post-CMP clean for colloidal silica ILD processes consists of:<\/p>\r\n<ul>\r\n<li><strong>On-pad DI water rinse:<\/strong> Performed immediately after polishing while the wafer is still on the pad, to dilute and begin removing bulk slurry before wafer surface drying occurs<\/li>\r\n<li><strong>Alkaline particle clean (SC-1):<\/strong> NH<sub>4<\/sub>OH:H<sub>2<\/sub>O<sub>2<\/sub>:H<sub>2<\/sub>O at volume ratios of 1:1:5 to 1:2:10, at 35\u201350\u00b0C. The alkaline pH (10\u201311) maintains the negative charge on both the silica particles and the SiO<sub>2<\/sub> surface, using the electrostatic repulsion force to detach particles. The low H<sub>2<\/sub>O<sub>2<\/sub> concentration oxidizes and solubilizes organic residues without aggressively oxidizing the surface.<\/li>\r\n<li><strong>PVA brush scrubbing:<\/strong> Polyvinyl alcohol (PVA) brushes rotating at 300\u2013600 RPM in the wet SC-1 environment provide mechanical assist to dislodge particles not removed by the chemical step alone<\/li>\r\n<li><strong>Megasonic rinse (optional but recommended for advanced nodes):<\/strong> High-frequency acoustic energy (400 kHz \u2013 1 MHz) applied during the DI rinse step provides cavitation-assisted particle detachment for sub-30 nm particles where van der Waals adhesion is particularly strong<\/li>\r\n<li><strong>Final DI rinse + spin dry:<\/strong> N<sub>2<\/sub>-assisted spin dry to prevent watermark defects<\/li>\r\n<\/ul>\r\n<p>With optimized SC-1 + brush scrubbing + megasonic rinsing, post-clean silica particle counts below 20 particles\/cm\u00b2 (&gt;50 nm PSL) are achievable on bare SiO<sub>2<\/sub> surfaces, meeting advanced-node gate oxide cleanliness requirements.<\/p>\r\n<h2 id=\"pcc-ceria\">Cleaning for Ceria (STI) Processes<\/h2>\r\n<p>Post-CMP cleaning after STI ceria polishing is substantially more challenging than silica ILD cleaning. The fundamental reason is the Ce\u2013O\u2013Si bonding mechanism: ceria particles that have formed chemical bonds with the SiO<sub>2<\/sub> polished surface are in a different adhesion state than physisorbed silica particles. Ce\u2013O\u2013Si bonds are not disrupted by alkaline SC-1 cleaning \u2014 alkaline conditions actually favor the Ce\u2013O\u2013Si bond stability \u2014 and PVA brush scrubbing alone cannot provide sufficient mechanical force to break the chemical bond for sub-100 nm ceria particles.<\/p>\r\n<h3>Ceria-Specific Clean Protocol<\/h3>\r\n<p>Effective ceria residue removal requires a dedicated acid-based cleaning step targeting Ce\u2013O\u2013Si bond reversal:<\/p>\r\n<ol>\r\n<li><strong>Dilute acid clean:<\/strong> Citric acid (0.1\u20131 wt%) or oxalic acid (0.05\u20130.5 wt%) solution at pH 2\u20134, at 25\u201340\u00b0C. Citric acid and oxalic acid are Ce ion chelating agents that competitively complex the Ce<sup>3+<\/sup>\/Ce<sup>4+<\/sup> ions at the particle\u2013surface interface, breaking the Ce\u2013O\u2013Si bond and allowing ceria particle detachment. Citric acid is preferred in most production applications due to its lower toxicity and better CMOS material compatibility. Contact time of 30\u201360 seconds is typically required for complete bond reversal at production-relevant particle loading levels.<\/li>\r\n<li><strong>DI rinse:<\/strong> Immediate thorough rinse to remove the acid clean and detached particles before re-adsorption occurs<\/li>\r\n<li><strong>Alkaline SC-1 clean + brush scrubbing:<\/strong> Follow-on SC-1 step (pH 10\u201311) removes any remaining physisorbed particles and organic residues, and reverses the surface charge to negative for electrostatic repulsion during final rinse<\/li>\r\n<li><strong>Megasonic-assisted DI rinse:<\/strong> Essential for ceria cleaning at advanced nodes \u2014 ceria&#8217;s strong but now chemically disrupted surface interaction benefits from acoustic energy to sweep detached particles from the surface before they can re-adsorb<\/li>\r\n<li><strong>Final DI rinse + spin dry<\/strong><\/li>\r\n<\/ol>\r\n<p>The acid cleaning step is the critical differentiator for ceria vs. silica post-CMP cleaning. Fabs that attempt to clean ceria STI wafers with SC-1 alone will see ceria residue counts 10\u2013100\u00d7 higher than with the acid clean step included.<\/p>\r\n<h2 id=\"pcc-chemistry\">Chemistry Selection Guide<\/h2>\r\n<div class=\"ocmp-table-wrap\">\r\n<table>\r\n<thead>\r\n<tr>\r\n<th>Cleaning Step<\/th>\r\n<th>Chemistry \/ Conditions<\/th>\r\n<th>Target<\/th>\r\n<th>Applicable Slurry<\/th>\r\n<\/tr>\r\n<\/thead>\r\n<tbody>\r\n<tr>\r\n<td class=\"ocmp-td-label\">On-Pad Rinse<\/td>\r\n<td>DI water, ambient, 30 sec<\/td>\r\n<td>Bulk slurry dilution<\/td>\r\n<td>All oxide CMP<\/td>\r\n<\/tr>\r\n<tr>\r\n<td class=\"ocmp-td-label\">Acid Clean (ceria)<\/td>\r\n<td>Citric acid 0.1\u20131 wt%, pH 2\u20134, 35\u00b0C<\/td>\r\n<td>Ce\u2013O\u2013Si bond reversal<\/td>\r\n<td>Ceria STI only<\/td>\r\n<\/tr>\r\n<tr>\r\n<td class=\"ocmp-td-label\">SC-1 Alkaline<\/td>\r\n<td>NH<sub>4<\/sub>OH:H<sub>2<\/sub>O<sub>2<\/sub>:H<sub>2<\/sub>O 1:1:5, pH 10, 40\u00b0C<\/td>\r\n<td>Particle lift-off, organics<\/td>\r\n<td>All oxide CMP<\/td>\r\n<\/tr>\r\n<tr>\r\n<td class=\"ocmp-td-label\">Brush Scrub<\/td>\r\n<td>PVA brush, 400\u2013600 RPM, in-situ with SC-1<\/td>\r\n<td>Mechanical particle removal<\/td>\r\n<td>All oxide CMP<\/td>\r\n<\/tr>\r\n<tr>\r\n<td class=\"ocmp-td-label\">Megasonic Rinse<\/td>\r\n<td>DI water, 400 kHz\u20131 MHz, 30 sec<\/td>\r\n<td>Sub-30 nm particle removal<\/td>\r\n<td>Advanced-node; recommended for ceria<\/td>\r\n<\/tr>\r\n<tr>\r\n<td class=\"ocmp-td-label\">SC-2 (optional)<\/td>\r\n<td>HCl:H<sub>2<\/sub>O<sub>2<\/sub>:H<sub>2<\/sub>O 1:1:6, pH ~0<\/td>\r\n<td>Metal ion removal (K<sup>+<\/sup>, Fe, Ca)<\/td>\r\n<td>FEOL post-ILD (if K<sup>+<\/sup> concern)<\/td>\r\n<\/tr>\r\n<tr>\r\n<td class=\"ocmp-td-label\">UV-Ozone (optional)<\/td>\r\n<td>UV light + O<sub>3<\/sub>, ambient<\/td>\r\n<td>Residual organic removal<\/td>\r\n<td>Advanced-node when XPS organic spec is tight<\/td>\r\n<\/tr>\r\n<\/tbody>\r\n<\/table>\r\n<\/div>\r\n<h2 id=\"pcc-equipment\">Equipment: Brush Scrubbers &amp; Megasonics<\/h2>\r\n<h3>PVA Brush Scrubbers<\/h3>\r\n<p>PVA (polyvinyl alcohol) brushes are the primary mechanical cleaning tool in post-CMP cleaning. They are porous, hydrophilic cylinders that rotate against the wafer surface while the chemical clean solution flows over the wafer. Key operating parameters:<\/p>\r\n<ul>\r\n<li><strong>Brush rotation speed:<\/strong> 300\u2013600 RPM (front surface); controlled to avoid mechanical damage to low-k dielectrics at downforce &gt;1 psi<\/li>\r\n<li><strong>Brush downforce:<\/strong> 0.2\u20130.8 psi for standard oxide; reduced to 0.1\u20130.3 psi for ULK-exposed surfaces<\/li>\r\n<li><strong>Brush conditioning:<\/strong> New PVA brushes must be conditioned in DI water for 30\u201360 minutes to reach equilibrium water content before use; dry brushes can scratch wafer surfaces<\/li>\r\n<li><strong>Brush replacement:<\/strong> PVA brushes should be replaced at fixed cycle counts (typically 2,000\u20135,000 wafer passes) or when surface particle counts trend upward over successive qualification monitors<\/li>\r\n<\/ul>\r\n<h3>Megasonic Cleaning<\/h3>\r\n<p>Megasonic systems use high-frequency acoustic transducers (400 kHz to 1 MHz) mounted at the bottom of a DI water tank or in a flow-through cleaning module to create oscillating micro-streaming and micro-bubble activity near the wafer surface. The acoustic energy provides sufficient hydrodynamic shear force to dislodge sub-30 nm particles \u2014 particularly important for ceria residue removal \u2014 where brush contact cannot reach due to surface topography (via bottoms, fin sidewalls) and where adhesion forces scale unfavorably with decreasing particle size.<\/p>\r\n<p>Megasonic cleaning is more effective at 1 MHz than at lower frequencies for nano-particle removal, because higher frequency creates smaller, more uniformly distributed bubble cavitation that provides finer-scale shear forces. However, high-intensity megasonic cleaning can damage fragile low-k dielectric structures; frequency, power density, and exposure time must be optimized for each specific application to maximize particle removal without creating acoustic-induced defects.<\/p>\r\n<h2 id=\"pcc-ulk\">Ultra-Low-k Dielectric Compatibility<\/h2>\r\n<p>At advanced BEOL nodes (sub-14 nm), porous ultra-low-k (ULK) dielectric films with k &lt; 2.5 are exposed at via sidewalls and CMP surfaces during ILD polishing. Several commonly used post-CMP cleaning chemicals are incompatible with ULK pore structures:<\/p>\r\n<ul>\r\n<li><strong>Surfactants in SC-1:<\/strong> High-surfactant SC-1 formulations can infiltrate ULK pores, increasing the effective dielectric constant (k) of the film by filling pores with residual surfactant. ULK-compatible SC-1 formulations use reduced or eliminated surfactant concentrations.<\/li>\r\n<li><strong>High-concentration NH<sub>4<\/sub>OH:<\/strong> Concentrated NH<sub>4<\/sub>OH can etch ULK dielectric surfaces, slightly increasing k. Reduced NH<sub>4<\/sub>OH concentrations (0.05\u20130.1 vol% rather than 0.25\u20131 vol%) are used for ULK-compatible SC-1 formulations.<\/li>\r\n<li><strong>H<sub>2<\/sub>O<sub>2<\/sub> concentration:<\/strong> At concentrations above 1 vol%, H<sub>2<\/sub>O<sub>2<\/sub> can oxidize the carbon-containing groups in SiCOH ULK films, increasing k and reducing the hydrophobicity that protects pores from moisture.<\/li>\r\n<\/ul>\r\n<p>For sub-7 nm BEOL ILD CMP with ULK dielectrics, cleaning chemistry must be qualified not just for particle removal efficacy but for k value maintenance in the ULK film, measured by C-V testing on patterned capacitor structures before and after the full CMP + clean sequence.<\/p>\r\n<h2 id=\"pcc-integration\">Process Integration &amp; Qualification<\/h2>\r\n<p>Post-CMP cleaning process qualification for oxide slurry should include the following characterization matrix:<\/p>\r\n<ul>\r\n<li>Particle removal efficiency (PRE) for the specific slurry type: PRE = (pre-clean count \u2013 post-clean count) \/ pre-clean count \u00d7 100%. Target PRE &gt;99.9% for advanced-node applications.<\/li>\r\n<li>Surface roughness after clean (AFM): Ra should be \u2264 post-CMP Ra before cleaning; any roughness increase indicates surface etching by the clean chemistry<\/li>\r\n<li>Metal ion contamination (VPD-ICP-MS): K<sup>+<\/sup>, Ce<sup>3+<\/sup>, Na<sup>+<\/sup>, Fe<sup>2+<\/sup> at the wafer surface after clean, verified to meet gate oxide contamination specifications<\/li>\r\n<li>Organic residue (XPS or TOF-SIMS): Carbon surface concentration after clean vs. specification limit<\/li>\r\n<li>ULK k-value retention (C-V): For advanced BEOL applications involving ULK<\/li>\r\n<\/ul>\r\n<p>A complete oxide CMP + post-CMP clean integration must be qualified as a coupled system \u2014 the clean chemistry and the slurry interact through the surface state left by polishing. Changing either without requalifying the other can create unexpected defect modes.<\/p>\r\n<div class=\"ocmp-back\">\u2190 Part of the JEEZ Oxide CMP Slurry series. Return to the <a href=\"https:\/\/jeez-semicon.com\/zh\/blog\/oxide-cmp-slurry\/\" target=\"_blank\" rel=\"noopener noreferrer\">Oxide CMP Slurry: Complete Technical &amp; Procurement Guide<\/a><\/div>\r\n<hr class=\"ocmp-hr\" \/>\r\n<h2 id=\"pcc-faq\">Frequently Asked Questions: Post-CMP Cleaning for Oxide Slurry<\/h2>\r\n<div class=\"ocmp-faq\">\r\n<div class=\"ocmp-faq-item\">\r\n<p class=\"ocmp-faq-q\">Why can&#8217;t standard SC-1 cleaning remove ceria particles after STI CMP?<\/p>\r\n<p class=\"ocmp-faq-a\">Ceria particles form Ce\u2013O\u2013Si chemical bonds with the SiO<sub>2<\/sub> polished surface during STI CMP. These bonds are not disrupted by alkaline SC-1 cleaning (pH 10\u201311) \u2014 alkaline conditions actually stabilize Ce\u2013O\u2013Si bonds. Effective ceria removal requires dilute acidic cleaning chemistry (citric acid 0.1\u20131 wt% at pH 2\u20134) that chelates Ce ions and competitively breaks the Ce\u2013O\u2013Si surface bond, allowing particle detachment before the subsequent alkaline SC-1 and rinse steps.<\/p>\r\n<\/div>\r\n<div class=\"ocmp-faq-item\">\r\n<p class=\"ocmp-faq-q\">What is the best acid chemistry for ceria residue removal?<\/p>\r\n<p class=\"ocmp-faq-a\">Citric acid (0.1\u20131 wt%, pH 2\u20134, 35\u201340\u00b0C) is the most widely used and CMOS-compatible choice for ceria residue removal. Oxalic acid (0.05\u20130.5 wt%) is also effective and sometimes faster at Ce\u2013O\u2013Si bond reversal, but requires more careful handling due to its lower safety profile. Both are selective for Ce ion complexation without aggressively etching SiO<sub>2<\/sub> or Si<sub>3<\/sub>N<sub>4<\/sub> surfaces at the recommended concentrations.<\/p>\r\n<\/div>\r\n<div class=\"ocmp-faq-item\">\r\n<p class=\"ocmp-faq-q\">What particle removal efficiency should post-CMP cleaning achieve?<\/p>\r\n<p class=\"ocmp-faq-a\">For advanced-node applications (14 nm and below), particle removal efficiency (PRE) of &gt;99.9% is the standard target \u2014 equivalent to reducing post-CMP particle count from millions to thousands per wafer. For mature-node applications, PRE of 99.5\u201399.9% is typically acceptable. PRE is measured by wafer surface scanning before and after clean, with detection threshold typically 50 nm PSL equivalent for advanced-node gate oxide cleanliness specifications.<\/p>\r\n<\/div>\r\n<div class=\"ocmp-faq-item\">\r\n<p class=\"ocmp-faq-q\">Can megasonic cleaning damage low-k dielectrics?<\/p>\r\n<p class=\"ocmp-faq-a\">Yes. High-intensity megasonic cleaning can damage fragile porous low-k (ULK) dielectric structures at sub-14 nm BEOL. The acoustic cavitation that effectively removes small particles can also delaminate fragile ULK films from underlying layers or collapse pore structures in highly porous films. Megasonic parameters (frequency, power density, exposure time) must be specifically optimized for each ULK material and trench aspect ratio to balance particle removal efficiency against structural integrity of the dielectric.<\/p>\r\n<\/div>\r\n<div class=\"ocmp-faq-item\">\r\n<p class=\"ocmp-faq-q\">Should post-CMP cleaning be qualified separately from the CMP process?<\/p>\r\n<p class=\"ocmp-faq-a\">No \u2014 they should be qualified as a coupled system. The surface state left by CMP (particle type, surface bond state, residual chemistry) determines what cleaning approach is required and how effective it will be. Changing the slurry formulation without requalifying the cleaning protocol, or changing the cleaning chemistry without reassessing its interaction with the slurry residue, can create new defect modes that were not present in the original qualification. CMP + post-clean qualification must be done together, using the production-representative slurry on the production-representative cleaning tool with the production-representative cleaning chemistry.<\/p>\r\n<\/div>\r\n<\/div>\r\n<\/article>\r\n<p><script type=\"application\/ld+json\">\r\n{\"@context\":\"https:\/\/schema.org\",\"@type\":\"FAQPage\",\"mainEntity\":[\r\n{\"@type\":\"Question\",\"name\":\"Why can standard SC-1 cleaning not remove ceria particles after STI CMP?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"Ceria particles form Ce-O-Si chemical bonds with the SiO2 surface during STI CMP. Alkaline SC-1 (pH 10-11) stabilizes these bonds rather than breaking them. Effective removal requires dilute acidic chemistry (citric acid 0.1-1 wt%, pH 2-4) to chelate Ce ions and break the Ce-O-Si bond before alkaline rinse.\"}},\r\n{\"@type\":\"Question\",\"name\":\"What is the best acid chemistry for ceria residue removal?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"Citric acid (0.1-1 wt%, pH 2-4, 35-40\u00b0C) is the most widely used CMOS-compatible choice. Oxalic acid (0.05-0.5 wt%) is also effective but requires more careful handling. Both chelate Ce ions without aggressively etching SiO2 or Si3N4 surfaces.\"}},\r\n{\"@type\":\"Question\",\"name\":\"What particle removal efficiency should post-CMP cleaning achieve?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"For advanced nodes (14 nm and below), particle removal efficiency (PRE) above 99.9% is the standard target. For mature nodes, 99.5-99.9% is typically acceptable. PRE is measured by wafer surface scanning at 50 nm PSL detection threshold.\"}},\r\n{\"@type\":\"Question\",\"name\":\"Can megasonic cleaning damage low-k dielectrics?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"Yes. High-intensity megasonics can delaminate or collapse porous ULK films. Frequency, power density, and exposure time must be optimized for each ULK material and trench geometry to balance particle removal against structural integrity.\"}},\r\n{\"@type\":\"Question\",\"name\":\"Should post-CMP cleaning be qualified separately from the CMP process?\",\"acceptedAnswer\":{\"@type\":\"Answer\",\"text\":\"No - they must be qualified as a coupled system. The surface state from CMP determines cleaning requirements. Changing either slurry or cleaning chemistry independently can create new defect modes not present in the original qualification.\"}}\r\n]}<\/script><\/p>","protected":false},"excerpt":{"rendered":"<p>\ud83d\udcc5 July 2026\u00b7\u23f1 17 min read\u00b7\u270d\ufe0f JEEZ Technical Team Post-CMP cleaning is an integral, yield-critical step in every oxide CMP process flow. The objective is complete removal of residual slurry  &#8230;<\/p>","protected":false},"author":1,"featured_media":2486,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[9,59],"tags":[],"class_list":["post-2484","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-blog","category-industry"],"acf":[],"_links":{"self":[{"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/posts\/2484","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/comments?post=2484"}],"version-history":[{"count":3,"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/posts\/2484\/revisions"}],"predecessor-version":[{"id":2497,"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/posts\/2484\/revisions\/2497"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/media\/2486"}],"wp:attachment":[{"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/media?parent=2484"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/categories?post=2484"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/jeez-semicon.com\/zh\/wp-json\/wp\/v2\/tags?post=2484"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}