How to Specify a Polishing Template: 6 Parameters Engineers Must Define

These two values are the dimensional foundation of the entire template specification. They directly determine the two most important machined dimensions: work-hole diameter and work-hole depth.

Work-hole diameter is calculated as the wafer OD plus a radial clearance of 0.2–0.5 mm. This clearance is not arbitrary — it must be tight enough to prevent lateral wafer slippage during polishing (which causes scratch defects and non-circular TTV patterns) while loose enough to allow the wafer to seat cleanly into the pocket without stress-induced bow. For 300 mm silicon, a radial clearance of 0.25–0.35 mm is typical. For fragile compound semiconductor substrates (GaAs, InP), tighter clearances of 0.15–0.25 mm are used to reduce lateral movement risk, but require more precise incoming wafer OD control to prevent jamming.

Work-hole depth is the most critical single dimension in the polishing template. It controls the mechanical “stand-off” of the wafer surface relative to the polishing pad contact plane, which directly determines the downforce applied to the wafer under carrier head load. Too deep, and the wafer is recessed below the pad contact plane — polishing pressure is reduced and material removal rate drops, while the edge sees relatively higher pressure, producing edge rollup. Too shallow, and the wafer protrudes above the template surface — edge pressure is reduced and edge rolloff results, with center-high TTV as a secondary effect.

The most common specification error related to FTT is confusing the incoming wafer thickness (before polishing) with the final target thickness (after polishing). Work-hole depth is set against FTT — the thickness of the wafer when it exits the polisher. Specifying work-hole depth against incoming wafer thickness produces a template that is systematically too deep by the material removal amount, which is typically 5–50 µm depending on the process.

The polishing template must fit precisely within the carrier head’s retaining ring pocket. Get this wrong and the template physically cannot be installed — there is no partial credit for a near-fit geometry. The carrier head information required to specify a template breaks down into three sub-parameters.

Machine platform and carrier head model. Common platforms each have a documented nominal template geometry: Strasbaugh 6EC and 6DS-SP, Peter Wolters AC2000 and AC3000, Speedfam 9B and 9DSP, Lapmaster 20S and 36S, DISCO DAS8830. For well-established platforms with documented catalog templates, the carrier head geometry is known and the template OD, thickness range, and pocket depth are derivable from existing product data. For lesser-known or OEM platforms, a direct measurement of the carrier head pocket is required.

Retaining ring inner diameter. This is the inner diameter of the retaining ring that constrains the template within the carrier head. The template OD must be 0.1–0.3 mm smaller than the retaining ring ID to allow free thermal expansion while preventing lateral play that would shift the template’s work hole(s) out of concentricity with the carrier head axis. Provide this dimension with a tolerance statement — “approximately 300 mm” is not a usable specification.

Carrier head pocket depth. The recess in the carrier head into which the template seats. Template total thickness (carrier plate + backing pad) must be compatible with this pocket depth to ensure the template seats flat, the backing pad is not over-compressed in the unloaded condition, and the retaining ring can be installed and removed without excessive force.

Carrier plate material selection is a chemical engineering decision, not a procurement convenience. The carrier plate is in continuous contact with polishing slurry throughout every polishing cycle. Over time, an incompatible material will swell, delaminate, leach contaminants into the slurry, and change dimensions — all of which degrade process performance and, in severe cases, contaminate the wafer surface.

Three material families cover the vast majority of semiconductor polishing applications. The selection logic follows a simple hierarchy: start with FR-4, step up to G-10 if the slurry is mildly acidic, and specify CXT-grade if the chemistry is outside the laminate envelope entirely. For the detailed material property comparison, our article on FR-4 vs G-10 fiberglass polishing templates covers the full property data.

When specifying carrier plate material, do not rely on slurry product names alone — specify the pH range and any oxidant components explicitly. The same slurry brand may be formulated differently for different substrate applications, and supplier formulations change over time. A material selection made against “Cabot Microelectronics SS25” slurry in 2018 may not be valid against the current formulation of the same product.

For SiC CMP applications, the CXT seamless grade is not optional — it is a process requirement. Standard FR-4 templates in KMnO₄ slurry at pH 2–4 typically show visible delamination within 15–25 polishing cycles, followed by progressive slurry penetration into the carrier plate laminate, dimensional swelling, and ultimately work-hole geometry distortion that produces systematic TTV excursions. Full technical guidance on SiC-specific template requirements is in our SiC wafer polishing template guide.

The backing pad is the mechanical interface between the rigid carrier plate and the wafer backside. Its compliance — the combination of Shore A hardness, thickness, and internal porosity — determines how faithfully the carrier head’s applied pressure is distributed across the wafer area, and how much the wafer is allowed to flex relative to the polishing pad surface.

Specifying backing pad hardness requires knowing three things about your process: the substrate material and its hardness, the nominal carrier head process pressure (in g/cm² or psi), and the target TTV and edge profile requirements. The relationship between these inputs and optimal pad hardness follows a consistent pattern:

• Hard substrates + high process pressure (SiC CMP at 5–7 psi) → hard backing pad (Shore A 70–85). A soft pad would over-compress under high load, reducing effective work-hole depth control and creating TTV instability over the template’s service life as the pad fatigues.
• Soft or fragile substrates at moderate pressure (GaAs, thin Si at 1–3 psi) → soft pad (Shore A 30–55). The soft pad absorbs carrier head pressure non-uniformities and reduces the risk of stress concentrations at the wafer edge that could initiate fracture in brittle III-V materials.
• Standard Si SSP at nominal pressure (2–5 psi) → medium pad (Shore A 55–75). This is the most common configuration and the one for which standard catalog templates are optimized.

Pad thickness matters independently of hardness. Thicker pads provide greater compliance and are preferred for applications where the carrier head has a non-uniform pressure profile (a common characteristic of older or heavily worn carrier heads). Thinner pads provide more precise depth control and are preferred for ultra-tight TTV applications where every micrometer of pad compression must be accounted for.

The edge enhancement ring (EER) is an optional but increasingly important feature in polishing templates for advanced process nodes. Its purpose is to modify the pressure distribution in the annular zone between the wafer OD and the work-hole wall — the region that controls edge flatness and determines the size of the edge exclusion zone.

Without an EER, the template in the annular zone adjacent to the wafer edge provides relatively little mechanical support to the polishing pad. The pad deflects slightly under the wafer edge, reducing local contact pressure and creating a characteristic “rolloff” — a zone of lower-than-average material removal rate that leaves the wafer edge thicker than the center. For 300 mm silicon wafers at legacy process nodes, a 3–5 mm edge exclusion zone was standard and acceptable. For advanced logic and memory at 5 nm and below, edge exclusion targets of 1.0–1.5 mm require a polishing template with engineered edge support.

The EER achieves this by adding a precision-machined annular feature on the template back face, concentrically positioned relative to the work hole. This feature increases local stiffness in the edge zone, countering the pad deflection that causes rolloff. The geometry of the EER — inner and outer diameter, height, material — is custom-engineered to the specific wafer diameter, final thickness, backing pad specification, and target edge profile. Read the detailed technical engineering background in our article on edge profile control and edge exclusion reduction.

To specify the EER requirement, provide two inputs: your target edge exclusion in millimeters, and your historical edge profile data (maximum rolloff height at 1 mm and 2 mm from the wafer edge) from your current process. If you have no historical data, the EER geometry is initially estimated from the wafer diameter and backing pad specification, then iterated based on first-article process data.

Polishing templates are assembled in a cleanroom environment, and the class of that environment determines the maximum particle population on the template surface at the point of packaging. For most semiconductor production applications, ISO Class 5 (Class 100) assembly is adequate — this is Jizhi’s standard production environment. For advanced front-end-of-line applications at 28 nm and below, where wafer surface particle budgets are extremely tight, ISO Class 4 assembly (10× cleaner than Class 5) may be specified.

Beyond cleanroom class, there are four documentation elements that should be explicitly stated in the specification, as they form the quality system backbone for the template’s entire production life:

• Raw material traceability retention period. Standard Jizhi practice is a minimum of 5 years, covering carrier plate material, backing pad compound, and all adhesive systems. If your quality system or customer audit requirements mandate a longer retention period, specify this explicitly.
• Certificate of Conformance (CoC). A written statement confirming that the delivered lot was manufactured in accordance with the released drawing and all specified quality requirements. This is standard for semiconductor consumable supply; confirm whether your receiving inspection requires a per-lot or per-unit CoC.
• Material certificates. Raw material mill certificates for the carrier plate laminate, confirming composition, dielectric properties, and dimensional conformance to the relevant NEMA or IPC standard. Required for most semiconductor quality audits.
• Per-unit dimensional inspection data. For high-specification applications, a CMM measurement report for each individual template (rather than a sampling-based lot report) may be required. This increases cost and lead time; specify only if your process control requirements genuinely demand it.