Common Defects in Mechanical Polishing and CMP: Root Cause Analysis and Corrective Actions

Publicado en: 2026年5月26日Vistas: 226
Process Engineering — Defect Reference

A comprehensive troubleshooting reference for process engineers — covering macro-scratches, micro-scratches, dishing, erosion, delamination, orange peel, embedded abrasive, and edge roll-off in both industrial mechanical polishing and semiconductor CMP applications.

Updated: May 2026 By JEEZ Engineering Team ~1,400 words

Polishing defects represent some of the highest-impact yield detractors in both semiconductor manufacturing and precision industrial fabrication. In a semiconductor fab, a single CMP-induced scratch event on a 300 mm wafer can kill hundreds of die. In pharmaceutical equipment manufacturing, a surface defect that fails ASME BPE Ra requirements requires the entire polishing sequence to be restarted. In both contexts, rapid and accurate root cause identification — followed by a targeted corrective action — is the difference between a controlled process and chronic yield loss. This article is a structured technical troubleshooting reference for the most common polishing defects. For foundational polishing context, see our complete mechanical polishing guide.

1. Defect Classification Framework

Polishing defects can be organized by their root cause domain — which helps direct the troubleshooting investigation to the correct process variable:

Root Cause DomainTypical DefectsFirst Investigation Step
Consumable qualityMacro-scratch, micro-scratch, residual metalReview slurry LPC data; check pad condition; lot change history
Process parameterDishing, erosion, edge roll-off, delaminationReview pressure, velocity, polish time, endpoint signal
Workpiece / substrateOrange peel, embedded abrasive, pittingInspect incoming material; review prior process steps
Grit sequence / operatorResidual coarse scratches, smearing, glazingVerify grit sequence records; operator qualification check
Tool / equipmentRadial scratch patterns, WIWNU excursionRun bare wafer check; inspect retaining ring; verify conditioner

2. Macro-Scratches and Micro-Scratches

⚠️
Macro-Scratches / Micro-Scratches
Applicable to: CMP (wafer) and industrial mechanical polishing
Root Causes

Large particle contamination (LPC) in CMP slurry — particles >0.5 µm act as micro-cutting tools. Pad debris agglomerates. Grit step skipped in industrial polishing. Diamond conditioner shedding. Tool contamination (previous lot residue).

Detection

KLA bright-field or dark-field wafer inspection (CMP). Visual inspection under raking light for industrial SS. Profilometer Ra spike at scratch location. Macro: visible >1 µm wide; micro: detected by high-sensitivity inspection tool.

Corrective Actions

Implement in-line 0.2 µm slurry filtration at point-of-use. Add real-time LPC monitor (AccuSizer or equivalent) with auto-abort interlock. Enforce pad conditioning protocol — dressing rate, sweep speed, pressure. Perform tool qualification run with bare Si wafer after any wet maintenance. For industrial polishing: never skip grit steps; verify scratch removal before advancing.

CMP Slurry Shelf Life — A Frequently Overlooked Scratch Source

Colloidal silica CMP slurry undergoes particle agglomeration if stored beyond its stated shelf life, if frozen and thawed, or if exposed to excessive heat. Agglomerated particles behave as large particles in the CMP tool and generate macro-scratches indistinguishable from true LPC events. Always check slurry manufacturing date and storage conditions when investigating a scratch excursion, and enforce first-in-first-out (FIFO) slurry inventory management.

3. Dishing (CMP — Cu/W)

🔽
Dishing
Applicable to: Cu damascene CMP, W plug CMP
Root Causes

Cu or W removal rate significantly exceeds surrounding dielectric removal rate after metal clearing. The soft metal is over-polished while the pad continues to remove metal in wide, recessed features. Excessive over-polish time compounds the effect. High BTA concentration in Cu slurry can inhibit Cu dissolution and paradoxically increase dishing at low pattern densities.

Detection

AFM or contact profilometer measurement across wide Cu lines post-CMP. Spectroscopic reflectometry for in-line monitoring. Dishing values are typically specified at maximum wide metal feature (e.g., 100 µm Cu line): spec typically <30 nm for advanced Cu interconnect.

Corrective Actions

Implement robust optical endpoint detection to minimize over-polish time. Transition to low-downforce step-2 polish with high-oxide-selectivity slurry. Optimize BTA concentration for your pattern density distribution. Use a barrier-selective slurry in step-2 that removes residual Cu/barrier without further attacking recessed Cu. Design rule enforcement: limit maximum isolated Cu feature width in critical layers.

4. Erosion and Pattern Density Effects

📉
Erosion (Oxide Loss in High-Density Metal Arrays)
Applicable to: Cu damascene CMP, STI CMP
Root Causes

In high pattern density regions (e.g., 50% metal fill), the effective pad-wafer contact is softer and the local removal rate is higher than in low-density regions. Oxide between metal lines is removed faster than in sparse areas. The result is a height difference across the die between dense and isolated regions — the “density-dependent erosion” or “micro-loading” effect.

Detection

Multi-point spectroscopic reflectometry or ellipsometry mapping post-CMP. Cross-sectional TEM at dense vs. isolated regions. Erosion measured as oxide loss (nm) at dense metal array versus field oxide reference.

Corrective Actions

Use a slurry with high oxide-to-metal selectivity in bulk polish step to reduce oxide removal at dense regions. Adjust retaining ring and multi-zone carrier pressure to profile the within-wafer removal rate for your specific die layout. Implement dummy metal fill rules in design to equalize pattern density across the die. Optimize pad stiffness — harder pad reduces the pattern density effect (higher planarity efficiency).

5. Delamination

💥
Delaminación
Applicable to: low-k dielectric CMP, thin film stack polishing
Root Causes

Shear stress at pad–wafer interface exceeds the adhesion strength of the low-k dielectric or cap layer interface. Particularly severe for ultra-low-k (k < 2.5) porous dielectrics with Young’s modulus < 5 GPa. Excessive polish pressure or velocity concentrates stress at film interfaces. Water uptake by the porous dielectric during slurry exposure weakens the structure.

Detection

Acoustic emission monitoring (in-situ). KLA inspection for delamination fragments. Cross-sectional SEM/TEM for interface integrity verification. Electrical test: leakage current increase between adjacent metal lines indicates dielectric delamination.

Corrective Actions

Reduce down-force to minimum that achieves required removal rate. Switch to a compliant, low-modulus polishing pad. Minimize slurry contact time with exposed low-k surfaces. Optimize cap layer adhesion (hardmask selection). For porous ultra-low-k: consider UV cure before CMP to improve mechanical strength of the dielectric film.

6. Orange Peel (Industrial Metal Polishing)

🍊
Orange Peel Texture
Applicable to: stainless steel, hardened tool steel, aluminum alloy polishing
Root Causes

Coarse grain structure in the workpiece metal (common in castings, heavily cold-worked stock, or improperly annealed material). Individual grains polish at different rates due to crystallographic orientation differences, creating a bumpy, low-spatial-frequency surface texture. Also caused by transitioning to fine grit too early, before coarse defects are fully removed.

Detection

Visual inspection under raking (oblique) light reveals the matte, dimpled texture. Not detectable by Ra alone — Ra may appear within spec while the orange peel spatial wavelength (0.5–5 mm) contributes to Wa (waviness) rather than Ra. Optical profilometer shows characteristic mounds at grain scale.

Corrective Actions

Anneal the workpiece to refine grain structure before polishing if possible. Return to a coarser grit stage to re-establish a uniform scratch texture before progressing. For tool steels: confirm the hardness range before selecting abrasive; severely over-hardened steel may require soft annealing before polishing. Avoid excessive dwell in early buffing stages before the scratch pattern from prior steps is fully removed.

7. Embedded Abrasive

🔴
Embedded Abrasive Particles
Applicable to: soft metal polishing (Al, Cu, Mg); industrial mechanical polishing
Root Causes

Hard abrasive particles (Al₂O₃, SiC) pressed into a soft metal surface under polishing pressure become mechanically trapped in the subsurface deformation zone. The softer the metal and the harder the abrasive, the higher the embedding tendency. Also occurs when abrasive media is used without adequate flushing, allowing spent particles to accumulate and agglomerate on the surface.

Detection

EDS (energy-dispersive X-ray spectroscopy) analysis detects embedded Si or Al on a Cu or Al surface. Scanning electron microscopy (SEM) reveals sub-surface particle inclusions. In pharmaceutical equipment: ICP-MS analysis of rinse water detects particle contamination from embedded abrasive shedding during CIP.

Corrective Actions

Follow industrial mechanical polishing with electropolishing — the anodic dissolution removes the cold-worked surface layer containing embedded particles. For CMP: use colloidal slurry (smoother particles, lower embedding tendency) rather than fumed silica on soft metal layers. Ensure adequate slurry flow and pad conditioning to continuously remove spent abrasive from the pad surface rather than recirculating it. Post-CMP brush cleaning removes residual surface particles.

8. Edge Roll-Off and Corner Rounding

📐
Edge Roll-Off / Corner Rounding
Applicable to: CMP (wafer edge exclusion), industrial polishing of flat plates
Root Causes

At the wafer edge (or workpiece boundary), the pad complies downward as it extends beyond the edge, increasing local contact pressure and removal rate. The edge of the wafer sees higher removal rate than the center, resulting in a thinned, rolled-off edge profile. Retaining ring wear or incorrect retaining ring force settings amplify this effect in CMP.

Detection

Post-CMP film thickness mapping (spectroscopic reflectometry): characteristic “bull’s-eye” pattern with thin edge ring. Edge exclusion zone (typically 2–3 mm from wafer edge) is excluded from process window specification. For industrial plates: profilometer measurement at part edges confirms radius increase.

Corrective Actions

Optimize retaining ring down-force: increasing retaining ring force reduces edge roll-off by limiting pad deflection at the wafer edge. Adjust multi-zone carrier edge zone pressure upward to compensate for higher local removal rate. Implement edge exclusion rules in device placement to keep critical features away from the roll-off zone. For industrial polishing: reduce polishing dwell time at part edges; consider fixturing that extends the backing plate beyond the workpiece edge.

9. Residual Metal and Incomplete Clearing (CMP)

🔗
Residual Metal / Incomplete Clearing
Applicable to: Cu damascene CMP, W plug CMP, barrier CMP
Root Causes

Insufficient polish time; endpoint detection triggering too early (false endpoint on endpoint signal noise); wafer-center removal rate lower than wafer-edge rate (center-slow WIWNU profile) leaving residual metal at the wafer center; incoming film topography higher than the CMP process window (excessive incoming step height).

Detection

Sheet resistance mapping (4-point probe): residual conducting metal shows low sheet resistance in cleared regions. Optical inspection: metallic residue has characteristic bright appearance. KLA inspection: metal “bridges” between features detected as shorts in electrical test.

Corrective Actions

Extend polish time or increase over-polish percentage. Recalibrate endpoint detection algorithm to avoid false triggers. Profile carrier zone pressures to correct center-slow WIWNU — typically increase center zone pressure. Verify incoming film thickness and topography before CMP; if incoming step height exceeds the planarization length of the pad/slurry system, a pre-planarization step (spin-on glass or additional CVD) may be required.

10. Quick-Reference Troubleshooting Table

DefectTop Root CauseFirst Corrective ActionRelevant Process
Macro-scratchLPC in slurry / pad debrisPoint-of-use 0.2 µm filtration; bare wafer qualification runCMP
Micro-scratchSlurry agglomeration / glazed padCheck slurry shelf life; increase conditioner aggressivenessCMP
Residual coarse scratchesGrit step skippedReturn to previous grit; verify scratch removal under raking lightIndustrial polish
DishingOver-polish time; high Cu removal rateImprove endpoint detection; reduce step-2 down-forceCu/W CMP
ErosiónPattern density variationHarder pad; dummy fill; slurry selectivity optimizationCu/STI CMP
DelaminaciónExcessive shear on low-k filmReduce pressure; use compliant pad; check cap layer adhesionLow-k CMP
Orange peelCoarse grain structureAnneal; step back to coarser gritIndustrial SS/steel
Embedded abrasiveHard abrasive in soft metalFollow with electropolishing; switch to colloidal slurryIndustrial / CMP
Edge roll-offPad compliance at wafer edgeIncrease retaining ring force; adjust edge zone pressureCMP
Residual metalShort polish time / false endpointExtend over-polish; recalibrate endpoint algorithmCu/W CMP
Heat tint (SS)Excessive friction heatAdd coolant; replace worn belts; reduce contact pressureIndustrial SS
Proactive Defect Prevention: Consumable Monitoring Program

The most cost-effective defect reduction strategy in CMP is a proactive consumable monitoring program — tracking slurry LPC, D99 particle size, pH, and oxidizer concentration on every incoming lot before fab release, combined with pad-life endpoint tracking via in-situ friction monitoring. JEEZ provides full lot characterization data with every shipment, enabling customers to implement incoming inspection protocols without requiring in-house particle analysis infrastructure. Learn more about what to require from a CMP consumable supplier.


11. Preguntas más frecuentes

How do I distinguish a slurry-induced scratch from a pad-induced scratch in CMP?

Slurry-induced scratches (from LPC) typically appear as randomly distributed, isolated long scratches across the wafer surface, often with a “comet tail” morphology when examined under SEM. Pad-induced scratches (from pad debris or conditioner shedding) tend to appear in arcing or radial patterns that follow the pad rotation direction, and may cluster at specific wafer radii corresponding to tool kinematics. Running a bare silicon wafer through the same process conditions without slurry — replacing with DI water — and comparing scratch patterns can help isolate whether the tool hardware is generating the defects independently of slurry quality.

What is an acceptable dishing specification for Cu interconnect at advanced nodes?

Dishing specifications depend on the metal line width and device technology node. For advanced-node Cu interconnect (metal 1 and metal 2 at 3 nm class nodes), dishing at a 50 µm wide Cu feature is typically specified at ≤ 15–25 nm. For wider features used in power distribution (up to 100 µm), dishing ≤ 30–40 nm is typical. These specifications are driven by downstream lithography focus budget constraints and resistance uniformity requirements. As nodes scale, the acceptable dishing budget shrinks because the absolute metal height variation must remain below a smaller fraction of the total film thickness.

Can an orange peel surface on stainless steel be corrected by additional polishing?

In most cases, no — not by fine polishing alone. Orange peel is a manifestation of the underlying grain structure, which polishing cannot change. Attempting to eliminate orange peel by continuing to polish with finer grit typically results in a shinier but still dimpled surface where the grain-scale topography remains visible. The correct remedy is to step back to a coarser grit that cuts at a scale comparable to the grain size, re-establishing a uniform scratch texture, and then re-progressing through the grit sequence. For severe cases where grain size is fundamentally incompatible with the required finish, annealing the workpiece before re-polishing is necessary.


Related Technical Articles

Published by the applications engineering team at Jizhi Electronic Technology Co., Ltd. (JEEZ) — manufacturer of CMP slurries, polishing pads, absorption films, and dicing blades for the semiconductor industry. Last reviewed: May 2026.

Reduce CMP Defects with JEEZ Precision Consumables

JEEZ CMP slurries, polishing pads, and backing films are supplied with full lot characterization data — enabling incoming inspection protocols that prevent defect excursions before they reach production wafers.

Comparte este artículo

Consulta y presupuesto

Suscríbase a nuestro boletín de noticias