How to Achieve Sub-nm Surface Roughness in Silicon Wafer CMP

The Atomic-Scale Challenge in Silicon Wafer Polishing

Achieving a root-mean-square surface roughness (Rq) below 0.1 nm on a polished silicon wafer front surface is one of the most demanding specifications in all of industrial surface engineering. At this scale, the allowable roughness envelope corresponds to the displacement of fewer than one silicon atomic layer — the (001) Si lattice spacing is 0.136 nm, and a surface with Rq = 0.1 nm is varying by less than one atomic step on average across its measured area. Reaching this level consistently across an entire 300mm wafer in production, lot after lot, requires simultaneous optimization of at least five interdependent process variables.

This guide from Jizhi Electronic Technology Co., Ltd. (JEEZ) explains why sub-nanometer roughness matters, defines the metrics used to characterize it, identifies the five process levers that control it, and provides guidance on measurement and common process pitfalls. It is part of the JEEZ Silicon Wafer Polishing knowledge base.

Why Sub-Nanometer Surface Roughness Matters for Device Manufacturing

Surface roughness on a silicon wafer is not merely an aesthetic quality metric — it has direct, measurable consequences for device electrical performance and yield at multiple process steps:

• Gate dielectric integrity: When a gate oxide (SiO₂ or high-k HfO₂) is grown on a rough silicon surface, the oxide thickness varies locally in proportion to the underlying surface topography. At sub-5 nm oxide equivalent thickness (EOT), even 0.2 nm of surface roughness represents a 4% local oxide thickness variation — enough to shift the local breakdown voltage and generate measurable gate leakage current. The ITRS roadmap has consistently tightened gate oxide specifications as EOT scales downward.
• Epitaxial layer defects: For epi-silicon substrates — wafers that receive a device-quality epitaxial silicon layer before shipment — the epitaxial layer inherits the roughness of the substrate surface on which it grows. Rough substrate surfaces nucleate misfit dislocations, stacking faults, and local thickness variations in the epi layer. An epi-ready substrate requires Ra below 0.1 nm to support dislocation-free epitaxial growth at industrial rates.
• Photolithography and CMP overlay: Roughness at spatial wavelengths in the 1–10 μm range (contributing to haze) scatters alignment laser light and reduces signal-to-noise ratio in overlay metrology. This effect becomes significant when haze exceeds ~0.05 ppm on deep-UV lithography tools.
• Surface inspection noise floor: Haze — the diffuse scattered light from micro-roughness — raises the background signal on laser-scanning surface inspection tools. When haze exceeds ~0.03 ppm, it begins to mask real LPD events below the detection threshold, effectively blinding the inspection to small particles and pits that could cause device failures.

Surface Roughness Metrics: Ra, Rq, Rz, and Power Spectral Density

Four metrics are most relevant to silicon wafer CMP quality control:

For silicon wafer prime-grade production, Ra and Rq are the primary roughness specifications, measured by AFM. Haze is the primary in-line production control parameter because it can be measured on every wafer during surface inspection without a separate AFM tool. The relationship between haze (ppm) and Rq (nm) is not fixed — it depends on the spatial frequency composition of the roughness — but haze <0.03 ppm typically corresponds to Rq <0.10 nm for standard silicon finish-polish conditions. For a broader treatment of all wafer flatness and roughness metrics, see: Why Silicon Wafer Flatness Matters: TTV, SFQR, and Nanotopography Explained.

The Five Process Levers for Sub-Nanometer Roughness

Achieving Rq below 0.10 nm consistently requires simultaneous optimization of five interdependent process variables. Improving one in isolation, without adjusting the others, rarely delivers the target roughness.

Lever 1: Abrasive Concentration — Less Is More

Counterintuitively, reducing the abrasive concentration in the finish polish slurry improves surface roughness. At concentrations above ~2 wt%, the mechanical component of material removal (abrasive particles physically contacting and abrading the surface) is significant enough to leave a measurable micro-roughness imprint. As abrasive concentration is reduced below 1 wt%, the chemical component (alkaline dissolution of the SiO₂·nH₂O surface layer) increasingly dominates, and chemical dissolution is a far smoother, more isotropic material removal mechanism than mechanical abrasion. The limiting case — abrasive-free alkaline polishing — delivers the absolute smoothest surfaces achievable in CMP.

Lever 2: Particle Size — Smaller Is Smoother

Particle size affects roughness through two mechanisms. First, larger particles create larger asperity contacts and leave proportionally larger material removal events per particle-surface interaction. Second, larger particles are more likely to mechanically override the soft SiO₂·nH₂O surface layer and contact the hard crystalline silicon beneath, which increases micro-roughness. Final polish slurries with D50 of 20–30 nm consistently deliver lower Ra than slurries with D50 of 60–80 nm at the same abrasive concentration and process conditions. JEEZ FP-series finish slurries use 25–35 nm D50 colloidal silica specifically optimized for Ra performance.

Lever 3: Soft Polishing Pad — Conformality Over Flatness

Pad hardness governs how the load is distributed at the micro-scale. A hard pad (Shore D 65, IC1000-type) distributes load through discrete high asperities that contact the wafer at localized high-pressure points — creating high local material removal rates at those contact zones that produce micro-roughness. A soft pad (Shore A 50–60, Suba-type) conforms to the wafer surface at the micro-scale, distributing load over a much larger number of lower-pressure contacts and enabling the chemical component to dominate. The trade-off is that soft pads sacrifice the planarizing behavior that is needed for TTV and SFQR control — which is why the finish-polish step uses a soft pad only after DSP has already achieved global flatness with a hard pad.

Lever 4: Low Applied Pressure — Chemistry Takes Over

Applied pressure (the downforce of the carrier head membrane on the wafer against the pad) controls the balance between mechanical and chemical material removal. At high pressure (>3 psi), the Preston equation is dominated by the pressure×velocity product, and mechanical abrasion is the primary removal mechanism — which is fast but rough. Reducing pressure to below 1 psi (6.9 kPa) in the finish-polish step slows removal rate substantially but shifts the removal mechanism balance strongly toward chemistry. The rate-limiting step becomes the formation and chemical dissolution of the SiO₂·nH₂O layer — a mechanism that produces atomically smooth removal across the entire surface rather than localized mechanical events.

Lever 5: pH Optimization — Narrow Window, High Impact

The finish-polish slurry pH must be maintained within a narrow optimal window, typically pH 10.0–10.5 for (100) silicon. At pH below 9.5, the chemical dissolution rate of silicon is too slow to achieve adequate removal rate even at extended polish times. At pH above 11.0, the hydroxyl ion concentration is high enough to drive anisotropic chemical etching of the silicon crystal — which etches different crystallographic facets at different rates, creating step-edge roughness and COP pit enlargement that increases Ra. The narrow optimum window also means that pH drift during polishing (from dissolved silicon loading the slurry, from ambient CO₂ absorption, or from temperature effects) must be controlled through slurry freshness management and pH monitoring at the tool inlet.

Designing a Finish Polish Recipe for Sub-0.1 nm Ra

The following parameter set illustrates a representative finish-polish recipe targeting Ra <0.08 nm on (100) silicon, 300mm, using JEEZ FP-series slurry:

Common Mistakes That Prevent Sub-nm Results

• Over-polishing: The single most common mistake. Once the mechanical damage from the DSP step is fully removed, continuing to polish enters a regime where isotropic alkaline etching roughens different crystallographic facets at different rates — increasing Ra. The Ra vs. polish time curve is U-shaped; most process engineers optimize the left half but then operate on the right by continuing too long.
• Insufficient inter-step quench rinse: Residual rough-polish slurry particles (D50 80–150 nm) carried forward into the finish-polish step immediately dominate the surface finish. Even a few dozen killer particles from the rough-polish step reaching the finish pad can drive Ra from <0.1 nm to >0.3 nm. The inter-step quench rinse must flush both the wafer surface and the delivery lines.
• New pad without proper break-in: A freshly installed soft pad has an unstable surface texture with micro-debris and sharp asperities from the manufacturing process. The first 20–50 qualification wafers after pad installation gradually smooth the pad surface and stabilize removal rate. Running production wafers on a new pad before break-in completion produces inconsistent Ra results.
• pH drift during polishing: As silicon is removed and dissolved into the slurry, the silicic acid load increases, buffering the pH downward. In a long polish cycle or a high-removal-rate process, slurry pH at the pad can drop by 0.3–0.5 units below the fresh slurry value. Monitor pH at the tool inlet, not just in the supply tank.

For the complete defect context surrounding surface roughness issues, see: Silicon Wafer Surface Defects in CMP: Causes, Detection & Prevention. For slurry selection guidance, see: CMP Slurry for Silicon Wafer: Types, Selection & Best Practices.

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