Dishing and Erosion in Copper CMP: Causes, Pattern Density Effects & Mitigation

1. Why Dishing and Erosion Are Critical Yield Drivers

Copper interconnect resistance is proportional to the reciprocal of the cross-sectional area of the metal line. Even modest dishing or erosion can drive significant resistance increase:

• A copper line 100 nm wide × 100 nm tall that dishes by 10 nm loses 10% of its cross-sectional area and experiences approximately 10% higher resistance — potentially shifting a critical timing path outside specification.
• At 7 nm node interconnect dimensions (copper line width ≈ 15–20 nm, height ≈ 25–30 nm), even 2–3 nm of dishing represents 10–15% cross-sectional loss — pushing well beyond parametric budget.

Beyond resistance increase, dishing and erosion generate planarity nonuniformity that compounds upward through the metal stack. The next dielectric deposition fills into the topographic variation created by dishing and erosion at layer N, creating local thickness variations that affect via depth at layer N+1, which in turn creates etch nonuniformity at layer N+2. By the time the process reaches upper metal layers, topographic errors from lower levels have been amplified through multiple deposition and etch steps.

2. Copper Dishing: Mechanism, Measurement & Feature-Width Dependence

Dishing Mechanism

Copper dishing arises from two concurrent mechanisms acting on the copper in completed trench features during CMP:

Mechanical mechanism: The polishing pad is an elastic solid that deflects under the applied downforce. When the pad crosses a wide copper trench, it partially deflects into the trench opening under the locally unsupported span, bringing abrasive particles into contact with the copper below the level of the surrounding dielectric. The deflection magnitude — and therefore the dishing contribution — scales with feature width, pad compliance (softer pads dish more), and applied pressure.

Chemical mechanism: Even without pad contact, the slurry’s oxidizer and complexing agent continuously dissolve copper through the static etch rate (SER) mechanism. In the recessed trench feature, where no pad contact occurs, this isotropic chemical dissolution removes copper uniformly from all surfaces — floor and sidewalls — at the SER. Over the duration of the polishing process, this chemical contribution can add 1–5 nm to the total dishing depending on SER and process time.

Feature-Width Dependence

The mechanical contribution to dishing scales strongly with feature width because pad deflection into the trench scales with the unsupported span width. This creates the characteristic feature-width dependence of copper dishing:

Dishing Measurement

Dishing is measured by profilometry (contact or optical) on dedicated test structures — typically isolated lines of varying width in a low-density field. The measurement is the height difference between the copper line top and the adjacent ILD surface after CMP, with a positive value indicating copper is recessed below the ILD. High-resolution optical profilometry tools (e.g., Zygo, Bruker) can resolve dishing values down to 0.5 nm, and scatterometry-based techniques are increasingly used for sub-nm measurement on advanced-node test structures.

3. Dielectric Erosion: Pattern Density Effects & Measurement

Erosion Mechanism

Erosion is the thinning of the ILD material in dense metal array regions relative to isolated or low-density areas after CMP. It occurs because the polishing pad cannot distinguish between the copper lines and the narrow inter-line ILD spaces in a dense array: it contacts and removes both simultaneously during Step 2 barrier clearing. The selectivity of the Step 2 slurry (Cu:ILD selectivity) determines how much ILD is removed per unit of barrier clearing time — but even high-selectivity slurries remove some ILD in the Step 2 process, and that removal is concentrated in dense array regions where the pad contacts ILD most frequently.

Pattern Density Dependence

Erosion magnitude is strongly correlated with copper fill density (the fraction of a region’s area occupied by copper). Regions with 70–80% copper fill density show the most severe erosion because: (1) high density means the pad encounters ILD surfaces frequently per unit scan distance; (2) high density means the effective removal rate in the region is elevated due to the “loading effect,” driving more material removal per unit time than the nominal rate in open areas; and (3) dense regions tend to have the thinnest ILD inter-line spaces, which are abraded more easily by the slurry particles than wide ILD fields.

Erosion measurement requires measurements in both dense array regions and isolated ILD fields after CMP. The erosion value is the ILD thickness difference between these two regions: Erosion = ILD_isolated – ILD_dense. Production targets for erosion are typically 10–20 nm at 45 nm and older nodes, tightening to 3–5 nm at 7 nm and below.

4. The Dishing–Erosion Tradeoff

Dishing and erosion are not independent defects — they are linked through several common causal factors that create fundamental tradeoffs in the optimization of copper CMP slurry and process conditions.

The central tradeoff is between Cu:ILD selectivity in Step 2 and the ability to clear the barrier metal:

• High Cu:ILD selectivity (e.g., >100:1): Effectively stops ILD erosion once copper and barrier are cleared, but may leave residual barrier metal in low-density regions where insufficient mechanical force is applied to remove the hard Ta or TaN. Residual barrier creates local resistivity increase and potential reliability failures.
• Low Cu:ILD selectivity (e.g., 10:1): Ensures complete barrier metal clearing across all pattern density regions but removes significant ILD material in dense arrays, increasing erosion substantially.

A second tradeoff exists between BTA loading (which reduces dishing) and removal rate (which BTA also suppresses). Higher BTA loading reduces both dishing and removal rate simultaneously — so reducing dishing through BTA optimization always costs throughput. The process window for acceptable dishing with acceptable throughput is narrower at advanced nodes than at conventional nodes due to tighter dishing tolerances.

5. Slurry-Side Mitigation Strategies

BTA Concentration Optimization

Increasing BTA concentration suppresses the chemical (SER-driven) contribution to dishing by strengthening the Cu-BTA passivation film on recessed copper surfaces. For every 2× increase in BTA concentration within the effective range (0.001–0.1 wt%), SER typically decreases by 30–50%. The tradeoff is a proportional decrease in dynamic removal rate, requiring a compensating increase in H₂O₂ or mechanical parameters to maintain throughput. The optimal BTA concentration is process-specific and must be experimentally determined for each formulation and node target.

Step 2 Slurry Selectivity Engineering

Controlling erosion requires engineering the Cu:ILD selectivity of the Step 2 slurry. The primary formulation levers are:

• Abrasive type and hardness: Colloidal silica (lower hardness) preferentially removes the softer copper oxide and barrier metal while being gentler on the harder ILD. Switching from alumina to colloidal silica in Step 2 typically increases Cu:ILD selectivity by 2–5×.
• pH adjustment: Near-neutral to mildly alkaline pH (7–8) in Step 2 reduces the ILD removal rate (oxide is more stable at higher pH) while maintaining adequate copper and barrier removal rates.
• Selective surface inhibitors: Some advanced Step 2 formulations include ILD-selective surfactants that adsorb preferentially onto oxide surfaces, providing a degree of ILD passivation analogous to BTA’s role on copper — further increasing effective Cu:ILD selectivity.

Abrasive Particle Size and Distribution

Smaller abrasive particles (D50 below 80 nm) generally produce less mechanical dishing than larger particles (D50 above 150 nm) because smaller particles make contact with smaller areas of the copper trench floor during each asperity-contact event. The tradeoff is lower removal rate per unit particle contact, which must be compensated by higher particle loading or enhanced chemical activity. JEEZ’s CuS barrier slurry series uses sub-80 nm colloidal silica for this reason, achieving single-digit nanometer dishing on 100 nm features at standard Step 2 conditions.

6. Process-Side Mitigation Strategies

Endpoint Detection and Over-Polish Control

Over-polish time — the time polished beyond the theoretical endpoint — is the single most controllable contributor to both dishing and erosion. Every 10 seconds of over-polish at a Step 2 removal rate of 100 nm/min adds ~17 nm of additional exposure to the copper and ILD surfaces. Tight endpoint control using in-situ detection (motor current, optical reflectance, or eddy-current) combined with APC-driven run-to-run endpoint correction is the most effective process-side mitigation for both dishing and erosion.

Practical targets for over-polish time in advanced-node Step 2 copper CMP are <15 seconds — requiring endpoint detection accuracy better than ±5 seconds, which in turn requires clean endpoint signal discrimination (high signal-to-noise ratio) from the in-situ sensor system.

Polishing Pressure Optimization

Lower Step 2 polishing pressure reduces mechanical dishing by decreasing pad deflection into trench features. However, lower pressure also reduces the mechanical driving force for barrier metal removal, potentially leading to residual barrier on low-density regions. The optimal Step 2 pressure minimizes mechanical dishing while maintaining complete barrier clearing across all pattern density regions — typically 1.5–2.5 psi for conventional nodes, 0.7–1.2 psi for ELK-containing advanced nodes.

Pad Hardness Selection

Harder polishing pads deflect less into copper trenches, producing less mechanical dishing. The tradeoff with harder pads is higher defect density (more aggressive asperity contact) and less conformable surface contact on wafers with initial topographic variation. In practice, a two-layer pad stack — a hard backing layer (e.g., IC1000) under a softer polishing surface layer (e.g., SUBA) — offers a compromise that delivers hard-pad dishing performance with soft-pad defect levels.

7. Design-Side Mitigation: CMP-Aware Design

The most powerful long-term mitigation for dishing and erosion is design-level copper density control — ensuring that the circuit layout presents a sufficiently uniform copper density to the CMP process that pattern-density-dependent dishing and erosion effects are minimized before polishing begins.

Copper Fill Metal Insertion

Fill metal (also called “dummy metal” or “floating fill”) consists of electrically disconnected copper structures inserted into low-density regions of the layout to bring local copper density within a specified range (typically 30–70%) across all regions of the chip. Fill metal insertion is governed by design rules that specify minimum and maximum local density targets, fill shape constraints (to minimize capacitance coupling), and exclusion zones around critical timing paths.

Modern EDA tools (from Synopsys, Cadence, and others) include CMP-aware fill insertion algorithms that optimize fill density distributions to minimize predicted dishing and erosion based on calibrated CMP simulation models. JEEZ’s application engineering team can assist customers in calibrating CMP simulation models to specific slurry formulations and process conditions for accurate fill insertion optimization.

CMP Simulation in Sign-Off

CMP simulation tools (e.g., Mentor CMP Predictor, Cadence Voltus CMP) use physics-based or data-driven models to predict dishing and erosion at every location on the chip layout based on local copper density and feature geometry. These predictions are used to: identify hotspots that exceed dishing/erosion tolerance before tape-out, guide fill insertion optimization, and define which circuit paths need resistance margin adjustment in timing sign-off to account for CMP-induced resistance increase.

As of July 2026, CMP simulation accuracy at 7 nm and below has improved to ±2 nm dishing prediction error on calibrated test structures, making simulation-driven design sign-off a viable replacement for iterative physical silicon test iterations in most cases.

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8. Frequently Asked Questions