Semiconductor CMP Polishing Pads: Applications Across the Full IC Process Flow
A complete step-by-step guide to how CMP polishing pads are deployed across the full semiconductor IC manufacturing process — from shallow trench isolation to advanced BEOL copper interconnects, 3D NAND, and emerging heterogeneous integration applications.
Flow
Modern semiconductor manufacturing is fundamentally multi-material and three-dimensional. A leading-edge logic chip fabricated at 3–5 nm contains transistors made from silicon, silicon germanium, hafnium oxide, titanium nitride, and tungsten — all in the same active device layer. Above those transistors are 12–18 metal interconnect levels built from copper embedded in low-k dielectric, connected by tungsten vias, and isolated by silicon nitride etch stop layers. Each of these material boundaries represents a CMP step.
The result is that a modern 300 mm wafer running through a leading-edge logic process flow will undergo more than 30 individual CMP operations before it is ready for packaging. Each step uses a different pad specification, different slurry chemistry, and different process recipe — optimized for the specific material being planarized and the step-height challenge it presents.
For an introduction to what CMP pads are and how they work, see: What Is a CMP Polishing Pad? The Ultimate Guide.
1. Why Modern ICs Need 30+ CMP Steps
The need for so many CMP steps in modern IC manufacturing arises from three simultaneous trends: device scaling, architectural complexity, and material diversification. As transistor gates have shrunk below 10 nm, the tolerance for any surface non-planarity between process steps has become vanishingly small — the depth of focus of EUV lithography (used for the most critical pattern levels) is measured in tens of nanometers. Any surface deviation larger than this causes patterning errors. CMP is the only process that reliably delivers the global planarization required at each critical level.
The multi-level copper interconnect stack is equally demanding. Each copper level requires: (1) a CMP step to planarize the ILD dielectric before copper trench etching; (2) a CMP step to remove excess copper after electroplating; and (3) often a CMP step to clear the barrier metal and finalize the surface for the next level’s dielectric deposition. Multiply this three-step sequence across 12–18 metal levels and the copper CMP alone accounts for 36–54 individual polish operations.
2. Front-End-of-Line (FEOL) CMP Steps
| FEOL CMP Step | Target Film | Key Challenge | Recommended Pad Type |
|---|---|---|---|
| Shallow Trench Isolation (STI) | TEOS or HDP oxide over Si₃N₄ stop layer | High incoming step height (200–500 nm); must stop on nitride with high selectivity; no dishing of active areas | Hard PU (Shore D 60–65) + high-selectivity ceria slurry; IC1000-equivalent or JZ-H65 |
| Pre-Metal Dielectric (PMD) planarization | BPSG or undoped silicate glass over gate structures | Very high incoming topography from gate stacks; must achieve >80% step-height reduction in single pass | Hard PU (Shore D 62–66) + silica slurry; aggressive planarization recipe |
| Gate dielectric polish | High-k dielectric (HfO₂) over poly or metal gate | Very thin target film (<3 nm); extremely low removal rate needed; ultra-low scratch tolerance | Very soft PU (Shore D 28–35) + colloidal silica; ultra-low pressure |
| Dummy gate removal (gate-last FinFET) | Polysilicon dummy gate and sacrificial dielectric | High topography; must expose gate top without damaging gate dielectric; tight WIWNU | Medium-hard PU (Shore D 50–58) with stacked configuration |
| Contact hole pre-fill planarization | ILD oxide before contact etch | Must achieve flat surface for lithography of deep sub-20 nm contacts | Hard PU (Shore D 58–62) + standard ceria; standard oxide CMP recipe |
3. Back-End-of-Line (BEOL) CMP: Copper Interconnect
The BEOL copper interconnect stack is the most CMP-intensive part of any IC process flow, and the most demanding in terms of pad selection — because the target films (Cu, Ta, TaN, low-k SiCOH) are soft, fragile, and prone to scratch and corrosion defects that directly affect electrical performance. For a detailed discussion of the hard vs. soft pad choice in BEOL, see: Hard vs. Soft CMP Polishing Pads: Selection Guide.
| BEOL CMP Step | Target Film | Critical Requirement | Pad Type |
|---|---|---|---|
| ILD oxide planarization (pre-trench) | SiCOH low-k dielectric (k 2.4–3.0) | Flat surface for trench litho; must not crack or delaminate low-k | Medium-soft PU (Shore D 42–52) + stacked subpad; reduced pressure |
| Cu bulk overburden removal (Step 1) | Electroplated copper (2–5 µm overburden) | Fast removal of excess Cu; protect low-k beneath barrier; minimize dishing | Medium-soft PU (Shore D 38–48) + BTA-based Cu slurry; moderate pressure |
| Cu / barrier clearing and buff (Step 2) | Residual Cu + TaN/Ta barrier; low-k surface | Clear barrier with minimal dishing and erosion; Ra < 0.5 nm; scratch density <5/wafer | Very soft PU (Shore D 28–36) + colloidal silica barrier slurry; ultra-low pressure (<1.5 psi) |
| Via fill planarization (W) | CVD tungsten over TiN barrier | Clear W to ILD; high W-to-TiN selectivity; no W plug recess (dishing) | Hard PU (Shore D 58–64) + H₂O₂/ferric catalyst slurry; standard IC1000-equivalent |
| Inter-metal dielectric (IMD) planarization | Low-k SiCOH or extreme low-k (k < 2.5) | Fragile porous dielectric — shear force must be below delamination threshold | Ultra-soft PU (Shore D 24–32) + very low pressure (<1 psi); stacked configuration mandatory |
4. CMP in 3D NAND and DRAM Manufacturing
Memory chip manufacturing presents distinct CMP challenges compared to logic. In 3D NAND flash — where 100–256 alternating oxide/nitride (or oxide/polysilicon) layer pairs are deposited and etched in a high-aspect-ratio stack — the CMP requirements are driven by planarization uniformity rather than selectivity. Any within-wafer thickness variation in the planarized stack directly propagates as variation in cell threshold voltage, affecting device reliability and data retention.
- 3D NAND oxide-nitride stack planarization: Hard pads (Shore D 60–65) with ceria slurry; extremely tight WIWNU target (<0.5% 1σ) achieved by precise groove design and in-situ endpoint control
- 3D NAND channel hole fill (polysilicon): Medium-hard pad with silica slurry; must remove excess polysilicon uniformly from a surface with hundreds of etched holes per µm²
- DRAM capacitor node planarization: Hard pad with high-selectivity slurry; extremely deep-aspect-ratio structures require excellent step-height reduction
- DRAM peripheral circuit planarization: Standard oxide CMP — similar to FEOL logic; IC1000-equivalent hard pads with ceria slurry
5. Advanced Packaging CMP
The transition to advanced packaging architectures — chiplet-based heterogeneous integration, 2.5D interposers, 3D-IC stacking with through-silicon vias (TSVs) — has created an entirely new set of CMP applications that sit at the boundary between wafer fabrication and packaging. These applications are growing rapidly as of April 2026, driven by the AI chip market’s demand for high-bandwidth memory (HBM) stacking and die-to-die interconnect.
TSV (Through-Silicon Via) CMP
After TSV copper filling, CMP removes the copper overburden and reveals the TSV tops. Requires excellent local planarity around each TSV to enable die-to-die bonding. Soft pad + fine-pitch groove pattern for best uniformity around high-aspect-ratio TSV structures.
Redistribution Layer (RDL) CMP
Cu RDL lines on organic or glass substrates require CMP to achieve flat surfaces for multi-layer fan-out wafer-level packaging. Lower substrate stiffness compared to silicon wafers demands very soft, highly compliant pads that adapt to substrate bow without edge-center loading issues.
Hybrid Bonding Surface Preparation
Direct copper-to-copper hybrid bonding (used in HBM4 and advanced 3D-IC) requires atomically smooth Cu bond pads — Ra < 0.5 nm and step height below 2 nm relative to the surrounding dielectric. The most demanding surface quality specification in semiconductor CMP. Requires poreless pads with fine abrasive slurry at ultra-low pressure.
Interposer Planarization
Silicon interposers for 2.5D integration require multiple CMP steps for their embedded wiring layers — similar to standard IC BEOL CMP but often on thinner substrates that are more prone to warpage. Stacked pad configuration with a compliant subpad is essential for interposer CMP.
6. CMP Pad Selection Map: Full Process Flow Summary
| Process Step Category | Hardness Range | Jizhi Product | Key Slurry |
|---|---|---|---|
| STI, PMD oxide CMP | Shore D 60–66 (hard) | JZ-H65 | High-selectivity ceria, pH 7–9 |
| Standard oxide ILD (mature node) | Shore D 58–62 (hard) | JZ-H60 | Ceria or silica, pH 10–11 |
| Tungsten plug/via CMP | Shore D 60–65 (hard) | JZ-H60 / JZ-H65 | H₂O₂ + Fe catalyst, pH 2–4 |
| Cu bulk overburden (BEOL Step 1) | Shore D 38–48 (medium-soft) | JZ-S38 | BTA + H₂O₂, pH 4–7 |
| Cu / barrier buff (BEOL Step 2) | Shore D 26–36 (very soft) | JZ-S28 | Colloidal silica, pH 7–9 |
| Low-k, ultra-thin films | Shore D 24–32 (ultra-soft) | JZ-S28 (low pressure) | Ultra-fine silica, pH 7 |
| SiC substrate (Stage 2) | Shore D 63–68 (specialty) | JZ-SiC-I | Diamond 0.1–0.5 µm + H₂O₂ |
| SiC substrate (Stage 3 final) | Shore D 53–60 (specialty) | JZ-SiC-II | Ceria + KMnO₄ 0.5–1.5% |
| TSV / RDL / hybrid bonding | Shore D 28–42 (soft) | JZ-S38 / Custom | Ultra-fine Cu slurry, pH 4–7 |
