How Polishing Template Edge Design Controls Wafer Edge Profile & Reduces Edge Exclusion

Publié le : 2026年3月13日Vues : 772
Edge Engineering Guide

Every millimeter of edge exclusion zone you eliminate converts directly into additional die area. This guide explains the physics of edge rolloff and the template design parameters that control it — including how sub-2 mm edge exclusion is achieved at scale.

Par Jizhi Electronic Technology Co. · Spécialistes du polissage des semi-conducteurs · 13 minutes de lecture

Why Edge Exclusion Is a Yield Problem Worth Engineering For

Edge exclusion is defined by SEMI Standard M49 as the annular zone at the wafer perimeter within which die sites are not counted for yield because the surface flatness or layer thickness at those locations falls outside specification. At 300 mm with a 3 mm edge exclusion zone, approximately 3.8% of the wafer area is excluded — an area that could yield additional die on every wafer processed. At 150 mm with a 5 mm edge exclusion zone, over 12% of wafer area is excluded.

For advanced logic and memory devices where die size is small and die-per-wafer counts are high, reducing edge exclusion from 3 mm to 1.5 mm on a 300 mm wafer recovers approximately 1.9% of wafer area — which at a die yield of 90% and a selling price of $100 per die translates directly to additional revenue on every wafer shipped. Across a production line running 10,000 wafers per month, even a 1% recovery in die-per-wafer count represents significant annual revenue impact.

The edge exclusion zone is set by the polishing process, not the wafer specification: it is the zone where edge rolloff makes the polished surface too non-flat to meet the flatness specification required for successful photolithography. Reducing edge exclusion therefore requires reducing edge rolloff — and edge rolloff is controlled, to a significant degree, by the polishing template edge design. Understanding the full mechanics of fonctionnement des gabarits de polissage establishes the foundation for understanding why edge geometry matters.


The Physics of Edge Rolloff

Edge rolloff is a mechanical consequence of the polishing pad’s elastic behavior at the wafer perimeter. During polishing, the wafer sits face-down on the rotating polishing pad, with the wafer backside held against the template’s backing pad. The polishing pad contacts the wafer front face across the full wafer area and then must transition — at the wafer edge — to a zone where there is no longer a solid substrate beneath it.

At this transition point, the polishing pad deflects downward under its own elastic bending stiffness and the difference in support between the wafer area (rigid, backed by the wafer itself and the template) and the annular gap zone (compliant, backed only by the polishing pad’s bending resistance). This downward deflection of the pad at the wafer perimeter reduces the local contact pressure between the pad and the wafer surface in a zone that extends inward from the wafer edge by a characteristic rolloff length — typically 2–5 mm for standard polishing conditions.

The consequence of reduced local pressure is reduced local material removal rate at the wafer edge, following Preston’s law. The center of the wafer receives nominal pressure and is polished to the target thickness. The edge zone receives below-nominal pressure and is polished more slowly — leaving the edge thicker than the center. This is the edge rolloff profile: a zone of increasing thickness as you approach the wafer perimeter, visible as a rising edge on the wafer cross-section thickness map.

✗ Without EER — Standard Template
Tampon de polissage Wafer rolloff rolloff Carrier Plate Backing Pad ~3–5mm EE ~3–5mm EE
Pad deflects at wafer perimeter → local pressure reduction → edge rolloff zone 3–5 mm. Significant wafer area excluded from yield.
✓ With EER — Engineered Template
Tampon de polissage Wafer Carrier Plate EER EER Backing Pad ~1–2mm ~1–2mm
EER provides mechanical support to pad in the annular zone → reduced pad deflection → near-uniform pressure at wafer perimeter → EE zone shrinks to 1–2 mm.

What Standard Template Geometry Produces

A standard polishing template — carrier plate plus backing pad, without an edge enhancement ring — produces a predictable edge rolloff profile determined by the annular gap between the wafer OD and the work-hole wall, the backing pad compliance, the polishing pad stiffness, and the applied process pressure.

In this standard geometry, the annular zone between the wafer edge and the work-hole wall provides no mechanical support to the polishing pad. The polishing pad spans this gap freely, supported on one side by the wafer (rigid) and on the other side by nothing — or, if the gap is small enough, by the work-hole wall itself at a distance of 0.2–0.5 mm from the wafer edge. The characteristic distance over which the pad’s contact pressure falls from its nominal bulk value to zero at the edge is the rolloff length, and it is primarily a function of the pad’s elastic bending stiffness.

For standard IC-1000 polishing pads under typical SSP conditions (3–5 psi applied pressure), the rolloff length in a standard template geometry is approximately 3–5 mm — meaning that from 3–5 mm inside the wafer edge inward, the pad pressure profile begins declining. The actual edge exclusion zone is the subset of this rolloff length where the thickness deviation exceeds the process flatness specification. For a TTV specification of ±0.5 µm, the resulting edge exclusion is typically 2.5–4.0 mm depending on process conditions and backing pad hardness.

ℹ️
SEMI M49 Edge Exclusion Definition SEMI Standard M49 defines the edge exclusion zone as a fixed-width annular region measured from the wafer flat or notch edge inward, within which die sites are not counted for yield calculation. The M49 specification has evolved over successive SEMI updates to reflect industry push toward smaller EE zones: from a legacy 5 mm EE standard at 200 mm, to 2 mm as the current dominant 300 mm production target, to 1 mm as the leading-edge requirement at advanced nodes.

The Edge Enhancement Ring: Concept & Mechanics

The edge enhancement ring (EER) addresses the root cause of edge rolloff — the absence of mechanical support for the polishing pad in the annular zone adjacent to the wafer edge — by providing precisely controlled support in exactly that zone. It is a precision-machined annular feature added to the polishing template surface, concentrically positioned around the work hole, with its inner radius aligned to the wafer edge and its outer radius extending into the unsupported gap zone.

When the template is loaded into the carrier head and the polishing pad contacts the wafer surface, the EER’s raised surface contacts the back face of the polishing pad in the annular support zone. This contact counters the pad’s elastic tendency to deflect downward at the wafer perimeter, increasing local pad stiffness in the rolloff zone. The result is a partial recovery of contact pressure in the previously under-pressured edge zone, which equalizes the material removal rate between the edge and center and reduces the width and height of the rolloff profile.

The EER does not completely eliminate rolloff — perfect pressure uniformity at the wafer edge would require perfect support geometry that is not practically achievable. But a well-engineered EER reduces rolloff height by 60–80% and shrinks the edge exclusion zone from 3–5 mm to 1–2 mm, recovering 1–3 mm of usable die area around the entire wafer perimeter. This is a template-level engineering solution to an edge profile problem that cannot be solved by process recipe adjustments alone.


EER Anatomy: Four Design Parameters That Control Edge Profile

Edge Enhancement Ring — Design Parameter Map
Carrier Plate (FR-4 / G-10 / CXT) Backing Pad Work Hole EER EER Wafer surface A — EER Inner Diameter B — Width C - Hauteur D - Matériau
Paramètre A
EER Diamètre intérieur
= diamètre extérieur de la plaquette + 0,4-1,0 mm d'espace libre
Paramètre B
EER Largeur radiale
3-12 mm (selon le procédé)
Paramètre C
EER Hauteur
50-300 µm au-dessus de la face du gabarit
Paramètre D
EER Matériau
Identique à la plaque de support (FR-4 / G-10 / CXT)

Paramètre A : Diamètre intérieur du REE - Réglage du début de la zone de soutien

Le diamètre intérieur de l'EER définit le point de départ de la zone de support annulaire, mesuré à partir du centre du gabarit. Il correspond au diamètre extérieur de la plaquette plus un espace libre de 0,4 à 1,0 mm. Ce dégagement a deux fonctions : il empêche le REL d'entrer en contact avec le bord de la plaquette pendant le polissage (ce qui causerait des dommages mécaniques) et il permet le chargement et le déchargement de la plaquette sans que le REL n'obstrue la trajectoire de placement de la plaquette. Un espace libre inférieur à 0,4 mm risque d'entrer en contact avec le bord ; au-delà de 1,0 mm, la zone de support du dispositif d'extraction électronique ne commence plus à s'approcher suffisamment du périmètre de la plaquette pour contrer efficacement la chute à 1 ou 2 mm du bord.

Paramètre B : Largeur radiale de l'EER - Contrôle de l'étendue de la zone de soutien

La largeur de l'EER détermine à quelle distance du bord de la plaquette le tampon de polissage reçoit un soutien mécanique. Les EER plus larges (8-12 mm) fournissent un soutien sur une plus grande partie de la zone de décrochage et conviennent aux applications où le décrochage s'étend à plus de 5 mm du bord de la plaquette. Les EER plus étroits (3-6 mm) sont suffisants lorsque l'exclusion du bord cible est de 1,5-2,0 mm et que la chute est concentrée près du périmètre de la plaquette. Une largeur d'EER trop importante risque de trop soutenir le tampon de polissage et d'inverser le profil de pression - créant une condition de “bord élevé” où le bord est poli plus rapidement que le centre, produisant un nouveau type d'erreur de profil de bord.

Paramètre C : hauteur de l'EER - ampleur de la correction de la pression

La hauteur de l'EER est le plus sensible des quatre paramètres. Elle contrôle l'ampleur de la force mécanique appliquée par l'EER à la face arrière du tampon de polissage dans la zone de support, ce qui contrôle directement l'ampleur de l'augmentation de la pression sur le bord de la plaquette. Une EER trop faible fournit un soutien insuffisant et laisse une perte de charge résiduelle. Une EER trop élevée surcorrige le profil de pression, créant un TTV sur le bord qui est le problème inverse de celui de la chute initiale. La hauteur nominale de l'EER est généralement de 50 à 150 µm pour les applications SSP et de 100 à 300 µm pour les applications CMP à des pressions appliquées plus élevées, mais elle doit être validée et affinée à l'aide de données de qualification des premières particules. C'est pourquoi la géométrie de l'EER nécessite un cycle d'itération dans le processus de conception - la hauteur précise est réglée de manière empirique en fonction de la combinaison spécifique de la pression du processus, de la dureté du tampon d'appui et de la rigidité du tampon de polissage.

Paramètre D : Matériau EER

L'EER est généralement usiné dans le même matériau que le reste du gabarit (FR-4, G-10 ou CXT en fonction des exigences chimiques de la boue) en une seule étape de fabrication intégrée. Cela permet d'éliminer l'interface de collage qui existerait si l'EER était un composant séparé, empêchant ainsi le mode de défaillance de l'adhésif qui dégraderait la stabilité de la hauteur de l'EER pendant la durée de vie du gabarit. Pour plus de détails sur le choix des matériaux, voir notre site web Guide des matériaux FR-4 vs G-10.


EER Design & Qualification Process

1
Recueillir des données de base sur le profil des bords

Avant de commencer la conception de l'EER, le profil de bord actuel doit être caractérisé quantitativement. Fournissez les données de mesure du profil des bords de votre processus actuel : hauteur de chute (en µm) à 1 mm et à 2 mm du bord de la plaquette, mesurée sur au moins 5 plaquettes d'un lot de production représentatif. Fournissez également la largeur actuelle de la zone d'exclusion des bords et la spécification de planéité qui définit votre limite d'EE. Si vous spécifiez un nouveau procédé sans référence existante, la conception de l'EER partira d'une estimation nominale et nécessitera davantage de cycles d'itération.

Produit livrable : Ensemble de données sur les profils d'arêtes + spécification de l'EE cible
2
Déterminer l'exclusion des bords de la cible et dériver les paramètres de l'EER

La géométrie de l'EER est initialement calculée à partir des données de base et de la spécification de l'EE cible. Le diamètre intérieur du REE est défini à partir du diamètre extérieur de la plaquette et de l'exigence de dégagement. La largeur du REE est estimée à partir de la forme du profil de chute - en particulier, la distance radiale à laquelle la hauteur de chute dépasse pour la première fois la spécification de planéité. La hauteur de l'EER est initialement estimée à partir d'un modèle de déflexion du tampon paramétré par la dureté Shore A du tampon de support et la pression du processus.

Produit livrable : Dessin de la géométrie de la première itération de l'EER
3
Fabriquer et livrer le gabarit de qualification de la première particule

La géométrie de l'EER de la première itération est usinée dans un lot de gabarits de qualification (généralement 3 à 5 pièces). Ces gabarits sont contrôlés dimensionnellement par CMM pour vérifier la hauteur, le diamètre intérieur et la largeur de l'EER par rapport au dessin de conception avant l'expédition. Les gabarits sont expédiés avec le dessin de spécification complet et l'ensemble des données CMM pour référence pendant votre processus de qualification.

Délai : 3 à 5 semaines à compter de la confirmation du cahier des charges
4
Exécuter le lot de qualification et mesurer la réponse du profil de l'arête

Polir un lot de plaquettes de qualification en utilisant les gabarits EER de première particule à votre recette de production nominale. Mesurez le profil des bords sur au moins 3 plaquettes par modèle, en saisissant la hauteur de chute à des intervalles de 0,5 mm depuis le bord de la plaquette jusqu'à 5 mm vers l'intérieur. Comparez le profil de bord obtenu aux données de référence (avant l'EER) et à la spécification EE cible. Trois résultats sont possibles : l'EER atteint l'EE cible (passer à la qualification de la production), l'EER surcorrige (réduire la hauteur dans l'itération 2), ou l'EER sous-corrige (augmenter la hauteur ou la largeur dans l'itération 2).

Délai : Durée du cycle de qualification
5
Itérer la géométrie si nécessaire et confirmer la conception de la production

La plupart des conceptions de REE atteignent la performance cible du profil des bords en un ou deux cycles d'itération. La deuxième itération ajuste la hauteur de l'EER en fonction du facteur de correction mesuré de manière empirique et dérivé des données de réponse de la première particule. Une fois que le profil de bord répond à la spécification EE cible, la géométrie EER est verrouillée et le modèle entre dans la qualification de la production dans le cadre de votre système de contrôle des modifications.

Délai total entre le premier article et la conception verrouillée : 8 à 16 semaines en général

Impact quantifié : Zone d'exclusion des bords avant et après l'EER

Les données suivantes représentent les améliorations représentatives de l'exclusion des bords réalisables avec des gabarits EER dans les applications courantes de polissage des semi-conducteurs. Les résultats réels varient en fonction du substrat, de la plate-forme de la tête porteuse, de la spécification du support et de la pression du processus.

300 mm Si SSP - Pas d'EER (modèle standard) 3,5-5,0 mm EE
3,5-5,0 mm
300 mm Si SSP - Modèle standard EER 1,5-2,5 mm EE
1,5-2,5 mm
300 mm Si SSP - EER optimisé (nœud avancé) 1,0-1,5 mm EE
1,0-1,5 mm
Configuration Typical EE Zone EE Improvement vs. No EER Wafer Area Recovered (300 mm)
No EER — standard template 3,5-5,0 mm Baseline
Standard EER design 1,5-2,5 mm 2.0–2.5 mm reduction +2.3–2.9% usable area
Optimized EER (advanced node) 1,0-1,5 mm 2.5–4.0 mm reduction +2.9–4.6% usable area
150 mm Si — with EER 1,5-2,5 mm 2.0–3.5 mm reduction vs. 4–5 mm baseline +4.5–7.2% usable area

Yield Math: Translating Edge Exclusion Reduction to Die Revenue

The financial case for EER template investment can be calculated directly from die geometry and wafer volume. The following example uses 300 mm silicon with a representative advanced logic die size.

📊 EER Yield Impact Calculation — Illustrative Example
Wafer diameter: 300 mm
Die size: 100 mm² (10 × 10 mm)
Die price: $200 / die
Production volume: 5,000 wafers/month
Current edge exclusion: 4.0 mm → EER target: 1.5 mm
Edge area recovered: (π × 300 mm × 2.5 mm) ≈ 2,356 mm² per wafer
Additional die per wafer (at 85% yield): ≈ 2,356 / 100 × 0.85 ≈ 20 die
Additional revenue per wafer: 20 × $200 = $4,000
Monthly additional revenue: $4,000 × 5,000 = $20M / month
* Actual results depend on die geometry, layout efficiency, and edge flatness specification. Die at the exact perimeter may still be partially excluded depending on notch alignment and die grid offset.

Even at conservative recovery estimates — 5 additional die per wafer at a modest die price — the annual revenue impact of a 2.5 mm EE reduction far exceeds the cost difference between a standard template and an EER-equipped template. The EER is one of the highest-ROI tooling investments available in wafer polishing operations, and it requires no changes to the polishing machine, recipe, or slurry chemistry.


Substrate-Specific Edge Design Requirements

Silicon (Si) — 150–300 mm
Typical EE without EER3–5 mm
Target EE with EER1,0-1,5 mm
EER height range50–150 µm
EER inner clearance0.4–0.6 mm
Carrier materialFR-4 or G-10
Key challengeTight height tolerance on EER to avoid over-correction
Carbure de silicium (SiC)
Typical EE without EER4–6 mm
Target EE with EER1,5-2,5 mm
EER height range100–300 µm
EER inner clearance0.5–0.8 mm
Carrier materialCXT mandatory
Key challengeHigh process pressure requires taller EER; KMnO₄ slurry demands CXT grade
GaAs / InP
Typical EE without EER3–5 mm
Target EE with EER1,5-2,5 mm
EER height range40–100 µm
EER inner clearance0.5–0.7 mm
Carrier materialG-10 or CXT
Key challengeLow fracture toughness demands conservative EER height to avoid edge chipping
Glass / Ceramic Substrates
Typical EE without EER4–7 mm
Target EE with EER2.0–3.0 mm
EER height range80–200 µm
EER inner clearance0.6–1.0 mm
Carrier materialG-10
Key challengeNon-standard wafer thicknesses require custom work-hole depth + EER co-optimization

Interaction Effects: Backing Pad, Process Pressure & Edge Profile

The EER does not operate in isolation — its effect on edge profile interacts with two other process variables that independently influence edge rolloff: backing pad hardness and applied process pressure. Understanding these interactions prevents incorrect EER design decisions and explains why an EER geometry that works well on one machine platform may require adjustment when transferred to a different platform.

Backing Pad Hardness Interaction

A harder backing pad (higher Shore A) transmits applied pressure more rigidly and reduces the compliance that normally cushions the wafer against non-uniform pressure in the edge zone. This makes a harder pad more sensitive to the presence or absence of an EER: with no EER, a hard pad produces sharper, higher rolloff (because it transmits the full pressure drop at the wafer edge without compliance averaging); with an EER, a hard pad responds more strongly to the EER’s support force, requiring a lower EER height to achieve the same edge profile correction. For the same target edge profile, templates with harder backing pads require lower EER heights than templates with softer pads.

Process Pressure Interaction

Higher applied process pressure increases the magnitude of the polishing pad’s bending force at the wafer edge — the force that drives rolloff. This means that higher-pressure processes produce more severe rolloff and require more aggressive EER correction. An EER designed for 3 psi SSP may under-correct at 5 psi without geometry adjustment. When EER templates are transferred between process recipes at different nominal pressures, the EER height should be re-evaluated against the new pressure conditions before assuming the geometry will remain optimal.

💡
Document the Full System State When Qualifying an EER When recording the qualification data for an EER design, always document the backing pad Shore A specification, nominal process pressure, and carrier head model alongside the EER geometry. This system-state record makes it possible to correctly predict EER geometry adjustments when any of these parameters change in the future — without having to start the qualification process from scratch.

When to Specify an EER — and When Standard Template Geometry Is Sufficient

The EER is the right specification choice when the edge exclusion target cannot be achieved with standard template geometry and process optimization alone. The following decision framework provides clear guidance for the most common scenarios.

Scenario EER Recommended? Rationale
Target EE < 2.0 mm (any substrate) Yes — Required Sub-2 mm EE is not achievable with standard template geometry in typical SSP or CMP process conditions
Persistent edge rolloff > 0.5 µm at 2 mm from edge Yes — Recommended Residual rolloff at 2 mm indicates standard template geometry cannot meet advanced flatness specs in this zone
Target EE = 2.0–3.0 mm, current EE = 3.5–5.0 mm Evaluate Process optimization (backing pad, pressure) may achieve 2.5–3.0 mm; EER needed only if optimization insufficient
Target EE ≥ 3.0 mm, current EE meets spec No — Not needed Standard template geometry adequate; EER adds cost and design complexity without yield benefit
New process node with tightened EE requirement Yes — Proactive Plan EER design into new node template from the start; retrofitting EER after process qualification is costlier
Research / low-volume non-prime wafer polishing Typically no Non-prime specifications typically have EE ≥ 3 mm; EER investment not justified at low volume

For detailed guidance on specifying the full set of template parameters when including an EER, see our 6-parameter polishing template specification guide, which covers P5 (edge enhancement ring requirement) in full detail including the inputs needed to begin EER design.


Questions fréquemment posées

What causes edge rolloff in wafer polishing?
Edge rolloff occurs because the polishing pad deflects downward at the wafer perimeter where it transitions from the rigid, wafer-supported zone to the unsupported annular gap between the wafer edge and the work-hole wall. This deflection reduces local contact pressure, creating a zone of lower material removal rate that leaves the edge thicker than the wafer body. The rolloff length — typically 3–5 mm — depends on the pad’s elastic bending stiffness, the annular gap width, and the applied process pressure.
What is an edge enhancement ring in a polishing template?
An edge enhancement ring (EER) is a precision-machined annular raised feature on the polishing template, concentrically positioned around the work hole with its inner edge near the wafer perimeter. During polishing, the EER contacts the polishing pad’s back surface in the rolloff zone, providing mechanical support that counters pad deflection, increases local contact pressure at the wafer edge, and reduces the width and height of the rolloff profile. The result is a smaller edge exclusion zone — typically reduced from 3–5 mm to 1.0–2.0 mm with a well-engineered EER design.
What edge exclusion is achievable with an edge enhancement ring?
For 300 mm silicon prime wafer SSP, optimized EER designs consistently achieve edge exclusion zones of 1.0–1.5 mm, compared to the typical 3.5–5.0 mm baseline without an EER. For SiC and compound semiconductor substrates with more severe rolloff and higher process pressures, achievable EE with EER design is typically 1.5–2.5 mm. Sub-1.0 mm edge exclusion is an active area of development for the most advanced leading-edge nodes.
How is edge enhancement ring geometry determined?
EER geometry is determined through a structured engineering process: starting with the target edge exclusion, current edge profile measurement data, wafer diameter, backing pad specification, and process pressure, the initial EER inner diameter, radial width, and height are calculated analytically. First-article qualification templates are then fabricated and tested against the target, with EER height adjusted in 1–2 iteration cycles based on the measured edge profile response. Total timeline from specification to locked design is typically 8–16 weeks.
Do I need a custom template to get an edge enhancement ring?
Yes. EER geometry is specific to each combination of wafer diameter, target edge exclusion, backing pad specification, and carrier head platform — there is no catalog EER design that applies universally. However, the custom engineering process is straightforward once the six specification parameters are defined, and the EER design is integrated into the same template fabrication step as the carrier plate and work-hole machining — there is no separate EER assembly step that adds to lead time.

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