Semiconductor Planarization Techniques: CMP vs. SOG vs. Etch-Back Compared
Semiconductor planarization encompasses a range of techniques that have evolved over six decades — from thermal glass reflow and spin-on-glass to resist etch-back and, ultimately, Chemical Mechanical Planarization. This guide provides an in-depth technical comparison of all major planarization methods, explains why each delivers only local or global uniformity, and gives process engineers a clear framework for technique selection.
01Classification Framework: Local vs. Global Planarization
All semiconductor planarization techniques can be classified along two axes: the spatial scale over which they reduce topographic variation, and the physical mechanism by which they do so. The spatial scale axis is the most important for process selection: local techniques smooth features at the micrometer scale but leave large-scale wafer variation intact; global techniques establish uniformity across the full chip area and 300 mm wafer diameter.
Depth-of-focus requirements for 248 nm DUV and 193 nm immersion lithography (DOF ±50–80 nm) are far tighter than for earlier g-line (436 nm) or i-line (365 nm) exposure systems (DOF ±200–500 nm). Local planarization techniques were adequate for nodes >0.5 µm; they are insufficient for anything below. Only CMP’s global planarization capability satisfies the uniformity requirements of sub-100 nm nodes.
The following sections provide in-depth technical descriptions of each major planarization technique, including process conditions, achievable planarity, representative applications, and the reasons for each technique’s limitations.
02Thermal Oxide Reflow (BPSG / PSG)
Thermal oxide reflow exploits the viscous flow behavior of doped silicate glass films at elevated temperatures. Borophosphosilicate glass (BPSG) — a CVD-deposited film containing both boron (B, typically 3–5 wt%) and phosphorus (P, 4–8 wt%) — has a reflow temperature of 850–950°C, substantially lower than undoped SiO₂ (~1600°C). At these temperatures, the viscosity of BPSG drops sufficiently for the glass to flow under surface tension forces, rounding and smoothing surface steps.
Process Mechanism and Conditions
BPSG is deposited at 400–450°C by PECVD or SACVD (sub-atmospheric CVD) over the pre-metal dielectric (PMD) module — above the poly gate but below the first metal layer. After deposition, the wafer is annealed in a nitrogen ambient at 850–950°C for 20–40 minutes. Surface tension drives the glass to flow: sharp 90° step edges at gate sidewalls are converted to gradual slopes (45–60°), reducing the maximum step height at that feature by 40–70% and providing local planarity that improves step coverage for subsequent barrier metal and tungsten plug deposition.
Limitations and Obsolescence at Advanced Nodes
BPSG reflow provides only local planarization — it smooths the profile of individual steps but cannot correct accumulated topographic variation across the chip. Furthermore, the 850–950°C anneal temperature is incompatible with: (1) metal gates (Ni, W, TiN, TaN melting or phase change); (2) NiSi silicides formed before the PMD step (stability limit ~750°C); and (3) strained silicon and SiGe channels sensitive to dopant redistribution at high temperatures. As a result, BPSG reflow disappeared from leading-edge logic process flows below 130 nm and is today confined to mature analog, power device, and sensor fabrication at 0.18 µm and above.
BPSG reflow remains in active use at 200 mm fabs producing analog ICs, automotive sensors, MEMS devices, and BCD (Bipolar-CMOS-DMOS) power management chips — applications where the high-temperature budget is acceptable and the cost of CMP steps must be minimized.
03Spin-on-Glass (SOG)
Spin-on-Glass materials are liquid precursor solutions — typically organosilicate or inorganic silicate compounds dissolved in organic solvents — that are spun onto the wafer surface at 1,000–5,000 rpm and then thermally cured to form a solid SiO₂-like film. The spin-coating process naturally produces a globally smooth top surface through the same capillary flow mechanism used for photoresist application: the liquid fills surface recesses preferentially before the solvent evaporates, leaving a surface that is locally flatter than the underlying topology.
Process Mechanism
SOG solution is dispensed in the center of a rotating wafer. Centrifugal force spreads the liquid across the wafer surface into a thin film (typically 100–500 nm final thickness after cure). During spin-on, the liquid preferentially fills the surface recesses adjacent to metal lines due to capillary forces, providing a locally planarizing effect. After spin, the wafer is baked at 150–250°C (soft cure) to evaporate solvent, then cured at 400–450°C (hard cure) to fully convert the organic silicate precursor to dense SiO₂.
Types of SOG
- Inorganic (silicate) SOG: Based on tetraethyl orthosilicate (TEOS) or silicate ester in alcohol solvents. Forms dense SiO₂ after cure. Low carbon content (<1%). Prone to cracking for films thicker than ~200 nm due to tensile stress on cure shrinkage.
- Organic (siloxane) SOG: Based on methylsiloxane or phenylsiloxane polymers. Forms a silica–carbon hybrid network after cure. Less prone to cracking, tolerates thicker deposition (~500 nm). Lower dielectric constant (k ~ 2.7–3.0 vs. 4.0 for thermal SiO₂). Used as an early low-k ILD material in the late 1990s and early 2000s.
- Hydrogen silsesquioxane (HSQ) / Methyl silsesquioxane (MSQ): Advanced cage-network siloxane materials with k values down to ~2.2. Used as ultra-low-k ILD in sub-130 nm processes before being replaced by CVD-deposited porous low-k materials.
Limitations
SOG provides only local planarization — the coating material pools in recesses adjacent to nearby features (within 2–5 µm) but follows the large-scale topographic trends of the underlying surface. Long-range wafer variation is not corrected. Additionally, thick SOG films are mechanically weak and prone to cracking under CTE mismatch stress during thermal cycling. SOG reliability concerns (moisture absorption, outgassing, via poisoning from organic decomposition) led to its replacement by CVD-deposited low-k dielectrics and CMP in advanced nodes.
04Resist Etch-Back Planarization
Resist etch-back planarization exploits the flow properties of photoresist to create a locally planar surface, then uses a dry etch process to transfer that planarity into the underlying dielectric film. It was widely used for ILD planarization at the 0.5–1 µm generation and remains a useful technique for specific applications in MEMS and sensor manufacturing.
Process Flow
- Dielectric deposition: A conformal CVD oxide or BPSG is deposited over the patterned metal or poly layer, conformally reproducing the underlying topography.
- Photoresist spin-coat: A thick (~1.5–3 µm) photoresist film is spun over the dielectric. The viscous resist flows to fill the surface recesses, producing a much flatter top surface than the underlying dielectric — though not perfectly flat (resist still exhibits some “bias” toward the underlying features for very narrow or deep recesses).
- Anisotropic RIE etch-back: A fluorine-based RIE process (CF₄/O₂ or SF₆/O₂) etches both the resist and the oxide simultaneously. The etch chemistry is tuned to achieve a 1:1 oxide-to-resist selectivity — so the resist and oxide are removed at equal rates. As the resist is consumed, its planar top surface is transferred into the oxide below, producing a planarized dielectric surface.
- Result: The ILD surface after etch-back exhibits ~50–70% step height reduction compared to the conformal as-deposited surface, providing useful local planarization.
Limitations
Pattern density dependence is the fundamental limitation of resist etch-back. In regions of different pattern density (dense metal arrays vs. isolated lines vs. field areas), the resist surface height above the dielectric varies depending on how well the resist fills the local topology. This produces systematic etch-back depth variation across the chip, leaving residual step heights that grow with increasing chip complexity. Resist etch-back is also limited to <0.5 µm feature sizes by the resist flow behavior and is incompatible with aggressive CD scaling.
05HDP-CVD: Gap Fill with Moderate Planarization
High-Density Plasma CVD (HDP-CVD) is a simultaneous deposition and sputter-etch process used primarily for dielectric gap fill in STI and IMD applications. An RF-biased plasma simultaneously deposits SiO₂ from SiH₄ and O₂ precursors and physically sputters the growing film from horizontal surfaces by argon ion bombardment. This combined action preferentially builds up material in the trench or gap (where the sputter erosion is geometrically reduced) while preventing the “bread-loafing” overburden that conventional CVD produces at feature corners.
HDP-CVD achieves void-free gap filling in trenches with aspect ratios up to 3:1–5:1, producing a partially planarized surface with significantly less overburden step height than conformal CVD. However, it does not achieve global planarization — large-scale height variation across pattern density transitions remains, and HDP-CVD surfaces still require a CMP step for final global planarization in STI applications.
06Electrochemical Planarization (ECP)
Electrochemical Planarization applies a controlled electrochemical potential to the wafer surface in an electrolyte solution to selectively dissolve metal from elevated surface regions. The mechanism relies on the fact that current density is highest at protruding surface features (analogous to lightning rod geometry), producing preferential dissolution at peaks and leaving recesses untouched. ECP has been demonstrated for copper film planarization at the wafer scale, producing smoother starting surfaces for subsequent copper CMP steps.
ECP is not a stand-alone planarization technique for IC manufacturing — it is only applicable to conductive surfaces, it provides only local-to-moderate planarization, and it cannot address the full overburden removal required in damascene Cu CMP. Its current production relevance is primarily as a “pre-CMP leveling” step that reduces the incoming step height for the copper bulk removal CMP, potentially extending pad life and reducing slurry consumption. As of June 2026, ECP pre-treatment remains a niche process at select advanced BEOL facilities.
07Chemical Mechanical Planarization: The Global Standard
CMP differs categorically from all other planarization techniques in one property: its ability to achieve global planarization — uniform surface flatness across the full die and full 300 mm wafer. This property stems from the self-leveling mechanism built into the process physics (described by Preston’s equation): elevated features experience higher contact pressure against the compliant polishing pad, resulting in higher material removal rates that drive the entire surface toward a single plane.
No deposition, reflow, spin-coating, or etch-back technique offers this self-leveling behavior over long spatial distances. All non-CMP techniques replicate or partially smooth the underlying topography; CMP actively corrects it. This distinction, combined with the scalability of CMP to sub-10 nm film thickness control and WIWNU below 1%, makes it irreplaceable for all critical planarization applications at leading-edge nodes.
For a complete process-level discussion of CMP, including equipment, step-by-step process flow, endpoint detection, and defect modes, see our dedicated CMP Process Steps guide.
08Master Comparison Table: All Planarization Techniques
| Technique | Mechanism | Planarity Scale | Process Temp. | Compatible Node | Still Used (2026)? |
|---|---|---|---|---|---|
| BPSG Thermal Reflow | Viscous glass flow | Local | 850–950°C | ≥ 0.18 µm | Yes — legacy, power |
| Spin-on-Glass (SOG) | Liquid capillary fill + cure | Local | 400–450°C | ≥ 0.13 µm | Limited — sensor, MEMS |
| Resist Etch-Back | Resist flow + 1:1 RIE | Local–Moderate | Room temp + 150°C | ≥ 0.5 µm | Limited — MEMS, analog |
| HDP-CVD | Deposition + sputter etch | Modéré | 400–550°C | All (gap fill only) | Yes — STI gap fill before CMP |
| Electrochemical (ECP) | Selective electrochemical dissolution | Local | Room temp | Metal films only | Niche — pre-Cu CMP leveling |
| CMP | Chemical + mechanical removal | Global ✓ | 20–25°C | All — required at <0.35 µm | Yes — all advanced nodes |
Detailed Performance Metrics Comparison
| Technique | WIWNU Achievable | Step Height Reduction | Surface Roughness (Ra) | Débit | Consumable Cost |
|---|---|---|---|---|---|
| BPSG Reflow | 5–15% | 40–70% (local) | 2–10 nm | High (batch furnace) | Faible |
| SOG | 5–20% | 30–60% (local) | 1–5 nm | High (track system) | Moyen |
| Resist Etch-Back | 8–25% | 40–70% (local) | 2–8 nm | Moyen | Low–Medium |
| HDP-CVD | 5–15% | 50–80% (local) | 3–10 nm | Moyen | Faible |
| ECP | 10-20% | 20–50% (local) | 5–20 nm | Low–Medium | Moyen |
| CMP | <1% | >99% (global) | 0.1–1 nm | Medium (WPH 40–80) | High (slurry + pad) |
09Technique Selection Guide for Process Engineers
Selecting the correct planarization technique requires balancing planarity requirements, thermal budget, material compatibility, throughput, and cost. The following decision framework covers the most common manufacturing scenarios:
Scenario 1: Legacy / Mature Node (>0.18 µm), PMD Planarization
Use BPSG thermal reflow if the thermal budget permits (no NiSi, no metal gate, no strained Si). Provides adequate local planarization at low cost for pre-metal dielectric at 0.18 µm and above. Supplement with a light CMP step if WIWNU specification is tighter than 10%.
Scenario 2: STI Dielectric Fill at Any Node
HDP-CVD for void-free gap fill followed by CMP for global planarization. HDP-CVD handles the gap fill challenge (AR 3:1–5:1 for STI trenches); CMP handles the critical global planarization and oxide/nitride selectivity (ceria slurry). These two techniques are complementary, not competitive.
Scenario 3: ILD Planarization at Sub-0.35 µm
CMP is the only choice. SOG and etch-back do not provide the WIWNU or step height reduction required for sub-350 nm optical lithography. PECVD-deposited TEOS oxide or FSG (for k < 3.7) followed by CMP with colloidal silica slurry is the standard approach.
Scenario 4: Copper Damascene BEOL
ECP pre-leveling (optional, for thick Cu overburden reduction) followed by two-step copper CMP (bulk Cu removal, then barrier clearing). SOG or reflow-based approaches are fundamentally incompatible with copper metallization chemistry. CMP is mandatory.
Scenario 5: MEMS / Sensor / Specialty
Resist etch-back and SOG remain valid options where: (a) the topography requirements are moderate (WIWNU 5–15% is acceptable); (b) the thermal budget is flexible; (c) minimizing process step count is more important than ultimate planarity; and (d) the device operates at feature sizes >1 µm.
Scenario 6: Advanced Node (<10 nm) — All Modules
CMP is non-negotiable for every global planarization module: STI, ILD, W contact, Cu damascene, replacement metal gate, nanosheet release, and hybrid bonding surface preparation. At 2 nm (June 2026), each of these modules has WIWNU specifications of ≤1%, achievable only by CMP.
CMP Consumables for Every Planarization Application
JEEZ manufactures CMP polishing slurries, polishing pads, and absorption films engineered for STI, ILD, tungsten, and copper CMP modules. Direct manufacturer. Global supply. Contact our team to discuss your specific process needs.
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