Polishing Templates for Glass Wafers & Ceramic Substrates: Key Considerations
Glass and ceramic substrates span the widest thickness range, the most varied chemistries, and the most diverse geometries of any substrate category. Getting the polishing template right requires understanding exactly which material you are polishing — and why a single “glass template” specification cannot serve all applications.
Glass & Ceramic: The Widest Template Variable Range
Every substrate category discussed in this series — silicon, SiC, GaAs, InP, sapphire — involves at least one sharply defined polishing challenge. Silicon templates need tight TTV control. SiC needs chemical resistance. GaAs and InP need fracture protection. In each case, a clear primary engineering requirement drives the template specification.
Glass and ceramic substrates do not have a single primary challenge. They have the most diverse range of physical properties, chemical compositions, and geometric forms of any substrate category, and the relevant template parameters shift significantly from one material to the next. Borosilicate glass polishes at nearly the same conditions as silicon. Fused silica requires acidic slurry and chemical-resistant carrier plates. Alumina ceramic is nearly as hard as sapphire. AlN has unusual thermal sensitivity. LTCC is a composite material with different polishing dynamics entirely. And ceramic substrates frequently come in non-circular shapes that require custom work-hole geometry rather than the standard circular pocket used for wafers.
The unifying theme — and the reason this entire category merits dedicated treatment — is that glass and ceramic substrates almost always arrive with non-standard thicknesses and dimensional specifications that differ from semiconductor wafer standards, making custom work-hole depth calculation unavoidable. Understanding the 6-parameter specification process is especially important for glass and ceramic applications precisely because every order is effectively custom.
The Non-Standard Thickness Challenge
Semiconductor silicon wafers are produced to tightly standardized thicknesses defined by SEMI standards: 725 µm for 200 mm wafers, 775 µm for 300 mm wafers, with incoming thickness tolerance of ±25 µm for prime wafers. These standards make it possible to design template work-hole depths from a catalog, with minor adjustments for the specific carrier head and polishing conditions.
Glass wafers are not produced to these standards. They come from a different supply chain — glass manufacturers working to optical or MEMS specifications rather than SEMI standards — with thicknesses ranging from 0.3 mm to 2.0 mm and incoming tolerances of ±25 µm to ±100 µm depending on the glass type and manufacturer. Ceramic substrates are even more variable: green-state sintered ceramics arrive with post-sinter thickness variation of ±50–150 µm that must be accounted for in the template design.
The consequence is that every glass and ceramic polishing template is effectively a custom order. There is no standard work-hole depth that works for “glass wafers” — the depth must be calculated specifically for the combination of incoming substrate thickness, target final thickness, backing pad compression, and process conditions for that specific application. This is not a complexity to be managed around; it is a fundamental characteristic of the category that requires providing accurate substrate dimensional data when ordering templates.
Work-Hole Depth Formula for Glass & Ceramic Substrates
The work-hole depth calculation for glass and ceramic substrates follows the same fundamental relationship as all polishing templates, but the larger thickness variability of these substrates makes each term in the formula more consequential — and getting the calculation wrong has a larger impact than it would for standardized silicon wafers.
Overpolish allowance: amount of material removed past target thickness to reach surface quality spec — typically 0–5 µm for glass final polish.
Practical Calculation Example
Consider a 150 mm borosilicate glass wafer with incoming nominal thickness 700 µm (tolerance ±50 µm), target final thickness 500 µm, backing pad compression of 12 µm at 3 psi, and overpolish allowance of 3 µm for surface finish:
Work-hole depth = 500 + 12 − 3 = 509 µm
The incoming thickness of 700 µm enters the calculation indirectly: the polishing recipe removes 700 − 500 = 200 µm of material. The template work-hole depth of 509 µm ensures the wafer sits at the correct mechanical position relative to the polishing pad for the final 500 µm target thickness. The ±50 µm incoming thickness tolerance means that lot-to-lot thickness variation must be tracked — if an incoming lot arrives nominally 30 µm thinner than spec (670 µm), the same template will remove only 161 µm instead of 200 µm to reach the 509 µm mechanical stop, requiring recipe time adjustment to compensate.
Borosilicate Glass Wafers
Borosilicate Glass (e.g., Schott D263, Corning 7740 / Pyrex)
Borosilicate glass is the most forgiving of the glass/ceramic substrates from a template design perspective. Its hardness is comparable to silicon, its fracture toughness is similar to silicon prime wafers, and its primary polishing slurry — alkaline colloidal silica at pH 9–12 — is compatible with FR-4 carrier plates at moderate cycle counts and fully compatible with G-10 and CXT for extended production use.
The primary template engineering challenge for borosilicate glass is not chemistry or fracture risk but thickness diversity. Borosilicate glass wafers for MEMS applications arrive at thicknesses from 300 µm (for thinned substrates) to 1,100 µm (for rigid carrier applications), compared to the 625–775 µm range typical for semiconductor wafers. Each thickness requires a custom work-hole depth calculation. Additionally, through-glass via (TGV) substrates often have a target post-polish thickness specified to ±5 µm tolerance for via depth control — a flatness requirement that demands the same work-hole depth precision as advanced semiconductor applications.
Fused Silica Wafers
Fused Silica / Fused Quartz (SiO₂ amorphous)
Fused silica presents a different set of template challenges than borosilicate glass. Its extremely low CTE (0.55 × 10⁻⁶/°C, compared to 3.3 × 10⁻⁶/°C for borosilicate) makes it dimensionally ultra-stable — which is exactly why it is used for photomask blanks and EUV lithography components where sub-nm flatness must be maintained across thermal cycling. This low CTE also means that fused silica substrates are extremely sensitive to thermally-induced stress during polishing: any temperature gradient across the substrate during polishing creates differential expansion stress that can exceed the fracture toughness locally and produce subsurface cracking invisible to visual inspection but detectable in post-polish interferometric flatness measurements.
Fused silica polishing — particularly for photomask blank applications — uses cerium oxide (CeO₂) slurry or mixed CeO₂/SiO₂ slurry at mildly acidic to near-neutral pH (4–7). This pH range is marginal for FR-4 carrier plates in extended production use and requires G-10 minimum. The surface roughness targets for photomask blank polishing (Ra < 0.1 nm, comparable to silicon prime wafer spec) impose the same demanding template flatness requirements as advanced semiconductor CMP. Work-hole depth precision of ±3 µm and carrier plate bow of ≤5 µm are required to meet these surface specifications.
Alumina (Al₂O₃) Ceramic Substrates
Alumina Ceramic (96–99.6% Al₂O₃)
Alumina ceramic substrates are among the hardest materials routinely polished in the electronic substrate market, with Mohs hardness of 9.0 — equal to sapphire and exceeded only by SiC and diamond. This hardness has direct consequences for template specification: backing pad hardness must be high enough to maintain pressure uniformity under the elevated process pressures (3–6 psi) required to achieve acceptable removal rates with diamond abrasive slurry, and carrier plate material must resist the acidic diamond slurry chemistry that FR-4 cannot tolerate.
Alumina ceramics arrive from sintering with relatively wide thickness variation — ±50–150 µm is typical for standard-grade substrates — compared to the ±5–10 µm of semiconductor prime wafers. This variation must be measured and accounted for in work-hole depth specification. Many alumina polishing applications require a target post-polish TTV of ≤10–20 µm, which is achievable only if the template work-hole depth is correctly matched to the actual incoming substrate thickness distribution. Using a nominal work-hole depth without lot-specific thickness adjustment produces systematic TTV patterns correlated to the thickness variation within the lot.
Alumina substrates also frequently have non-circular geometries — squares, rectangles, and custom shapes — which require custom work-hole shapes rather than circular pockets. This is covered in detail in Section 9.
Aluminum Nitride (AlN) Substrates
Aluminum Nitride (AlN)
Aluminum nitride is selected for its exceptional thermal conductivity — the highest of any practical electronic substrate at 170–230 W/m·K — which makes it essential for high-power LED packages and RF power amplifiers where heat dissipation is the primary design constraint. Its polishing requirements are unlike any other substrate in this guide because of a critical chemical property: AlN reacts with water through hydrolysis — AlN + 3H₂O → Al(OH)₃ + NH₃ — producing ammonia gas and consuming the substrate surface in any aqueous polishing environment. This hydrolysis reaction is not a slow corrosion process; it is fast enough to cause measurable surface damage within minutes in standard aqueous slurry at room temperature.
AlN polishing therefore requires either non-aqueous polishing media (organic-solvent-based diamond suspensions) or passivated aqueous slurry with pH adjustment and inhibitor chemistry that minimizes water activity at the substrate surface. This chemistry requirement dictates the carrier plate material: standard aqueous slurry inhibitor systems often use organic acid passivants at pH 4–6, which are incompatible with FR-4. Non-aqueous polishing media may be compatible with G-10 but require verification; CXT-grade is the safe choice for production AlN polishing regardless of the specific slurry chemistry.
Template design for AlN also benefits from minimizing the time the substrate spends wetted after polishing. AlN polishing templates should be specified with a smooth, non-porous carrier plate surface (CXT satisfies this; G-10 has slightly higher surface porosity from exposed fiber) to minimize slurry retention at the template surface that would extend AlN hydrolysis exposure after the polishing cycle ends.
LTCC & Thick-Film Ceramic Substrates
LTCC & Thick-Film Ceramics (Low-Temperature Co-fired Ceramic)
LTCC substrates are co-fired glass-ceramic composites with buried metal conductors (typically silver or gold), produced in panel form that is then singulated. Their polishing requirements differ from the other ceramics in this guide because LTCC contains both a glass-ceramic matrix et metal conductors, and polishing must achieve surface planarity without preferentially removing either the ceramic or the metal — a selective polishing problem similar to CMP damascene metal planarization.
Post-fire LTCC panels arrive with surface topography arising from the differential sintering shrinkage of the glass-ceramic matrix versus the embedded metal layers. The polishing goal is to planarize this topography to within ±5–10 µm across the panel for reliable die bonding and interconnect processes. Because LTCC is softer than pure alumina (Mohs ~5–6 vs 9 for alumina), lower process pressures (1.5–3 psi) and softer backing pads (Shore A 50–65) are appropriate — harder pads at higher pressure cause preferential removal of the softer glass-ceramic matrix relative to the metal conductors, worsening the planarity problem rather than solving it.
LTCC panel formats (114 × 114 mm or custom sizes) are non-circular and non-standard, requiring custom rectangular work-hole geometry in the polishing template. The work-hole depth must be specified based on the post-fire panel thickness, which itself varies with the number of co-fired layers and firing batch conditions. Obtaining a post-fire thickness measurement from at least 5 sample panels per production lot is the recommended input for work-hole depth specification.
Non-Circular & Custom-Shape Substrates
One of the most frequent template engineering questions from glass and ceramic polishing customers concerns non-circular substrate shapes. Semiconductor wafers are circular by definition, and the entire standard polishing template ecosystem is built around circular work holes. But glass and ceramic substrates routinely come in squares, rectangles, and custom polygonal shapes — and these require custom work-hole geometry that is standard practice for specialized template manufacturers but unavailable from suppliers whose product line covers only semiconductor wafers.
Engineering Requirements for Non-Circular Work Holes
Non-circular work holes require the same clearance engineering as circular ones — the gap between the substrate perimeter and the work-hole wall must be 0.25–0.50 mm to prevent edge contact during polishing while constraining the substrate from lateral movement. For rectangular substrates, this means specifying the work-hole dimensions as substrate length + 0.50 mm × substrate width + 0.50 mm. Corner geometry requires a radius (typically 0.5–1.0 mm) to match the substrate’s corner chamfer or to prevent stress concentration at sharp internal corners that could initiate carrier plate cracking under cyclic polishing load.
Multi-cavity templates for small ceramic substrates — for example, a carrier holding six 25 × 25 mm alumina substrates simultaneously — require precise inter-cavity spacing and equal work-hole depth across all cavities. The depth uniformity across cavities (≤5 µm variation between the deepest and shallowest cavity on a single carrier) directly controls the TTV uniformity between substrates polished simultaneously, and is verified by CMM measurement of each cavity before dispatch. For non-circular multi-cavity templates, providing a dimensioned engineering drawing of the substrate and the desired cavity layout at time of order is the most efficient way to specify the template geometry.
Slurry Chemistry & Template Material Selection Table
| Substrate | Slurry Chemistry | pH Range | FR-4 | G-10 | CXT |
|---|---|---|---|---|---|
| Borosilicate glass | Colloidal silica, alkaline | 9–12 | Acceptable | Bon | Recommended |
| Borosilicate glass | CeO₂, mildly acidic | 5–8 | Marginal | Bon | Recommended |
| Borosilicate glass | NH₄F / BHF (etch polish) | 4–6 | Not suitable | Not suitable | Required |
| Fused silica | CeO₂ / SiO₂ acidic | 4–7 | Marginal | Bon | Recommended |
| Alumina ceramic | Diamond abrasive, acidic | 4-8 | Not suitable | Bon | Recommended |
| AlN substrate | Non-aqueous / passivated | 4–7 | Not suitable | Marginal | Required |
| LTCC / thick-film | Near-neutral silica | 7–10 | Acceptable | Bon | Recommended |
Full Specification Comparison
| Paramètres | Borosilicate Glass | Fused Silica | Alumina | AlN | LTCC |
|---|---|---|---|---|---|
| Carrier plate | FR-4 / G-10 | G-10 / CXT | G-10 / CXT | CXT | FR-4 / G-10 |
| Backing pad Shore A | 55–70 | 60–75 | 65–80 | 55–70 | 50-65 |
| Process pressure | 2–4 psi | 1.5–4 psi | 3–6 psi | 2–4 psi | 1.5–3 psi |
| Work-hole shape | Circular | Circular / square | Custom required | Custom required | Rectangular |
| Thickness input critical? | Yes — always | Yes — always | Yes — always | Yes — always | Yes — post-fire |
| Fluoride chemistry? | Possible — CXT only | Rare | No | No | No |
| Key challenge | Thickness diversity | Ra < 0.1 nm spec | Hardness + geometry | Hydrolysis risk | Metal + ceramic co-removal |
| Typical cycle life | 100–200 | 80–150 | 60–120 | 80–150 | 100–200 |
