CMPスラリーの種類酸化物、STI、銅、タングステン、その他
A comprehensive technical breakdown of every major CMP slurry category — covering formulation chemistry, key process parameters, application scope, and selection criteria for each type used in modern semiconductor manufacturing.
CMP slurry is not a single product category — it is a family of chemically distinct formulations, each engineered for a specific film material, process integration context, and performance target. Choosing the wrong slurry type for an application does not merely result in suboptimal performance; it can result in no measurable removal at all, catastrophic selectivity failure, or post-CMP defect density that renders wafers unsalvageable.
This article provides a systematic breakdown of every major CMP slurry type used in semiconductor manufacturing as of May 2026, from the well-established oxide and copper categories to the rapidly growing SiC and advanced packaging segments. For foundational background on CMP process mechanics, see: What Is CMP Slurry? A Complete Guide to Chemical Mechanical Planarization.
1. Why Slurry Type Matters: The Chemistry-Application Match
Every CMP slurry is a system in which three variables must be simultaneously optimized: the target material being removed, the stop layer at which polishing should cease, and the surface quality required for subsequent processing steps. These three constraints drive every formulation decision — abrasive type, particle size, pH, oxidizer chemistry, and additive package.
The concept of selectivity is central to understanding why different slurry types exist. Selectivity is the ratio of removal rates between two different materials under identical process conditions. A slurry with high oxide-to-nitride selectivity (e.g., 50:1) removes oxide fifty times faster than nitride — which is exactly what is needed for STI CMP, where polishing must stop precisely at the nitride surface. A copper CMP slurry, by contrast, needs near-unity selectivity between the copper conductor and the surrounding dielectric in some steps, and very high copper-to-barrier selectivity in others.
Key principle: There is no universal CMP slurry. A formulation optimized for maximum oxide removal rate will typically have near-zero selectivity over nitride, making it completely unsuitable for STI applications. Matching slurry chemistry to the specific film stack and process integration requirements is the foundational step in any CMP consumable selection process.
2. Oxide and STI CMP Slurry
Oxide CMP slurries are the largest single category by application breadth — used for ILD planarization between every metal layer in the back-end stack, and critically for STI CMP in the front-end of line. Ceria-based formulations dominate this category because of a unique surface chemistry advantage: Ce⁴⁺ ions form direct Ce–O–Si bonds with silicon dioxide surfaces, enabling a chemical pulling mechanism that delivers far higher removal rates at lower abrasive concentration than silica-based alternatives.
For STI applications, the critical performance parameter is oxide:nitride selectivity. The silicon nitride layer serves as the CMP stop layer — if the slurry removes nitride nearly as fast as oxide, the process window is too narrow for high-volume manufacturing. Premium STI slurries achieve selectivity ratios of 50:1 to over 200:1, depending on formulation and process conditions, giving process engineers the margin they need to achieve consistent within-die planarity across large wafer areas.
JEEZ oxide CMP slurries are formulated for both high-removal-rate ILD applications and high-selectivity STI applications, with additive packages that suppress nitride removal while maintaining stable particle dispersion across the process window.
3. Copper (Cu) CMP Slurry
Copper CMP is the most chemically sophisticated CMP application in mainstream device fabrication. It typically proceeds in three stages, each with its own slurry chemistry: Stage 1 removes the bulk of the copper overfill at high removal rate; Stage 2 clears the remaining copper and approaches the barrier layer with tight thickness control; Stage 3 removes the barrier (Ta/TaN) and equalizes the final surface. Each stage demands a different selectivity profile.
The central challenge in copper CMP is balancing three competing requirements: high copper removal rate, low corrosion of the copper surface during polishing, and precise control of dishing (the concave depression that forms in wide copper features when too much metal is removed) and erosion (thinning of the surrounding dielectric). Benzotriazole (BTA) serves as a corrosion inhibitor, forming a passivation film on the copper surface that modulates the effective removal rate and protects against galvanic corrosion at the metal-dielectric interface.
JEEZ copper CMP slurries cover all three stages of the damascene process, with formulations optimized for node-appropriate dishing and erosion targets and BTA concentrations tuned for different line/space ratios.
4. Tungsten (W) CMP Slurry
Tungsten CMP operates at acidic pH (typically 2–4), where hydrogen peroxide oxidizes tungsten metal to tungsten oxide (WO₃), a softer compound that is then mechanically abraded by alumina particles. The low pH is necessary to maintain an adequate oxidation rate on the tungsten surface — at neutral or alkaline pH, tungsten passivates rapidly and MRR collapses.
Alumina is selected as the abrasive for tungsten CMP because its hardness (Mohs 9) provides sufficient mechanical energy to abrade WO₃ at commercially useful removal rates. The trade-off is higher scratch risk compared to softer abrasives — making particle size distribution control and the suppression of agglomerates critical quality parameters. JEEZ tungsten CMP slurries use alumina particles with tightly controlled size distributions and surface modifications to minimize scratch defects while maintaining the removal rate needed for high-throughput manufacturing.
In 3D NAND manufacturing, tungsten CMP is among the highest-volume applications in the fab, with multiple W CMP steps required per wafer for each tier in the NAND stack. The tolerance for scratch defects is extremely low in this context, as scratches that propagate through multiple memory cell layers can cause correlated failures across many bits.
5. Barrier and Liner CMP Slurry
In copper damascene processes, a tantalum or tantalum nitride (Ta/TaN) barrier layer is deposited before the copper fill to prevent copper diffusion into the surrounding dielectric. After the copper CMP steps, this barrier layer must be removed — but with highly controlled selectivity to avoid over-polishing the copper interconnects below or the dielectric around them.
Barrier slurries are typically near-neutral pH formulations with colloidal silica abrasives and carefully balanced additive packages that deliver near-unity selectivity among copper, tantalum, and oxide. This is the most demanding selectivity control requirement in all of CMP: the slurry must remove Ta/TaN at a useful rate while simultaneously slowing down on copper (to prevent dishing) and slowing down on the dielectric (to prevent erosion). The three-way selectivity balance is achieved through combinations of organic inhibitors, surfactants, and precisely tuned pH.
Process note: Barrier CMP performance is extremely sensitive to incoming copper topography from the preceding stage-2 copper CMP step. Excessive copper residual topography entering the barrier step puts far greater demands on the barrier slurry’s ability to clear Ta/TaN uniformly without creating new Cu dishing. This inter-step dependency is why copper and barrier slurries should ideally be selected and optimized together as a system.
6. Silicon Wafer Polishing Slurry
Silicon wafer polishing uses colloidal silica at high pH, where hydroxide ions provide the chemical component of material removal through a hydration and dissolution mechanism on the silicon surface. At pH 10–11, the silica particles themselves are also chemically active, forming Si–O–Si bonds at the polishing interface that contribute to removal. The combination of chemical activity and gentle mechanical abrasion from well-dispersed, spherical silica particles produces the extremely smooth surfaces (Ra < 0.1 nm) required for epitaxial silicon deposition, gate oxide growth, and other demanding FEOL processes.
JEEZ silicon wafer polishing slurries are formulated with narrow particle size distributions to minimize surface roughness and haze, and are designed for stability over the extended polishing times characteristic of final-finish silicon wafer processing.
7. SiC and Wide-Bandgap Semiconductor Slurry
Silicon carbide’s extraordinary hardness — Mohs 9.5, just below diamond — makes it one of the most challenging substrates in the semiconductor industry to polish. Conventional silica and alumina slurries have MRRs of just 2–5 nm/min on SiC, which is completely impractical for production. Two approaches have emerged to address this: diamond abrasive slurries for high-MRR stock removal stages, and chemically enhanced ceria slurries with oxidizing additives for the final finishing stage where surface roughness becomes the primary target.
The oxidizer chemistry in SiC slurries serves to convert the hard SiC surface to softer SiO₂ and other oxidized products that are more readily abraded. Hydrogen peroxide, potassium permanganate, and other oxidizers are used depending on the stage and the degree of chemical assistance required. Achieving an epi-ready SiC surface (Ra < 0.3 nm, no scratches visible by AFM) typically requires a two- or three-stage polishing sequence with different slurry chemistries at each stage.
JEEZ has dedicated SiC polishing slurry formulations covering both the stock removal and final finishing stages. For full technical coverage of SiC CMP challenges and solutions, see: CMP Slurry for SiC Wafer Polishing: Challenges & Solutions.
8. Advanced Packaging CMP Slurry
Advanced packaging CMP encompasses a set of applications that do not exist in conventional front-end-of-line manufacturing, and which present unique challenges that standard slurry formulations are not designed to address. The three most important applications are: TSV (Through-Silicon Via) reveal, where silicon is back-ground and polished to expose the copper TSV tips; RDL (Redistribution Layer) planarization, where thick copper traces and dielectric must be co-planarized for subsequent layer buildup; and hybrid bonding surface preparation, where both copper and dielectric must achieve sub-nanometer roughness and atomic-level planarity for direct wafer-to-wafer bonding without solder.
JEEZ has developed commercial CMP slurry solutions for all three advanced packaging application categories. Our advanced packaging slurries address the specific challenges of thick copper removal at high MRR, multi-material planarization selectivity control, and the extreme surface quality requirements of hybrid bonding interfaces. For a full technical discussion, see: Advanced Packaging CMP: Slurry Requirements for 3D NAND & TSV Processes.
9. Emerging Types: Cobalt, Ruthenium, and Low-k
As semiconductor technology advances beyond the 5nm node, new materials are entering the interconnect stack that require dedicated CMP chemistries not well represented in existing commercial portfolios:
- コバルト（Co）CMP： Cobalt is being introduced as a liner material and, in some architectures, as the primary conductor in the lowest metal layers (M0/M1) of advanced logic devices. Cobalt requires slurries with very different oxidizer chemistry than copper — it is more easily corroded and requires careful pH control and inhibitor selection to prevent excessive galvanic attack. Commercial Co CMP slurries are available from several major suppliers as of 2026.
- Ruthenium (Ru) CMP: Ruthenium’s lower resistivity than copper at sub-10nm dimensions makes it a candidate for ultra-narrow interconnect lines at advanced nodes. Ru CMP is chemically challenging because ruthenium oxide (RuO₄) is volatile and potentially hazardous — requiring carefully designed slurry chemistry that avoids forming gaseous oxidation products at process conditions.
- Low-k and Ultra-low-k Dielectric CMP: Porous low-k dielectrics (k < 2.5) used in advanced BEOL interconnect stacks are mechanically fragile and chemically sensitive. Polishing them requires slurries with very low abrasive concentration, gentle particle morphology, and minimal chemical aggressiveness — essentially the opposite of a high-MRR oxide slurry. Formulating effective slurries for low-k materials while maintaining practical throughput remains an active area of industry development.
10. Quick Reference Comparison Table
| スラリータイプ | 主研磨材 | pH | Typical MRR | Key Selectivity | Main Application |
|---|---|---|---|---|---|
| Oxide / STI | セリア | 5–8 | 2,000–5,000 Å/min | Oxide > Nitride (50:1+) | ILD, STI planarization |
| Copper (Bulk) | Colloidal SiO₂ | 7-9 | 300-800 nm/分 | Cu > Barrier (10:1+) | Damascene Cu removal |
| Copper (Stage 2) | Colloidal SiO₂ | 7-9 | 50-150 nm/分 | Low Cu:Oxide selectivity | Cu clearing / thickness ctrl |
| Barrier (Ta/TaN) | Colloidal SiO₂ | 6–8 | 20–80 nm/min | Near-unity Cu:Ta:Oxide | Barrier removal after Cu |
| タングステン | アルミナ | 2-4 | 100–400 nm/min | W > Oxide (5–15:1) | Contact / via fill, NAND |
| Silicon Wafer | Colloidal SiO₂ | 10–11.5 | 50–300 nm/min | N/A (single material) | Bare Si final polish |
| SiC / WBG | Diamond / Ceria | Varies | 10–100 nm/min | 該当なし | Power device substrates |
| Advanced Packaging | SiO₂ / Cu-specific | Varies | 500–1,500 nm/min (TSV Cu) | Multi-material balance | TSV, RDL, hybrid bond |
For guidance on which slurry type is right for your specific process, see our selection framework article: How to Choose a CMP Slurry: Selection Guide for Semiconductor Engineers. For an overview of how the major global manufacturers cover these categories, see: Top CMP Slurry Manufacturers: Global Supplier Guide 2026.
Need Help Selecting the Right Slurry Type for Your Process?
JEEZ application engineers work with customers across all major CMP slurry categories — from mainstream oxide and copper to specialized SiC and advanced packaging applications. Contact us to discuss your specific film stack, process targets, and integration requirements.
Contact Our Experts →
